From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Subject: [PATCH v3 02/19] drm/i915/bmg: Define IS_BATTLEMAGE macro
Date: Tue, 30 Apr 2024 10:28:33 -0700 [thread overview]
Message-ID: <20240430172850.1881525-3-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com>
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Display code uses IS_BATTLEMAGE macro but the platform support doesn't
exist in i915. So fake IS_BATTLEMAGE macro defined to enable building
i915 code. We should make sure the macro parameter is used in the
always-false expression so that we don't run into "unused variable"
warnings from i915 builds if the IS_BATTLEMAGE() check is the only place
the i915 pointer gets used in a function.
While we're at it, also update the IS_LUNARLAKE macro to include the
parameter in the false expression for consistency.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ee0d7d5f135d..481ddce038b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -535,7 +535,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
-#define IS_LUNARLAKE(i915) 0
+/*
+ * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,
+ * so we need to define these even on platforms that the i915 base driver
+ * doesn't support. Ensure the parameter is used in the definition to
+ * avoid 'unused variable' warnings when compiling the shared display code
+ * for i915.
+ */
+#define IS_LUNARLAKE(i915) (0 && i915)
+#define IS_BATTLEMAGE(i915) (0 && i915)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
--
2.34.1
next prev parent reply other threads:[~2024-04-30 17:30 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 17:28 [PATCH v3 00/19] Enable display support for Battlemage Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 01/19] drm/i915/bmg: Lane reversal requires writes to both context lanes Radhakrishna Sripada
2024-04-30 17:28 ` Radhakrishna Sripada [this message]
2024-04-30 17:28 ` [PATCH v3 03/19] drm/i915/xe2hpd: Initial cdclk table Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 04/19] drm/i915/bmg: Extend DG2 tc check to future Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 05/19] drm/i915/xe2hpd: Properly disable power in port A Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address Radhakrishna Sripada
2024-05-03 3:24 ` Sripada, Radhakrishna
2024-04-30 17:28 ` [PATCH v3 07/19] drm/i915/xe2hpd: Add support for eDP PLL configuration Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 08/19] drm/i915/xe2hpd: update pll values in sync with Bspec Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 09/19] drm/i915/xe2hpd: Add display info Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 10/19] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 11/19] drm/i915/xe2hpd: Add max memory bandwidth algorithm Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 12/19] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 13/19] drm/i915/bmg: BMG should re-use MTL's south display logic Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 14/19] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 15/19] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 16/19] drm/xe/gt_print: add xe_gt_err_once() Radhakrishna Sripada
2024-05-03 18:34 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 17/19] drm/xe/device: implement transient flush Radhakrishna Sripada
2024-05-03 18:40 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 18/19] drm/i915/display: perform " Radhakrishna Sripada
2024-04-30 17:57 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 19/19] drm/xe/bmg: Enable the display support Radhakrishna Sripada
2024-04-30 17:49 ` Lucas De Marchi
2024-04-30 20:40 ` ✓ CI.Patch_applied: success for Enable display support for Battlemage (rev3) Patchwork
2024-04-30 20:40 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-30 20:41 ` ✓ CI.KUnit: success " Patchwork
2024-04-30 20:53 ` ✓ CI.Build: " Patchwork
2024-04-30 20:55 ` ✓ CI.Hooks: " Patchwork
2024-04-30 20:57 ` ✗ CI.checksparse: warning " Patchwork
2024-05-01 3:04 ` ✗ CI.FULL: failure " Patchwork
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