From: Tony Nguyen <anthony.l.nguyen@intel.com>
To: Karol Kolacinski <karol.kolacinski@intel.com>,
<intel-wired-lan@lists.osuosl.org>
Cc: Michal Michalik <michal.michalik@intel.com>,
Sergey Temerkhanov <sergey.temerkhanov@intel.com>,
netdev@vger.kernel.org,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Jacob Keller <jacob.e.keller@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH v4 iwl-next 07/12] ice: Introduce ETH56G PHY model for E825C products
Date: Wed, 3 Apr 2024 16:33:45 -0700 [thread overview]
Message-ID: <b12ea5e0-5ef2-b6ef-76cc-89b3887e370e@intel.com> (raw)
In-Reply-To: <20240329161730.47777-21-karol.kolacinski@intel.com>
On 3/29/2024 9:09 AM, Karol Kolacinski wrote:
> From: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
>
> E825C products feature a new PHY model - ETH56G.
>
> Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
> analogous to E82X and E810 ones with addition of a few HW-specific
> functionalities for ETH56G like one-step timestamping.
>
> It ensures correct PTP initialization and operation for E825C products.
>
> Co-developed-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Co-developed-by: Michal Michalik <michal.michalik@intel.com>
> Signed-off-by: Michal Michalik <michal.michalik@intel.com>
> Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
...
> +/**
> + * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
> + * @a: multiplier value
> + * @b: multiplicand value
> + */
> +static inline u32 mul_u32_u32_fx_q9(u32 a, u32 b)
> +{
> + return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
> +}
Please don't use 'inline' in c files.
> +
> +/**
> + * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
> + * @a: first value
> + * @b: second value
> + */
> +static inline u32 add_u32_u32_fx(u32 a, u32 b)
> +{
> + return lower_32_bits(((u64)a + b));
> +}
Here too.
...
> +
> +/**
> + * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
> + * @hw: pointer to the HW struct
> + * @port: port to configure
> + * @spd: link speed
> + * @cfg: structure to store output values
> + * @fc: FC-FEC enabled
> + * @rs: RS-FEC enabled
> + */
> +static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
> + enum ice_eth56g_link_spd spd,
> + const struct ice_eth56g_mac_reg_cfg *cfg,
> + bool fc, bool rs)
> +{
> + u32 rx_offset, tx_offset, bs_ds;
> + bool onestep, sfd;
> +
> +#ifdef SWITCH_MODE
> + onestep = ice_is_bit_set(hw->ptp.phy.eth56g.onestep_ena, port);
> + sfd = ice_is_bit_set(hw->ptp.phy.eth56g.sfd_ena, port);
> +#else /* SWITCH_MODE */
> + onestep = hw->ptp.phy.eth56g.onestep_ena;
> + sfd = hw->ptp.phy.eth56g.sfd_ena;
> +#endif /* SWITCH_MODE */
I don't believe this is supposed to be here?
> + bs_ds = cfg->rx_offset.bs_ds;
> +
> + if (fc)
> + rx_offset = cfg->rx_offset.fc;
> + else if (rs)
> + rx_offset = cfg->rx_offset.rs;
> + else
> + rx_offset = cfg->rx_offset.no_fec;
> +
...
> +/**
> + * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
> + * @hw: pointer to the HW struct
> + * @port: the timestamp port
> + * @ena: enable or disable interrupt
> + * @threshold: interrupt threshold
> + *
> + * Configure TX timestamp interrupt for the specified port
> + */
> +int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
> +{
> + int err;
> + u32 val;
> +
> + err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
> + if (err)
> + return err;
> +
> + if (ena) {
> + val |= PHY_TS_INT_CONFIG_ENA_M;
> + val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
> + val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
> + } else {
> + val &= ~PHY_TS_INT_CONFIG_ENA_M;
> + }
> +
> + err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
> + return err;
return ice_write_ptp_reg_eth56g()
> +}
> +
...
> +/**
> + * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
> + * @hw: pointer to HW struct
> + *
> + * Perform PHC initialization steps specific to E82X devices.
> + */
> +static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
> +{
> + int err;
> +
> + ice_sb_access_ena_eth56g(hw, true);
> + /* Initialize the Clock Generation Unit */
> + err = ice_init_cgu_e82x(hw);
> +
> + return err;
return ice_init_cgu_e82c();
Also no need for local var after that.
Please check the the patches to ensure that they aren't assigning a
local var to be returned immediately after (I saw more instances).
> +}
next prev parent reply other threads:[~2024-04-03 23:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 16:09 [Intel-wired-lan] [PATCH v4 iwl-next 00/12] Introduce ETH56G PHY model for E825C products Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 01/12] ice: Introduce ice_ptp_hw struct Karol Kolacinski
2024-04-03 23:25 ` Tony Nguyen
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 02/12] ice: Introduce helper to get tmr_cmd_reg values Karol Kolacinski
2024-04-03 23:25 ` Tony Nguyen
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 03/12] ice: Implement Tx interrupt enablement functions Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 04/12] ice: Add PHY OFFSET_READY register clearing Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 05/12] ice: Move CGU block Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 06/12] ice: Introduce ice_get_base_incval() helper Karol Kolacinski
2024-04-03 23:29 ` Tony Nguyen
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 07/12] ice: Introduce ETH56G PHY model for E825C products Karol Kolacinski
2024-04-03 23:33 ` Tony Nguyen [this message]
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 08/12] ice: Change CGU regs struct to anonymous Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 09/12] ice: Add support for E825-C TS PLL handling Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 10/12] ice: Add NAC Topology device capability parser Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 11/12] ice: Support 2XNAC configuration using auxbus Karol Kolacinski
2024-03-29 16:09 ` [Intel-wired-lan] [PATCH v4 iwl-next 12/12] ice: Adjust PTP init for 2x50G E825C devices Karol Kolacinski
2024-03-29 16:23 ` [Intel-wired-lan] [PATCH v4 iwl-next 00/12] Introduce ETH56G PHY model for E825C products Tony Nguyen
2024-04-02 12:31 ` Kolacinski, Karol
2024-04-03 23:24 ` Tony Nguyen
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