From: "Kolacinski, Karol" <karol.kolacinski@intel.com>
To: "Lobakin, Aleksander" <aleksander.lobakin@intel.com>
Cc: Michal Michalik <michal.michalik@intel.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"Kitszel, Przemyslaw" <przemyslaw.kitszel@intel.com>,
"intel-wired-lan@lists.osuosl.org"
<intel-wired-lan@lists.osuosl.org>
Subject: Re: [Intel-wired-lan] [PATCH v5 iwl-next 09/12] ice: Add support for E825-C TS PLL handling
Date: Thu, 4 Apr 2024 12:29:58 +0000 [thread overview]
Message-ID: <MW4PR11MB58005728FD74C12F9552E520863C2@MW4PR11MB5800.namprd11.prod.outlook.com> (raw)
In-Reply-To: <5238eaf3-cc47-470e-85ba-4930a2acbc15@intel.com>
From: Aleksander Lobakin <aleksander.lobakin@intel.com>
Date: Thu, 4 Apr 2024 13:11 +0200
[...]
> > +#define NAC_CGU_DWORD16_E825C 0x40
> > +union nac_cgu_dword16_e825c {
> > + struct {
> > + u32 synce_remndr : 6;
> > + u32 synce_phlmt_en : 1;
> > + u32 misc13 : 17;
> > + u32 tspll_ck_refclkfreq : 8;
> > + };
> > + u32 val;
> > +};
>
> Will this work on Big Endian systems?
I guess it won't, not sure about compiler behaviour.
It would probably work better with masks defined and le32_to_cpu().
[...]
Thanks,
Karol
next prev parent reply other threads:[~2024-04-04 12:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 9:09 [Intel-wired-lan] [PATCH v5 iwl-next 00/12] Introduce ETH56G PHY model for E825C products Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 01/12] ice: Introduce ice_ptp_hw struct Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 02/12] ice: Introduce helper to get tmr_cmd_reg values Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 03/12] ice: Implement Tx interrupt enablement functions Karol Kolacinski
2024-04-04 10:52 ` Alexander Lobakin
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 04/12] ice: Add PHY OFFSET_READY register clearing Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 05/12] ice: Move CGU block Karol Kolacinski
2024-04-04 11:08 ` Alexander Lobakin
2024-04-04 12:26 ` Kolacinski, Karol
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 06/12] ice: Introduce ice_get_base_incval() helper Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 07/12] ice: Introduce ETH56G PHY model for E825C products Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 08/12] ice: Change CGU regs struct to anonymous Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 09/12] ice: Add support for E825-C TS PLL handling Karol Kolacinski
2024-04-04 11:11 ` Alexander Lobakin
2024-04-04 12:29 ` Kolacinski, Karol [this message]
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 10/12] ice: Add NAC Topology device capability parser Karol Kolacinski
2024-04-04 9:09 ` [Intel-wired-lan] [PATCH v5 iwl-next 11/12] ice: Support 2XNAC configuration using auxbus Karol Kolacinski
2024-04-04 9:10 ` [Intel-wired-lan] [PATCH v5 iwl-next 12/12] ice: Adjust PTP init for 2x50G E825C devices Karol Kolacinski
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