From: Andrew Cooper <andrew.cooper3@citrix.com>
To: speck@linutronix.de
Subject: [MODERATED] Updated microperf tests
Date: Thu, 7 Mar 2019 14:26:04 +0000 [thread overview]
Message-ID: <e20dc092-9b46-201a-e5fc-4bf3e58815f2@citrix.com> (raw)
In-Reply-To: <8e57a8b6-15e7-9dc3-be10-15270e984e9d@citrix.com>
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Hello,
Intel analysed my CoffeeLake performance numbers, and put the
discrepancy down to being an early alpha build. Since my first email,
microcode for Skylake-SP has become available, and is in its production
form.
Like before, these are raw TSC cycles collected with RDTSCP, and are not
comparable with the raw Coffeelake numbers, because I haven't scaled
them by the TSC frequency.
Curiously, with Skylake-SP I see a difference in instruction latency
depending on whether it is operating in root mode or non-root mode. I
didn't observe this difference with CoffeeLake. (For reasons of ease of
my test environment, MSR_FLUSH_CMD is only measured in Non-Root mode.)
Pre microcode:
* VERW of NUL => Root: 70-74, Non-Root: 82-86 cycles
* VERW of %ds => Root: 36-40, Non-Root: 44-48 cycles
* MSR_FLUSH_CMD => Non-Root: 1070-1078 cycles
Post microcode:
* VERW of NUL => Root: 394-406, Non-Root: 384-390 cycles
* VERW of %ds => Root: 362-370, Non-Root: 352-360 cycles
* MSR_FLUSH_CMD => Non-Root: 1280-1288 cycles
So, in comparison to the Coffeelake very early alpha ucode, the numbers
now favour VERW of %ds in all cases, and the absolute hit of the extra
flushing has reduced (by far more than the delta between raw values).
Both of these are consistent with this being better optimised microcode,
and mean that the aforementioned guidance is accurate.
Thanks,
~Andrew
prev parent reply other threads:[~2019-03-07 15:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-23 18:26 [MODERATED] Some microperf tests Andrew Cooper
2019-02-23 19:30 ` [MODERATED] " Linus Torvalds
2019-02-23 20:42 ` Andrew Cooper
2019-02-24 14:23 ` Andi Kleen
2019-03-07 14:26 ` Andrew Cooper [this message]
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