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From: Thomas Gleixner <tglx@linutronix.de>
To: speck@linutronix.de
Subject: Re: [PATCH v4 8/8] [PATCH v4 8/8] Linux Patch #8
Date: Wed, 27 Jun 2018 15:05:02 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1806271459420.17787@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180623135446.010873334@localhost.localdomain>

On Sat, 23 Jun 2018, speck for konrad.wilk_at_oracle.com wrote:
> x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if required.
> +
> +	/*
> +	 * If we enforce flushing the L1D cache on every VMENTER lets use the
> +	 * MSR save list.
> +	 */
> +	if (vmx_l1d_cache_flush_req(&vmx->vcpu))
> +		if (vmentry_l1d_flush == 2)
> +			add_atomic_switch_msr(vmx, MSR_IA32_FLUSH_CMD,
> +					      L1D_FLUSH, 0, true);

That's broken when the CPU does not have the FLUSH MSR, unless I'm missing
something.

>  static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
> @@ -10079,7 +10095,7 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
>  	evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
>  		(unsigned long)&current_evmcs->host_rsp : 0;
>  
> -	if (vcpu->arch.flush_cache_req)
> +	if (vcpu->arch.flush_cache_req && vmentry_l1d_flush != 1)
>  		kvm_l1d_flush();

Huch? So above you use the MSR list for vmentry_l1d_flush == 2 and here you
do the direct flush for vmentry_l1d_flush != 1. That should be == 1, right?

Thanks,

	tglx

next prev parent reply	other threads:[~2018-06-27 13:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-23 13:54 [MODERATED] [PATCH v4 8/8] [PATCH v4 8/8] Linux Patch #8 konrad.wilk
2018-06-25 14:32 ` [MODERATED] " Paolo Bonzini
2018-06-27 13:05 ` Thomas Gleixner [this message]
2018-06-27 14:43   ` Konrad Rzeszutek Wilk
2018-06-27 17:00     ` Thomas Gleixner
2018-06-28 16:40       ` [MODERATED] " Konrad Rzeszutek Wilk

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