From: Alexei Starovoitov <alexei.starovoitov@gmail.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: AMD SSBD extension document
Date: Fri, 18 May 2018 09:40:04 -0700 [thread overview]
Message-ID: <20180518164002.gp72oy264fmtjb6t@ast-mbp.dhcp.thefacebook.com> (raw)
In-Reply-To: <c9cec09f-bfc3-6981-f87a-99c6d50db192@amd.com>
On Fri, May 18, 2018 at 10:26:46AM -0500, speck for Tom Lendacky wrote:
> I'm including the documentation on the AMD SSBD extension support.
> This is preliminary information, please share only as needed.
thanks a lot of the doc!
Could you share what cases of memory disambiguation are being disabled,
so we can better estimate the impact ?
Same question to Intel folks.
Like, does it disable store-to-load forwarding out of store queue as well?
Meaning that today push+pop is a single cycle operation and passing
more than 5 arguments to functions via stack is still fast.
Callee saving registers with a sequence of pushes and pops is fast too.
If that is being disabled my MSR, it would mean that any short function
that has small number of insns to execute will be penalized with
save/restore of registers. The functions with more than 5 args will see
the penalty too.
The ubiquitous register spill/fill is penalized as well?
next prev parent reply other threads:[~2018-05-18 16:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-18 15:26 [MODERATED] AMD SSBD extension document Tom Lendacky
2018-05-18 16:40 ` Alexei Starovoitov [this message]
2018-05-18 17:04 ` [MODERATED] " Linus Torvalds
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