From: Michael Walle <mwalle@kernel.org>
To: Andrzej Hajda <andrzej.hajda@intel.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Sam Ravnborg <sam@ravnborg.org>,
Vinay Simha BN <simhavcs@gmail.com>,
Tony Lindgren <tony@atomide.com>
Cc: Daniel Semkowicz <dse@thaumatec.com>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Michael Walle <mwalle@kernel.org>
Subject: [PATCH 12/20] drm/bridge: tc358775: correctly configure LVDS clock
Date: Mon, 06 May 2024 15:34:41 +0200 [thread overview]
Message-ID: <20240506-tc358775-fix-powerup-v1-12-545dcf00b8dd@kernel.org> (raw)
In-Reply-To: <20240506-tc358775-fix-powerup-v1-0-545dcf00b8dd@kernel.org>
The driver assumes a DSI link with four lanes for now and has the LVDS
clock divider hardcoded to either 3 or 6. Take the number of lanes into
account, too. Also, explicitly set the clock source to the DSI clock.
While at it, replace the TC358775_LVCFG_PCLKDIV() and
TC358775_LVCFG_LVDLINK() inline functions style by the more common
linux bitfields functions.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/gpu/drm/bridge/tc358775.c | 48 +++++++++++++++++----------------------
1 file changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
index e6d1f0c686ac..eea41054c6fa 100644
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -139,6 +139,12 @@ enum {
};
#define LVCFG 0x049C /* LVDS Configuration */
+#define LVCFG_LVEN BIT(0)
+#define LVCFG_LVDLINK BIT(1)
+#define LVCFG_PCLKDIV GENMASK(7, 4)
+#define LVCFG_PCLKSEL GENMASK(11, 10)
+#define PCLKSEL_HSRCK 0 /* DSI clock */
+
#define LVPHY0 0x04A0 /* LVDS PHY 0 */
#define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
#define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
@@ -183,28 +189,8 @@ enum {
#define DEBUG01 0x05A4 /* LVDS Data */
#define DSI_CLEN_BIT BIT(0)
-#define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
-#define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
-#define LVCFG_LVEN_BIT BIT(0)
-
#define L0EN BIT(1)
-#define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
-#define TC358775_LVCFG_PCLKDIV__SHIFT 4
-static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
-{
- return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
- TC358775_LVCFG_PCLKDIV__MASK;
-}
-
-#define TC358775_LVCFG_LVDLINK__MASK 0x00000002
-#define TC358775_LVCFG_LVDLINK__SHIFT 1
-static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
-{
- return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
- TC358775_LVCFG_LVDLINK__MASK;
-}
-
enum tc358775_ports {
TC358775_DSI_IN,
TC358775_LVDS_OUT0,
@@ -327,6 +313,8 @@ static void tc_bridge_enable(struct drm_bridge *bridge)
struct tc_data *tc = bridge_to_tc(bridge);
u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
+ int bpp = mipi_dsi_pixel_format_to_bpp(tc->dsi->format);
+ int clkdiv;
unsigned int val = 0;
struct drm_display_mode *mode;
struct drm_connector *connector = get_connector(bridge->encoder);
@@ -408,14 +396,20 @@ static void tc_bridge_enable(struct drm_bridge *bridge)
regmap_write(tc->regmap, VFUEN, VFUEN_EN);
- val = LVCFG_LVEN_BIT;
- if (tc->lvds_dual_link) {
- val |= TC358775_LVCFG_LVDLINK(1);
- val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
- } else {
- val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
- }
+ /* Configure LVDS clock */
+ clkdiv = bpp / tc->num_dsi_lanes;
+ if (!tc->lvds_dual_link)
+ clkdiv /= 2;
+
+ val = u32_encode_bits(clkdiv, LVCFG_PCLKDIV);
+ val |= u32_encode_bits(PCLKSEL_HSRCK, LVCFG_PCLKSEL);
+ if (tc->lvds_dual_link)
+ val |= LVCFG_LVDLINK;
+
regmap_write(tc->regmap, LVCFG, val);
+
+ /* Finally, enable the LVDS transmitter */
+ regmap_write(tc->regmap, LVCFG, val | LVCFG_LVEN);
}
/*
--
2.39.2
next prev parent reply other threads:[~2024-05-06 13:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 13:34 [PATCH 00/20] drm/bridge: tc358775: proper bridge bringup and code cleanup Michael Walle
2024-05-06 13:34 ` [PATCH 01/20] drm/bridge: add dsi_lp11_notify mechanism Michael Walle
2024-05-07 8:37 ` Alexander Stein
2024-05-07 13:39 ` Dmitry Baryshkov
2024-05-06 13:34 ` [PATCH 02/20] drm/mediatek: dsi: provide LP-11 mode during .pre_enable Michael Walle
2024-05-06 13:34 ` [PATCH 03/20] drm/mediatek: dsi: add support for .dsi_lp11_notity() Michael Walle
2024-05-06 13:34 ` [PATCH 04/20] drm/bridge: tc358775: fix regulator supply id Michael Walle
2024-05-06 13:34 ` [PATCH 05/20] drm/bridge: tc358775: add crtc modes fixup Michael Walle
2024-05-06 13:34 ` [PATCH 06/20] drm/bridge: tc358775: redefine LV_MX() Michael Walle
2024-05-06 13:34 ` [PATCH 07/20] drm/bridge: tc358775: use regmap instead of open coded access functions Michael Walle
2024-05-06 13:34 ` [PATCH 08/20] drm/bridge: tc358775: remove error message if regulator is missing Michael Walle
2024-05-06 13:34 ` [PATCH 09/20] drm/bridge: tc358775: remove complex vsdelay calculation Michael Walle
2024-05-06 13:34 ` [PATCH 10/20] drm/bridge: tc358775: simplify lvds_link property Michael Walle
2024-05-06 13:34 ` [PATCH 11/20] drm/bridge: tc358775: reformat weird indentation Michael Walle
2024-05-06 13:34 ` Michael Walle [this message]
2024-05-06 13:34 ` [PATCH 13/20] drm/bridge: tc358775: split the init code Michael Walle
2024-05-06 13:34 ` [PATCH 14/20] drm/bridge: tc358775: configure PLL depending on the LVDS clock Michael Walle
2024-05-06 13:34 ` [PATCH 15/20] drm/bridge: tc358775: dynamically configure DSI link settings Michael Walle
2024-05-06 13:34 ` [PATCH 16/20] drm/bridge: tc358775: use proper defines to configure LVDS timings Michael Walle
2024-05-06 13:34 ` [PATCH 17/20] drm/bridge: tc358775: move bridge power up/down into functions Michael Walle
2024-05-06 13:34 ` [PATCH 18/20] drm/bridge: tc358775: fix the power-up/down delays Michael Walle
2024-05-06 13:34 ` [PATCH 19/20] drm/bridge: tc358775: fix power-up sequencing Michael Walle
2024-05-06 13:34 ` [PATCH 20/20] drm/bridge: tc358775: use devm_drm_bridge_add() Michael Walle
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