* [PATCH 0/2] eDP DSC fixes
@ 2023-08-24 12:51 Ankit Nautiyal
2023-08-24 12:51 ` [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
2023-08-24 12:51 ` [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
0 siblings, 2 replies; 8+ messages in thread
From: Ankit Nautiyal @ 2023-08-24 12:51 UTC (permalink / raw)
To: dri-devel, intel-gfx
Assume 8bpc is supported if Sink claims DSC support.
Also consider bpc constraint coming from EDID while computing
input BPC for DSC.
Rev2: Fix check for dsc support.
Rev3: Minor styling and typos fix.
Ankit Nautiyal (2):
drm/display/dp: Assume 8 bpc support when DSC is supported
drivers/drm/i915: Honor limits->max_bpp while computing DSC max input
bpp
drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
2 files changed, 9 insertions(+), 4 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
2023-08-24 12:51 [PATCH 0/2] eDP DSC fixes Ankit Nautiyal
@ 2023-08-24 12:51 ` Ankit Nautiyal
2023-08-29 8:44 ` [Intel-gfx] " Jani Nikula
2023-08-30 7:51 ` [1/2] " Lisovskiy, Stanislav
2023-08-24 12:51 ` [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
1 sibling, 2 replies; 8+ messages in thread
From: Ankit Nautiyal @ 2023-08-24 12:51 UTC (permalink / raw)
To: dri-devel, intel-gfx
As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.
So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.
v2: Use helper to get check dsc support. (Ankit)
v3: Fix styling and other typos. (Jani)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e6a78fd32380..8a1b64c57dfd 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
int num_bpc = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
+ if (!drm_dp_sink_supports_dsc(dsc_dpcd))
+ return 0;
+
if (color_depth & DP_DSC_12_BPC)
dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
dsc_bpc[num_bpc++] = 10;
- if (color_depth & DP_DSC_8_BPC)
- dsc_bpc[num_bpc++] = 8;
+
+ /* A DP DSC Sink device shall support 8 bpc. */
+ dsc_bpc[num_bpc++] = 8;
return num_bpc;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp
2023-08-24 12:51 [PATCH 0/2] eDP DSC fixes Ankit Nautiyal
2023-08-24 12:51 ` [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
@ 2023-08-24 12:51 ` Ankit Nautiyal
2023-08-30 12:02 ` [Intel-gfx] " Jani Nikula
1 sibling, 1 reply; 8+ messages in thread
From: Ankit Nautiyal @ 2023-08-24 12:51 UTC (permalink / raw)
To: dri-devel, intel-gfx
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.
v2: Use int instead of u8 for computations. (Jani)
Add closes tag. (Ankit)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9161
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd3..8f3dc79089ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2061,9 +2061,10 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
+ int max_bpc = min(limits->max_bpp / 3, (int)conn_state->max_requested_bpc);
+
/* For eDP use max bpp that can be supported with DSC. */
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc);
if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
"Computed BPC is not in DSC BPC limits\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
2023-08-24 12:51 ` [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
@ 2023-08-29 8:44 ` Jani Nikula
2023-08-29 9:01 ` Maxime Ripard
2023-08-30 7:51 ` [1/2] " Lisovskiy, Stanislav
1 sibling, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2023-08-29 8:44 UTC (permalink / raw)
To: Ankit Nautiyal, dri-devel, intel-gfx, Maxime Ripard,
Thomas Zimmermann, Maarten Lankhorst
On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
> Apparently some panels that do support DSC, are not setting the bit for
> 8bpc.
>
> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
> supported.
Maarten, Maxime, Thomas, ack for merging this via drm-intel?
BR,
Jani.
>
> v2: Use helper to get check dsc support. (Ankit)
> v3: Fix styling and other typos. (Jani)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e6a78fd32380..8a1b64c57dfd 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> int num_bpc = 0;
> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
>
> + if (!drm_dp_sink_supports_dsc(dsc_dpcd))
> + return 0;
> +
> if (color_depth & DP_DSC_12_BPC)
> dsc_bpc[num_bpc++] = 12;
> if (color_depth & DP_DSC_10_BPC)
> dsc_bpc[num_bpc++] = 10;
> - if (color_depth & DP_DSC_8_BPC)
> - dsc_bpc[num_bpc++] = 8;
> +
> + /* A DP DSC Sink device shall support 8 bpc. */
> + dsc_bpc[num_bpc++] = 8;
>
> return num_bpc;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
2023-08-29 8:44 ` [Intel-gfx] " Jani Nikula
@ 2023-08-29 9:01 ` Maxime Ripard
0 siblings, 0 replies; 8+ messages in thread
From: Maxime Ripard @ 2023-08-29 9:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: Thomas Zimmermann, Ankit Nautiyal, intel-gfx, dri-devel
[-- Attachment #1: Type: text/plain, Size: 496 bytes --]
On Tue, Aug 29, 2023 at 11:44:10AM +0300, Jani Nikula wrote:
> On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> > As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
> > Apparently some panels that do support DSC, are not setting the bit for
> > 8bpc.
> >
> > So always assume 8bpc support by DSC decoder, when DSC is claimed to be
> > supported.
>
> Maarten, Maxime, Thomas, ack for merging this via drm-intel?
That's fine by me
Maxime
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
2023-08-24 12:51 ` [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
2023-08-29 8:44 ` [Intel-gfx] " Jani Nikula
@ 2023-08-30 7:51 ` Lisovskiy, Stanislav
2023-08-30 12:00 ` [Intel-gfx] " Jani Nikula
1 sibling, 1 reply; 8+ messages in thread
From: Lisovskiy, Stanislav @ 2023-08-30 7:51 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Aug 24, 2023 at 06:21:20PM +0530, Ankit Nautiyal wrote:
> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
> Apparently some panels that do support DSC, are not setting the bit for
> 8bpc.
>
> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
> supported.
>
> v2: Use helper to get check dsc support. (Ankit)
> v3: Fix styling and other typos. (Jani)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index e6a78fd32380..8a1b64c57dfd 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> int num_bpc = 0;
> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
>
> + if (!drm_dp_sink_supports_dsc(dsc_dpcd))
> + return 0;
> +
> if (color_depth & DP_DSC_12_BPC)
> dsc_bpc[num_bpc++] = 12;
> if (color_depth & DP_DSC_10_BPC)
> dsc_bpc[num_bpc++] = 10;
> - if (color_depth & DP_DSC_8_BPC)
> - dsc_bpc[num_bpc++] = 8;
> +
> + /* A DP DSC Sink device shall support 8 bpc. */
> + dsc_bpc[num_bpc++] = 8;
>
> return num_bpc;
> }
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [1/2] drm/display/dp: Assume 8 bpc support when DSC is supported
2023-08-30 7:51 ` [1/2] " Lisovskiy, Stanislav
@ 2023-08-30 12:00 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2023-08-30 12:00 UTC (permalink / raw)
To: Lisovskiy, Stanislav, Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Wed, 30 Aug 2023, "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com> wrote:
> On Thu, Aug 24, 2023 at 06:21:20PM +0530, Ankit Nautiyal wrote:
>> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
>> Apparently some panels that do support DSC, are not setting the bit for
>> 8bpc.
>>
>> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
>> supported.
>>
>> v2: Use helper to get check dsc support. (Ankit)
>> v3: Fix styling and other typos. (Jani)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Pushed both to drm-intel-next, with Maxime's ack, thanks for the patches
and review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index e6a78fd32380..8a1b64c57dfd 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -2449,12 +2449,16 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>> int num_bpc = 0;
>> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
>>
>> + if (!drm_dp_sink_supports_dsc(dsc_dpcd))
>> + return 0;
>> +
>> if (color_depth & DP_DSC_12_BPC)
>> dsc_bpc[num_bpc++] = 12;
>> if (color_depth & DP_DSC_10_BPC)
>> dsc_bpc[num_bpc++] = 10;
>> - if (color_depth & DP_DSC_8_BPC)
>> - dsc_bpc[num_bpc++] = 8;
>> +
>> + /* A DP DSC Sink device shall support 8 bpc. */
>> + dsc_bpc[num_bpc++] = 8;
>>
>> return num_bpc;
>> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp
2023-08-24 12:51 ` [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
@ 2023-08-30 12:02 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2023-08-30 12:02 UTC (permalink / raw)
To: Ankit Nautiyal, dri-devel, intel-gfx
On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
>
> v2: Use int instead of u8 for computations. (Jani)
> Add closes tag. (Ankit)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9161
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7067ee3a4bd3..8f3dc79089ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2061,9 +2061,10 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> if (forced_bpp) {
> pipe_bpp = forced_bpp;
> } else {
> + int max_bpc = min(limits->max_bpp / 3, (int)conn_state->max_requested_bpc);
Hmh, only noticed after pushing, there's min_t() for when the types
differ.
BR,
Jani.
> +
> /* For eDP use max bpp that can be supported with DSC. */
> - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
> - conn_state->max_requested_bpc);
> + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc);
> if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
> drm_dbg_kms(&i915->drm,
> "Computed BPC is not in DSC BPC limits\n");
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-08-30 12:02 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-24 12:51 [PATCH 0/2] eDP DSC fixes Ankit Nautiyal
2023-08-24 12:51 ` [PATCH 1/2] drm/display/dp: Assume 8 bpc support when DSC is supported Ankit Nautiyal
2023-08-29 8:44 ` [Intel-gfx] " Jani Nikula
2023-08-29 9:01 ` Maxime Ripard
2023-08-30 7:51 ` [1/2] " Lisovskiy, Stanislav
2023-08-30 12:00 ` [Intel-gfx] " Jani Nikula
2023-08-24 12:51 ` [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
2023-08-30 12:02 ` [Intel-gfx] " Jani Nikula
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