From: Yang Xiwen <forbidden405@outlook.com>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Alex Elder <elder@linaro.org>,
Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info
Date: Sun, 18 Feb 2024 20:02:52 +0800 [thread overview]
Message-ID: <20240218-cache-v2-3-1fd919e2bd3e@outlook.com> (raw)
In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com>
During boot, the kernel complains:
[ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0
So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)
With this patch, the line above is gone and the following info is added
to the output of `lscpu`:
Caches (sum of all):
L1d: 128 KiB (4 instances)
L1i: 128 KiB (4 instances)
L2: 512 KiB (1 instance)
Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index fc64d2fa99eb..0a9533786f50 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -31,6 +31,13 @@ cpu@0 {
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-size = <0x8000>; /* 32 KiB */
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>; /* 32 KiB */
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
};
cpu@1 {
@@ -38,6 +45,13 @@ cpu@1 {
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-size = <0x8000>; /* 32 KiB */
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>; /* 32 KiB */
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
};
cpu@2 {
@@ -45,6 +59,13 @@ cpu@2 {
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-size = <0x8000>; /* 32 KiB */
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>; /* 32 KiB */
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
};
cpu@3 {
@@ -52,9 +73,25 @@ cpu@3 {
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-size = <0x8000>; /* 32 KiB */
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>; /* 32 KiB */
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
};
};
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x80000>; /* 512 KiB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
--
2.43.0
prev parent reply other threads:[~2024-02-18 12:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-18 12:02 [PATCH v2 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen
2024-02-18 12:02 ` [PATCH v2 1/3] arm64: dts: hi3798cv200: fix the size of GICR Yang Xiwen
2024-02-18 12:02 ` [PATCH v2 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Yang Xiwen
2024-02-18 12:02 ` Yang Xiwen [this message]
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