From: Yang Xiwen <forbidden405@outlook.com>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Alex Elder <elder@linaro.org>,
Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH 0/2] arm64: dts: hi3798cv200: fix GICR size, add cache info
Date: Sun, 18 Feb 2024 17:40:29 +0800 [thread overview]
Message-ID: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> (raw)
They are tested on a hi3798mv200 board in fact. Though the 2 SoCs are
highly similar and the CPU should be the same. Still, Tested-by are
welcomed.
The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53
Documentation [2]. Dts for other SoCs are also a good reference.
From the doc, we know L1 i-cache is 4-way assoc, L1 d-cache is 2-way
assoc and L2 cache is 16-way assoc. Fill the dts props accordingly.
Dear maintainers, maybe consider Cc to stable too?
[1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
[2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
Yang Xiwen (2):
arm64: dts: hi3798cv200: Fix the size of GICR
arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 39 +++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
---
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
change-id: 20240218-cache-11c8bf7566c2
Best regards,
--
Yang Xiwen <forbidden405@outlook.com>
next reply other threads:[~2024-02-18 9:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-18 9:40 Yang Xiwen [this message]
2024-02-18 9:40 ` [PATCH 1/2] arm64: dts: hi3798cv200: Fix the size of GICR Yang Xiwen
2024-02-18 9:40 ` [PATCH 2/2] arm64: dts: hi3798cv200: add cache info Yang Xiwen
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