From: Yang Xiwen <forbidden405@outlook.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH RFC v2 5/5] dt-bindings: clock: hisilicon,clock-reset-controller: add Hi3798MV200 SoC support
Date: Sat, 17 Feb 2024 20:52:10 +0800 [thread overview]
Message-ID: <20240217-clk-mv200-v2-5-b782e4eb66f7@outlook.com> (raw)
In-Reply-To: <20240217-clk-mv200-v2-0-b782e4eb66f7@outlook.com>
This SoC is similar to Hi3798CV200.
Also document the specific DLL regs and add an example for it.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
.../clock/hisilicon,clock-reset-generator.yaml | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
index d37cd892473e..8ee844574eda 100644
--- a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
+++ b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
@@ -44,12 +44,17 @@ properties:
- hisilicon,hi3519-crg
- hisilicon,hi3798cv200-crg
- hisilicon,hi3798cv200-sysctrl
+ - hisilicon,hi3798mv200-crg
+ - hisilicon,hi3798mv200-sysctrl
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
+ ranges:
+ maxItems: 1
+
'#clock-cells':
const: 1
@@ -87,6 +92,12 @@ properties:
description: |
Reset controller for Hi3798CV200 GMAC module
+patternProperties:
+ '.*-dll@[0-9a-f]+':
+ type: object
+ description: |
+ eMMC/SD delay-locked-loop (DLL) register subnode
+
required:
- compatible
- '#clock-cells'
@@ -137,3 +148,28 @@ examples:
#clock-cells = <1>;
};
};
+ - |
+ crg: clock-reset-controller@8a22000 {
+ compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd";
+ reg = <0x8a22000 0x1000>;
+ ranges = <0x0 0x8a22000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+
+ emmc_sap_dll: sap-dll@39c {
+ compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd";
+ reg = <0x39c 0x8>;
+ };
+
+ sdio0_sap_dll: sap-dll@3a4 {
+ compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd";
+ reg = <0x3a4 0x8>;
+ };
+
+ sdio1_sap_dll: sap-dll@3ac {
+ compatible = "hisilicon,sdmmc-sap-dll", "syscon", "simple-mfd";
+ reg = <0x3ac 0x8>;
+ };
+ };
--
2.43.0
prev parent reply other threads:[~2024-02-17 12:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-17 12:52 [PATCH RFC v2 0/5] clk: hisilicon: add support for Hi3798MV200 Yang Xiwen
2024-02-17 12:52 ` [PATCH RFC v2 1/5] dt-bindings: clock: histb-clock: Add missing common clock and Hi3798MV200 specific clock definition Yang Xiwen
2024-02-17 12:52 ` [PATCH RFC v2 2/5] clk: hisilicon: add CRG driver for Hi3798MV200 SoC Yang Xiwen
2024-02-17 12:52 ` [PATCH RFC v2 3/5] dt-bindings: clock: merge all hisilicon clock bindings to hisilicon,clock-reset-generator Yang Xiwen
2024-02-17 12:52 ` [PATCH RFC v2 4/5] dt-bindings: mfd: syscon: Add hisilicon,sdmmc-sap-dll compatible Yang Xiwen
2024-02-17 12:52 ` Yang Xiwen [this message]
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