* [PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
@ 2021-06-01 16:28 shaoyunl
2021-06-02 2:14 ` Alex Deucher
0 siblings, 1 reply; 2+ messages in thread
From: shaoyunl @ 2021-06-01 16:28 UTC (permalink / raw
To: amd-gfx; +Cc: shaoyunl
On SRIOV, driver should only access register through RLC in runtime
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Change-Id: Iecaa52436a2985a18ede9c86cb00cc197a717bd6
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index c781808e4dc3..f6cf70e69cce 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -28,12 +28,12 @@
#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
- ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+ ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
WREG32(reg, value))
#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
- ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+ ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
RREG32(reg))
--
2.17.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
2021-06-01 16:28 [PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime shaoyunl
@ 2021-06-02 2:14 ` Alex Deucher
0 siblings, 0 replies; 2+ messages in thread
From: Alex Deucher @ 2021-06-02 2:14 UTC (permalink / raw
To: shaoyunl; +Cc: amd-gfx list
On Tue, Jun 1, 2021 at 12:28 PM shaoyunl <shaoyun.liu@amd.com> wrote:
>
> On SRIOV, driver should only access register through RLC in runtime
>
> Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Change-Id: Iecaa52436a2985a18ede9c86cb00cc197a717bd6
> ---
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index c781808e4dc3..f6cf70e69cce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -28,12 +28,12 @@
> #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> WREG32(reg, value))
>
> #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> RREG32(reg))
>
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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2021-06-01 16:28 [PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime shaoyunl
2021-06-02 2:14 ` Alex Deucher
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