* [PATCH 00/22] DC Patches Jan 29 2024
@ 2024-01-24 7:01 Tom Chung
2024-01-24 7:01 ` [PATCH 01/22] drm/amd/display: Fix static screen event mask definition change Tom Chung
` (22 more replies)
0 siblings, 23 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
Daniel Wheeler, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
wayne.lin, Harry.Wentland, agustin.gutierrez
This DC patchset brings improvements in multiple areas.
In summary, we have:
- Add control flag for IPS residency profiling
- Populate invalid split index to be 0xF
- Fix dcn35 8k30 Underflow/Corruption Issue
- Fix DP audio settings
- Use correct phantom pipe when populating subvp pipe info
- Fix incorrect mpc_combine array size
- Fix DPSTREAM CLK on and off sequence
- Fix USB-C flag update after enc10 feature init
- Add debugfs disallow edp psr
- Unify optimize_required flags and VRR adjustments
- Increased min_dcfclk_mhz and min_fclk_mhz
- Fix static screen event mask definition change
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Alvin Lee (2):
drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel
drm/amd/display: Populate invalid split index to be 0xF
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.202.0
Aric Cyr (2):
drm/amd/display: Unify optimize_required flags and VRR adjustments
drm/amd/display: 3.2.270
Charlene Liu (3):
Revert "drm/amd/display: initialize all the dpm level's stutter
latency"
drm/amd/display: fix USB-C flag update after enc10 feature init
drm/amd/display: fix DP audio settings
Dmytro Laktyushkin (1):
drm/amd/display: Fix DPSTREAM CLK on and off sequence
Eric Yang (1):
drm/amd/display: fix invalid reg access on DCN35 FPGA
Fangzhi Zuo (1):
drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue
Fudongwang (1):
drm/amd/display: refine code for dmcub inbox1 ring buffer debug
Hersen Wu (1):
drm/amd/display: add debugfs disallow edp psr
Mounika Adhuri (1):
drm/amd/display: clkmgr unittest with removal of warn & rename DCN35
ips handshake for idle
Nicholas Kazlauskas (2):
drm/amd/display: Wait before sending idle allow and after idle
disallow
drm/amd/display: Wait for mailbox ready when powering up DMCUB
Nicholas Susanto (1):
drm/amd/display: Underflow workaround by increasing SR exit latency
Sohaib Nadeem (1):
drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
Taimur Hassan (1):
drm/amd/display: Send DTBCLK disable message on first commit
Wenjing Liu (2):
drm/amd/display: fix incorrect mpc_combine array size
drm/amd/display: use correct phantom pipe when populating subvp pipe
info
Yiling Chen (1):
drm/amd/display: Fix static screen event mask definition change
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 7 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 53 +++++++++++++++++++
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 53 ++++++++++---------
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 15 ++++++
drivers/gpu/drm/amd/display/dc/core/dc.c | 45 ++++++++++++----
.../gpu/drm/amd/display/dc/core/dc_resource.c | 14 +++++
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 14 +++--
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 -
.../gpu/drm/amd/display/dc/dce/dce_audio.c | 9 +++-
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 4 +-
.../display/dc/dcn32/dcn32_resource_helpers.c | 14 -----
.../display/dc/dcn35/dcn35_dio_link_encoder.c | 4 +-
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 15 +++---
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 +-
.../display/dc/dml2/dml2_translation_helper.c | 33 +++++-------
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 20 ++++---
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 18 -------
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 3 --
.../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 +-
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 18 +++++++
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.h | 4 ++
.../amd/display/dc/hwss/dcn31/dcn31_init.c | 2 +-
.../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 +-
.../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 +-
.../amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 2 +-
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 ++
.../dc/resource/dcn32/dcn32_resource.c | 2 +-
.../dc/resource/dcn32/dcn32_resource.h | 3 --
.../dc/resource/dcn321/dcn321_resource.c | 2 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 --
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 18 ++++---
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 ++++-
39 files changed, 274 insertions(+), 150 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 01/22] drm/amd/display: Fix static screen event mask definition change
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 02/22] Revert "drm/amd/display: initialize all the dpm level's stutter latency" Tom Chung
` (21 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, Yiling Chen, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
wayne.lin, Harry.Wentland, agustin.gutierrez
From: Yiling Chen <yi-ling.chen2@amd.com>
[why]
The static screen event mask definition is different
betwnn DCN31 after and before.
[how]
Rename DCN30_set_static_screen_control to DCN31.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Yiling Chen <yi-ling.chen2@amd.com>
---
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 18 ------------------
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 3 ---
.../drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 2 +-
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 18 ++++++++++++++++++
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.h | 4 ++++
.../drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 2 +-
.../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 +-
.../drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 2 +-
.../drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 2 +-
10 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 54d42cf860c9..7e6b7f2a6dc9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -1164,21 +1164,3 @@ void dcn30_prepare_bandwidth(struct dc *dc,
if (!dc->clk_mgr->clks.fw_based_mclk_switching)
dc_dmub_srv_p_state_delegate(dc, false, context);
}
-
-void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
- int num_pipes, const struct dc_static_screen_params *params)
-{
- unsigned int i;
- unsigned int triggers = 0;
-
- if (params->triggers.surface_update)
- triggers |= 0x100;
- if (params->triggers.cursor_update)
- triggers |= 0x8;
- if (params->triggers.force_trigger)
- triggers |= 0x1;
-
- for (i = 0; i < num_pipes; i++)
- pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,
- triggers, params->num_frames);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
index 4248a4c0e574..638f018a3cb5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
@@ -93,7 +93,4 @@ void dcn30_set_hubp_blank(const struct dc *dc,
void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context);
-void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
- int num_pipes, const struct dc_static_screen_params *params);
-
#endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index 9894caedffed..ef913445a795 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -64,7 +64,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn10_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 7423880fabb6..58eb918e2c10 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -617,3 +617,21 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
if (hws->ctx->dc->debug.hpo_optimization)
REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
}
+
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_params *params)
+{
+ unsigned int i;
+ unsigned int triggers = 0;
+
+ if (params->triggers.surface_update)
+ triggers |= 0x100;
+ if (params->triggers.cursor_update)
+ triggers |= 0x8;
+ if (params->triggers.force_trigger)
+ triggers |= 0x1;
+
+ for (i = 0; i < num_pipes; i++)
+ pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,
+ triggers, params->num_frames);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
index edfc01d6ad73..b8bc939da155 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
@@ -56,4 +56,8 @@ bool dcn31_is_abm_supported(struct dc *dc,
void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_params *params);
+
+
#endif /* __DC_HWSS_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index 669f524bd064..c06cc2c5da92 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -67,7 +67,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index ccb7e317e86a..542ce3b7f9e4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -69,7 +69,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index 427cfc8c24a4..0980df6c65ea 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -65,7 +65,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index a630aa77dcec..29a93dbc6631 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -70,7 +70,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn35_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 143d3fc0221c..e5cb7fb8b2d4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -69,7 +69,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn30_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 02/22] Revert "drm/amd/display: initialize all the dpm level's stutter latency"
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
2024-01-24 7:01 ` [PATCH 01/22] drm/amd/display: Fix static screen event mask definition change Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 03/22] drm/amd/display: Wait before sending idle allow and after idle disallow Tom Chung
` (20 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, Muhammad Ahmed, chiahsuan.chung, Sunpeng.Li,
Rodrigo.Siqueira, roman.li, jerry.zuo, Aurabindo.Pillai,
hersenxs.wu, wayne.lin, Harry.Wentland, agustin.gutierrez
From: Charlene Liu <charlene.liu@amd.com>
Revert commit beca01e909cf
("drm/amd/display: initialize all the dpm level's stutter latency")
Because it causes some regression
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 64d01a9cd68c..8b0f930be5ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -341,9 +341,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
break;
}
- if (dml2->config.bbox_overrides.clks_table.num_states)
- p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
-
/* Override from passed values, if available */
for (i = 0; i < p->in_states->num_states; i++) {
if (dml2->config.bbox_overrides.sr_exit_latency_us) {
@@ -400,6 +397,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
}
/* Copy clocks tables entries, if available */
if (dml2->config.bbox_overrides.clks_table.num_states) {
+ p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 03/22] drm/amd/display: Wait before sending idle allow and after idle disallow
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
2024-01-24 7:01 ` [PATCH 01/22] drm/amd/display: Fix static screen event mask definition change Tom Chung
2024-01-24 7:01 ` [PATCH 02/22] Revert "drm/amd/display: initialize all the dpm level's stutter latency" Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 04/22] drm/amd/display: Wait for mailbox ready when powering up DMCUB Tom Chung
` (19 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, Nicholas Kazlauskas, agustin.gutierrez
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
We want acknowledgment of the driver idle disallow from DMCUB before
continuing with any further programming.
For idle allow we want to minimize the chance of DMCUB actively
interacing with other firmware components on the system (eg. PMFW)
at the same time.
[How]
Ensure that DMCUB isn't in the middle of processing other command
submissions prior to allowing idle and after disallowing idle by
inserting a wait before the allow and by changing the wait type for
the idle disallow.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 2b79a0e5638e..c365cca05718 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1195,6 +1195,9 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
if (dc->debug.dmcub_emulation)
return;
+ if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
+ return;
+
memset(&cmd, 0, sizeof(cmd));
cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
@@ -1205,13 +1208,15 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
if (allow_idle) {
+ dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+
if (dc->hwss.set_idle_state)
dc->hwss.set_idle_state(dc, true);
}
/* NOTE: This does not use the "wake" interface since this is part of the wake path. */
/* We also do not perform a wait since DMCUB could enter idle after the notification. */
- dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
+ dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);
}
static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 04/22] drm/amd/display: Wait for mailbox ready when powering up DMCUB
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (2 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 03/22] drm/amd/display: Wait before sending idle allow and after idle disallow Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 05/22] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Tom Chung
` (18 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, Nicholas Kazlauskas, agustin.gutierrez
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
Otherwise we can send commands too early and they don't execute until
the next command is sent.
[How]
Check the extra status bit when polling for HW powered up.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 71eee58d86a1..569c2a27a042 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -791,11 +791,20 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)
{
+ union dmub_fw_boot_status status;
+
if (!dmub->hw_funcs.is_hw_powered_up)
return true;
- return dmub->hw_funcs.is_hw_powered_up(dmub) &&
- dmub->hw_funcs.is_hw_init(dmub);
+ if (!dmub->hw_funcs.is_hw_powered_up(dmub))
+ return false;
+
+ if (!dmub->hw_funcs.is_hw_init(dmub))
+ return false;
+
+ status = dmub->hw_funcs.get_fw_status(dmub);
+
+ return status.bits.dal_fw && status.bits.mailbox_rdy;
}
enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 05/22] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (3 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 04/22] drm/amd/display: Wait for mailbox ready when powering up DMCUB Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 06/22] drm/amd/display: Unify optimize_required flags and VRR adjustments Tom Chung
` (17 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sohaib Nadeem, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, Alvin Lee,
wayne.lin, Chaitanya Dhere, Harry.Wentland, agustin.gutierrez
From: Sohaib Nadeem <sohaib.nadeem@amd.com>
[why]
Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
requirement will still be satisfied. Increasing min DCFCLK addresses
underflow issues (underflow occurs when phantom pipe is turned on for some
Sub-Viewport configs).
[how]
Increasing DCFCLK by raising the min_dcfclk_mhz
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sohaib Nadeem <sohaib.nadeem@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 9f37f717a1f8..b13a6fd7cc83 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2753,7 +2753,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
- unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
+ unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 06/22] drm/amd/display: Unify optimize_required flags and VRR adjustments
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (4 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 05/22] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 07/22] drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel Tom Chung
` (16 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Aric Cyr, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
jerry.zuo, Aurabindo.Pillai, hersenxs.wu, Alvin Lee, wayne.lin,
Harry.Wentland, agustin.gutierrez
From: Aric Cyr <aric.cyr@amd.com>
[why]
There is only a single call to dc_post_update_surfaces_to_stream
so there is no need to have two flags to control it. Unifying
this to a single flag allows dc_stream_adjust_vmin_vmax to skip
actual programming when there is no change required.
[how]
Remove wm_optimze_required flag and set only optimize_required in its
place. Then in dc_stream_adjust_vmin_vmax, check that the stream timing
range matches the requested one and skip programming if they are equal.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++++---------
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 --
.../drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
.../drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ++++----
5 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index aa7c02ba948e..186d54205bcc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -411,9 +411,12 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
* avoid conflicting with firmware updates.
*/
if (dc->ctx->dce_version > DCE_VERSION_MAX)
- if (dc->optimized_required || dc->wm_optimized_required)
+ if (dc->optimized_required)
return false;
+ if (!memcmp(&stream->adjust, adjust, sizeof(*adjust)))
+ return true;
+
stream->adjust.v_total_max = adjust->v_total_max;
stream->adjust.v_total_mid = adjust->v_total_mid;
stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
@@ -2227,7 +2230,6 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
}
dc->optimized_required = false;
- dc->wm_optimized_required = false;
}
bool dc_set_generic_gpio_for_stereo(bool enable,
@@ -2650,8 +2652,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
dc->optimized_required = true;
}
-
- dc->optimized_required |= dc->wm_optimized_required;
}
return type;
@@ -2859,9 +2859,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
if (update->vrr_active_fixed)
stream->vrr_active_fixed = *update->vrr_active_fixed;
- if (update->crtc_timing_adjust)
- stream->adjust = *update->crtc_timing_adjust;
-
if (update->dpms_off)
stream->dpms_off = *update->dpms_off;
@@ -4291,8 +4288,7 @@ static bool full_update_required(struct dc *dc,
stream_update->mst_bw_update ||
stream_update->func_shaper ||
stream_update->lut3d_func ||
- stream_update->pending_test_pattern ||
- stream_update->crtc_timing_adjust))
+ stream_update->pending_test_pattern))
return true;
if (stream) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 8ef322b6c724..ee561d941f53 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1038,7 +1038,6 @@ struct dc {
/* Require to optimize clocks and bandwidth for added/removed planes */
bool optimized_required;
- bool wm_optimized_required;
bool idle_optimizations_allowed;
bool enable_c20_dtm_b0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index ee10941caa59..a23eebd9933b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -139,7 +139,6 @@ union stream_update_flags {
uint32_t wb_update:1;
uint32_t dsc_changed : 1;
uint32_t mst_bw : 1;
- uint32_t crtc_timing_adjust : 1;
uint32_t fams_changed : 1;
} bits;
@@ -326,7 +325,6 @@ struct dc_stream_update {
struct dc_3dlut *lut3d_func;
struct test_pattern *pending_test_pattern;
- struct dc_crtc_timing_adjust *crtc_timing_adjust;
};
bool dc_is_stream_unchanged(
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index d923d8d915f9..e8632a4222a6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -3126,7 +3126,7 @@ void dcn10_prepare_bandwidth(
context,
false);
- dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
+ dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,
&context->bw_ctx.bw.dcn.watermarks,
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
true);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 6514a51ee7f3..a2a30204f565 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2265,10 +2265,10 @@ void dcn20_prepare_bandwidth(
}
/* program dchubbub watermarks:
- * For assigning wm_optimized_required, use |= operator since we don't want
+ * For assigning optimized_required, use |= operator since we don't want
* to clear the value if the optimize has not happened yet
*/
- dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub,
+ dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,
&context->bw_ctx.bw.dcn.watermarks,
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
false);
@@ -2281,10 +2281,10 @@ void dcn20_prepare_bandwidth(
if (hubbub->funcs->program_compbuf_size) {
if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
- dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
+ dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
} else {
compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
- dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
+ dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
}
hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 07/22] drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (5 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 06/22] drm/amd/display: Unify optimize_required flags and VRR adjustments Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 08/22] drm/amd/display: add debugfs disallow edp psr Tom Chung
` (15 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
jerry.zuo, Aurabindo.Pillai, hersenxs.wu, Alvin Lee, wayne.lin,
Harry.Wentland, agustin.gutierrez
From: Alvin Lee <alvin.lee2@amd.com>
[Why & How]
For FPO and SubVP/DRR cases we need to ensure to program
OTG_V_TOTAL_MIN/MAX_SEL, otherwise stretching the vblank
in FPO / SubVP / DRR cases will not have any effect
and we could hit underflow / corruption.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 31 +++++++++++++++++++
.../gpu/drm/amd/display/dc/core/dc_resource.c | 14 +++++++++
.../display/dc/dcn32/dcn32_resource_helpers.c | 14 ---------
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 11 ++++---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 1 -
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 ++
.../dc/resource/dcn32/dcn32_resource.c | 2 +-
.../dc/resource/dcn32/dcn32_resource.h | 3 --
.../dc/resource/dcn321/dcn321_resource.c | 2 +-
9 files changed, 56 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 186d54205bcc..2db361aeaf25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3481,6 +3481,33 @@ static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state
}
}
+static void update_drr_for_full_update(struct dc *dc, struct dc_state *context)
+{
+ uint32_t i;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct dc_stream_state *stream = pipe->stream;
+ struct timing_generator *tg = pipe->stream_res.tg;
+ struct drr_params params = {0};
+
+ /* pipe not in use */
+ if (!resource_is_pipe_type(pipe, OTG_MASTER))
+ continue;
+
+ /* skip phantom pipes */
+ if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
+ continue;
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+ params.vertical_total_mid = stream->adjust.v_total_mid;
+ params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
+ if (pipe->stream_res.tg->funcs->set_drr)
+ tg->funcs->set_drr(pipe->stream_res.tg, ¶ms);
+ }
+}
+
static void commit_planes_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
@@ -3848,6 +3875,10 @@ static void commit_planes_for_stream(struct dc *dc,
pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
}
+ // Update DRR for all pipes
+ if (update_type != UPDATE_TYPE_FAST)
+ update_drr_for_full_update(dc, context);
+
current_stream_mask = get_stream_mask(dc, context);
if (current_stream_mask != context->stream_mask) {
context->stream_mask = current_stream_mask;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9fbdb09697fd..259ccbe858b4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4990,6 +4990,20 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
return DC_OK;
}
+bool resource_subvp_in_use(struct dc *dc,
+ struct dc_state *context)
+{
+ uint32_t i;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)
+ return true;
+ }
+ return false;
+}
+
bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)
{
if (!dc->debug.disable_subvp_high_refresh && is_subvp_high_refresh_candidate(stream))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 87760600e154..e4a328b45c8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -183,20 +183,6 @@ bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
return true;
}
-bool dcn32_subvp_in_use(struct dc *dc,
- struct dc_state *context)
-{
- uint32_t i;
-
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
-
- if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)
- return true;
- }
- return false;
-}
-
bool dcn32_mpo_in_use(struct dc_state *context)
{
uint32_t i;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b13a6fd7cc83..9b80f65c0466 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -33,6 +33,7 @@
#include "dcn30/dcn30_resource.h"
#include "link.h"
#include "dc_state_priv.h"
+#include "resource.h"
#define DC_LOGGER_INIT(logger)
@@ -291,7 +292,7 @@ int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
/* for subvp + DRR case, if subvp pipes are still present we support pstate */
if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
- dcn32_subvp_in_use(dc, context))
+ resource_subvp_in_use(dc, context))
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
@@ -2272,7 +2273,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
unsigned int dummy_latency_index = 0;
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
- bool subvp_in_use = dcn32_subvp_in_use(dc, context);
+ bool subvp_active = resource_subvp_in_use(dc, context);
unsigned int min_dram_speed_mts_margin;
bool need_fclk_lat_as_dummy = false;
bool is_subvp_p_drr = false;
@@ -2281,7 +2282,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
dc_assert_fp_enabled();
/* need to find dummy latency index for subvp */
- if (subvp_in_use) {
+ if (subvp_active) {
/* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */
if (!pstate_en) {
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
@@ -2467,7 +2468,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
}
- if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {
+ if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_active) {
/* find largest table entry that is lower than dram speed,
* but lower than DPM0 still uses DPM0
*/
@@ -3527,7 +3528,7 @@ void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)
{
// WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)
- if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&
+ if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || resource_subvp_in_use(dc, context)) &&
dc->dml.soc.num_chans <= 8) {
int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index a2a30204f565..1ffdaa38c932 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2064,7 +2064,6 @@ void dcn20_program_front_end_for_ctx(
&& context->res_ctx.pipe_ctx[i].stream)
hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
-
/* Disconnect mpcc */
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index c958ef37b78a..1d51fed12e20 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -609,6 +609,9 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
struct pipe_ctx *sec_pipe,
bool odm);
+bool resource_subvp_in_use(struct dc *dc,
+ struct dc_state *context);
+
/* A test harness interface that modifies dp encoder resources in the given dc
* state and bypasses the need to revalidate. The interface assumes that the
* test harness interface is called with pre-validated link config stored in the
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index c4d71e7f18af..ac04a9c9a3d8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1899,7 +1899,7 @@ int dcn32_populate_dml_pipes_from_context(
static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
- .get_subvp_en = dcn32_subvp_in_use,
+ .get_subvp_en = resource_subvp_in_use,
};
void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 0c87b0fabba7..62611acd4bcb 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -131,9 +131,6 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc,
bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
struct dc_state *context);
-bool dcn32_subvp_in_use(struct dc *dc,
- struct dc_state *context);
-
bool dcn32_mpo_in_use(struct dc_state *context);
bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 6f832bf278cf..eefc127a9381 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1574,7 +1574,7 @@ static void dcn321_destroy_resource_pool(struct resource_pool **pool)
static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
- .get_subvp_en = dcn32_subvp_in_use,
+ .get_subvp_en = resource_subvp_in_use,
};
static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 08/22] drm/amd/display: add debugfs disallow edp psr
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (6 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 07/22] drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 09/22] drm/amd/display: fix USB-C flag update after enc10 feature init Tom Chung
` (14 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, agustin.gutierrez
From: Hersen Wu <hersenxs.wu@amd.com>
[Why]
fix reading edp rx crc timeout failure. after
bootup, kernel setup psr with dpcd 0x170 = 5. this
notify rx psr enable and let rx fw start checking crc
for fw internal logic. rx fw may not update crc read
count within dpcd 0x246. read count is always 0. this
will lead tx crc reading timeout.
[How]
add debugfs to let test app to disbable rx crc
checking for rx internal logic. then test app can read
rx crc dpcd 0x246 successfully.
expected app sequence is as below:
1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
without dpcd 0x170 = 5.
4. read crc from rx dpcd 0x270, 0x246, etc.
5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
this will let eDP back to normal with psr setup dpcd 0x170 = 5.
Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 7 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 53 +++++++++++++++++++
4 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 41994a60e2cd..a17b2edee269 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8568,7 +8568,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
- amdgpu_dm_link_setup_psr(acrtc_state->stream);
+
+ struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
+ acrtc_state->stream->dm_stream_context;
+
+ if (!aconn->disallow_edp_enter_psr)
+ amdgpu_dm_link_setup_psr(acrtc_state->stream);
}
}
@@ -8597,6 +8602,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
#endif
!acrtc_state->stream->link->psr_settings.psr_allow_active &&
+ !aconn->disallow_edp_enter_psr &&
(timestamp_ns -
acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
500000000)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 9c1871b866cc..09519b7abf67 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -693,6 +693,7 @@ struct amdgpu_dm_connector {
struct drm_display_mode freesync_vid_base;
int psr_skip_count;
+ bool disallow_edp_enter_psr;
/* Record progress status of mst*/
uint8_t mst_status;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index c5078e6e1a3c..e23a0a276e33 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -142,7 +142,12 @@ static void amdgpu_dm_crtc_set_panel_sr_feature(
amdgpu_dm_psr_disable(vblank_work->stream);
} else if (link->psr_settings.psr_feature_enabled &&
allow_sr_entry && !is_sr_active && !is_crc_window_active) {
- amdgpu_dm_psr_enable(vblank_work->stream);
+
+ struct amdgpu_dm_connector *aconn =
+ (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
+
+ if (!aconn->disallow_edp_enter_psr)
+ amdgpu_dm_psr_enable(vblank_work->stream);
}
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 68a846323912..f77ee5eb7f56 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2971,6 +2971,53 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val)
return 0;
}
+/* check if kernel disallow eDP enter psr state
+ * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 0: allow edp enter psr; 1: disallow
+ */
+static int disallow_edp_enter_psr_get(void *data, u64 *val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+
+ *val = (u64) aconnector->disallow_edp_enter_psr;
+ return 0;
+}
+
+/* set kernel disallow eDP enter psr state
+ * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 0: allow edp enter psr; 1: disallow
+ *
+ * usage: test app read crc from PSR eDP rx.
+ *
+ * during kernel boot up, kernel write dpcd 0x170 = 5.
+ * this notify eDP rx psr enable and let rx check crc.
+ * rx fw will start checking crc for rx internal logic.
+ * crc read count within dpcd 0x246 is not updated and
+ * value is 0. when eDP tx driver wants to read rx crc
+ * from dpcd 0x246, 0x270, read count 0 lead tx driver
+ * timeout.
+ *
+ * to avoid this, we add this debugfs to let test app to disbable
+ * rx crc checking for rx internal logic. then test app can read
+ * non-zero crc read count.
+ *
+ * expected app sequence is as below:
+ * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
+ * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
+ * without dpcd 0x170 = 5.
+ * 4. read crc from rx dpcd 0x270, 0x246, etc.
+ * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
+ * this will let eDP back to normal with psr setup dpcd 0x170 = 5.
+ */
+static int disallow_edp_enter_psr_set(void *data, u64 val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+
+ aconnector->disallow_edp_enter_psr = val ? true : false;
+ return 0;
+}
+
static int dmub_trace_mask_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
@@ -3092,6 +3139,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
allow_edp_hotplug_detection_get,
allow_edp_hotplug_detection_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
+ disallow_edp_enter_psr_get,
+ disallow_edp_enter_psr_set, "%llu\n");
+
DEFINE_SHOW_ATTRIBUTE(current_backlight);
DEFINE_SHOW_ATTRIBUTE(target_backlight);
@@ -3265,6 +3316,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
&edp_ilr_debugfs_fops);
debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
&allow_edp_hotplug_detection_fops);
+ debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
+ &disallow_edp_enter_psr_fops);
}
for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 09/22] drm/amd/display: fix USB-C flag update after enc10 feature init
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (7 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 08/22] drm/amd/display: add debugfs disallow edp psr Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 10/22] drm/amd/display: Send DTBCLK disable message on first commit Tom Chung
` (13 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, Muhammad Ahmed, chiahsuan.chung, Sunpeng.Li,
Rodrigo.Siqueira, roman.li, jerry.zuo, Aurabindo.Pillai,
hersenxs.wu, wayne.lin, Harry.Wentland, agustin.gutierrez
From: Charlene Liu <charlene.liu@amd.com>
[why]
BIOS's integration info table not following the original order
which is phy instance is ext_displaypath's array index.
[how]
Move them to follow the original order.
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
index 501388014855..d761b0df2878 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
@@ -203,12 +203,12 @@ void dcn32_link_encoder_construct(
enc10->base.hpd_source = init_data->hpd_source;
enc10->base.connector = init_data->connector;
- if (enc10->base.connector.id == CONNECTOR_ID_USBC)
- enc10->base.features.flags.bits.DP_IS_USB_C = 1;
enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
enc10->base.features = *enc_features;
+ if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+ enc10->base.features.flags.bits.DP_IS_USB_C = 1;
enc10->base.transmitter = init_data->transmitter;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
index da94e5309fba..81e349d5835b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
@@ -184,8 +184,6 @@ void dcn35_link_encoder_construct(
enc10->base.hpd_source = init_data->hpd_source;
enc10->base.connector = init_data->connector;
- if (enc10->base.connector.id == CONNECTOR_ID_USBC)
- enc10->base.features.flags.bits.DP_IS_USB_C = 1;
enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
@@ -240,6 +238,8 @@ void dcn35_link_encoder_construct(
}
enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+ if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+ enc10->base.features.flags.bits.DP_IS_USB_C = 1;
if (bp_funcs->get_connector_speed_cap_info)
result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 10/22] drm/amd/display: Send DTBCLK disable message on first commit
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (8 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 09/22] drm/amd/display: fix USB-C flag update after enc10 feature init Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 11/22] drm/amd/display: refine code for dmcub inbox1 ring buffer debug Tom Chung
` (12 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
Taimur Hassan, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
wayne.lin, Harry.Wentland, Nicholas Kazlauskas, agustin.gutierrez
From: Taimur Hassan <syed.hassan@amd.com>
[Why]
Previous patch to allow DTBCLK disable didn't address boot case. Driver
thinks DTBCLK is disabled by default, so we don't send disable message to
PMFW. DTBCLK is then enabled at idle desktop on boot, burning power.
[How]
Set dtbclk_en to true on boot so that disable message is sent during first
commit.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 0e5a3184f01c..3d1a60cc2908 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -415,6 +415,7 @@ void dcn35_init_clocks(struct clk_mgr *clk_mgr)
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
// Assumption is that boot state always supports pstate
+ clk_mgr->clks.dtbclk_en = true;
clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 11/22] drm/amd/display: refine code for dmcub inbox1 ring buffer debug
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (9 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 10/22] drm/amd/display: Send DTBCLK disable message on first commit Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 12/22] drm/amd/display: fix invalid reg access on DCN35 FPGA Tom Chung
` (11 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Fudongwang, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, Nicholas Kazlauskas, agustin.gutierrez
From: Fudongwang <fudong.wang@amd.com>
[Why]
1. To watch dmcub inbox1 ring buffer cmd type without tools
2. dmub_cmd_PLAT_54186_wa 66 bytes
[How]
Added dmcub cmd type enum: unsigned char for debug use only,
also fixed 66 bytes issue by using unsigned int in bit
define instead of unsigned char.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Fudongwang <fudong.wang@amd.com>
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 ----
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 10 +++++-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 410420683f31..0684a0b93637 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -78,10 +78,6 @@ struct dmub_srv_dcn31_regs;
struct dmcub_trace_buf_entry;
-struct dmcub_inbox1_buf {
- union dmub_rb_cmd cmd[DMUB_RB_MAX_ENTRY];
-};
-
/* enum dmub_window_memory_type - memory location type specification for windows */
enum dmub_window_memory_type {
DMUB_WINDOW_MEMORY_TYPE_FB = 0,
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 89717076933e..49bc1e41ac67 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1265,11 +1265,11 @@ struct dmub_cmd_PLAT_54186_wa {
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
struct {
- uint8_t hubp_inst : 4; /**< HUBP instance */
- uint8_t tmz_surface : 1; /**< TMZ enable or disable */
- uint8_t immediate :1; /**< Immediate flip */
- uint8_t vmid : 4; /**< VMID */
- uint8_t grph_stereo : 1; /**< 1 if stereo */
+ uint32_t hubp_inst : 4; /**< HUBP instance */
+ uint32_t tmz_surface : 1; /**< TMZ enable or disable */
+ uint32_t immediate :1; /**< Immediate flip */
+ uint32_t vmid : 4; /**< VMID */
+ uint32_t grph_stereo : 1; /**< 1 if stereo */
uint32_t reserved : 21; /**< Reserved */
} flip_params; /**< Pageflip parameters */
uint32_t reserved[9]; /**< Reserved bits */
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 12/22] drm/amd/display: fix invalid reg access on DCN35 FPGA
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (10 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 11/22] drm/amd/display: refine code for dmcub inbox1 ring buffer debug Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 13/22] drm/amd/display: Fix DPSTREAM CLK on and off sequence Tom Chung
` (10 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin, Eric Yang,
Harry.Wentland, agustin.gutierrez, Sung joon Kim
From: Eric Yang <eric.yang@amd.com>
[Why]
Unguarded SMU and CLK IP access cause issue on FPGA
[How]
Guard them for FPGA environment
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Eric Yang <eric.yang@amd.com>
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 12 ++++++++----
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 15 +++++++++++++++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 3d1a60cc2908..e1b035380f6a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -408,13 +408,12 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs
struct clk_mgr_dcn35 *clk_mgr)
{
}
-void dcn35_init_clocks(struct clk_mgr *clk_mgr)
+
+static void init_clk_states(struct clk_mgr *clk_mgr)
{
uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
-
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
- // Assumption is that boot state always supports pstate
clk_mgr->clks.dtbclk_en = true;
clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
clk_mgr->clks.p_state_change_support = true;
@@ -422,6 +421,11 @@ void dcn35_init_clocks(struct clk_mgr *clk_mgr)
clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
}
+
+void dcn35_init_clocks(struct clk_mgr *clk_mgr)
+{
+ init_clk_states(clk_mgr);
+}
static struct clk_bw_params dcn35_bw_params = {
.vram_type = Ddr4MemType,
.num_channels = 1,
@@ -883,7 +887,7 @@ static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
{
- dcn35_init_clocks(clk_mgr);
+ init_clk_states(clk_mgr);
/* TODO: Implement the functions and remove the ifndef guard */
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 6d4a1ffab5ed..a07f7e685d28 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -447,6 +447,9 @@ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
{
+ if (!clk_mgr->smu_present)
+ return;
+
dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
@@ -458,6 +461,9 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
{
int retv;
+ if (!clk_mgr->smu_present)
+ return 0;
+
retv = dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_DispPsrExit,
@@ -470,6 +476,9 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
{
int retv;
+ if (!clk_mgr->smu_present)
+ return 0;
+
retv = dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_QueryIPS2Support,
@@ -481,6 +490,9 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
{
+ if (!clk_mgr->smu_present)
+ return;
+
REG_WRITE(MP1_SMN_C2PMSG_71, param);
//smu_print("%s: write_ips_scratch = %x\n", __func__, param);
}
@@ -489,6 +501,9 @@ uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
{
uint32_t retv;
+ if (!clk_mgr->smu_present)
+ return 0;
+
retv = REG_READ(MP1_SMN_C2PMSG_71);
//smu_print("%s: dcn35_smu_read_ips_scratch = %x\n", __func__, retv);
return retv;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 13/22] drm/amd/display: Fix DPSTREAM CLK on and off sequence
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (11 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 12/22] drm/amd/display: fix invalid reg access on DCN35 FPGA Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 14/22] drm/amd/display: fix incorrect mpc_combine array size Tom Chung
` (9 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, Dmytro Laktyushkin, chiahsuan.chung, Daniel Miess,
Sunpeng.Li, Rodrigo.Siqueira, roman.li, jerry.zuo,
Aurabindo.Pillai, hersenxs.wu, wayne.lin, Harry.Wentland,
agustin.gutierrez
From: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
[Why]
Secondary DP2 display fails to light up in some instances
[How]
Clock needs to be on when DPSTREAMCLK*_EN =1. This change
moves dtbclk_p enable/disable point to make sure this is
the case
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
---
.../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 11 +++++------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index db71a261e9da..88170ab0ec7e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1183,9 +1183,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = &pipe_ctx->stream->timing;
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
- dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
+ dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
} else if (dccg && dccg->funcs->disable_symclk_se) {
dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
link_enc->transmitter - TRANSMITTER_UNIPHY_A);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 1ffdaa38c932..d26353dafc1c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2895,18 +2895,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
}
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
- dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
- dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
-
- phyd32clk = get_phyd32clk_src(link);
- dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
-
dto_params.otg_inst = tg->inst;
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
dto_params.timing = &pipe_ctx->stream->timing;
dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+ dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
+ dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
+
+ phyd32clk = get_phyd32clk_src(link);
+ dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
} else {
if (dccg->funcs->enable_symclk_se)
dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 14/22] drm/amd/display: fix incorrect mpc_combine array size
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (12 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 13/22] drm/amd/display: Fix DPSTREAM CLK on and off sequence Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 15/22] drm/amd/display: use correct phantom pipe when populating subvp pipe info Tom Chung
` (8 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Wenjing Liu, Rodrigo Siqueira,
roman.li, stable, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
Mario Limonciello, wayne.lin, Alex Deucher, Nevenko Stupar,
Chaitanya Dhere, Harry.Wentland, agustin.gutierrez
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
MAX_SURFACES is per stream, while MAX_PLANES is per asic. The
mpc_combine is an array that records all the planes per asic. Therefore
MAX_PLANES should be used as the array size. Using MAX_SURFACES causes
array overflow when there are more than 3 planes.
[how]
Use the MAX_PLANES for the mpc_combine array size.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 9b80f65c0466..a7981a0c4158 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1113,7 +1113,7 @@ struct pipe_slice_table {
struct pipe_ctx *pri_pipe;
struct dc_plane_state *plane;
int slice_count;
- } mpc_combines[MAX_SURFACES];
+ } mpc_combines[MAX_PLANES];
int mpc_combine_count;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 15/22] drm/amd/display: use correct phantom pipe when populating subvp pipe info
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (13 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 14/22] drm/amd/display: fix incorrect mpc_combine array size Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 16/22] drm/amd/display: Underflow workaround by increasing SR exit latency Tom Chung
` (7 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Wenjing Liu, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, Alvin Lee,
wayne.lin, Harry.Wentland, agustin.gutierrez
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
In current code, we recognize a pipe as a phantom pipe if it references
the same phantom stream. However it can also a phantom split pipe.
If the phantom split pipe has a smaller pipe index than the phantom pipe
we will mistakenly use the phantom split pipe as the phantom pipe. This
causes an incorrect subvp configuration where the first half of the
screen is flashing solid white image.
[how]
Add additional check that the pipe needs to be an OTG master pipe.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index c365cca05718..3d7252218ea9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -787,7 +787,8 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
- if (phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
+ if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) &&
+ phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
if (phantom_pipe->bottom_pipe) {
pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 16/22] drm/amd/display: Underflow workaround by increasing SR exit latency
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (14 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 15/22] drm/amd/display: use correct phantom pipe when populating subvp pipe info Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 17/22] drm/amd/display: fix DP audio settings Tom Chung
` (6 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Nicholas Susanto, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Chaitanya Dhere, Harry.Wentland, agustin.gutierrez
From: Nicholas Susanto <nicholas.susanto@amd.com>
[Why]
On 14us for exit latency time causes underflow for 8K monitor with HDR on.
Increasing the latency to 28us fixes the underflow.
[How]
Increase the latency to 28us. This workaround should be sufficient
before we figure out why SR exit so long.
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com>
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 32 +++++++++----------
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 +--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index e1b035380f6a..eda39d739ff9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -441,32 +441,32 @@ static struct wm_table ddr5_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
}
@@ -478,32 +478,32 @@ static struct wm_table lpddr5_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index a85693caebd5..912256006d75 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
},
},
.num_states = 5,
- .sr_exit_time_us = 14.0,
- .sr_enter_plus_exit_time_us = 16.0,
+ .sr_exit_time_us = 28.0,
+ .sr_enter_plus_exit_time_us = 30.0,
.sr_exit_z8_time_us = 210.0,
.sr_enter_plus_exit_z8_time_us = 320.0,
.fclk_change_latency_us = 24.0,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 17/22] drm/amd/display: fix DP audio settings
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (15 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 16/22] drm/amd/display: Underflow workaround by increasing SR exit latency Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 18/22] drm/amd/display: clkmgr unittest with removal of warn & rename DCN35 ips handshake for idle Tom Chung
` (5 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, chiahsuan.chung, Sunpeng.Li, Zhan Liu,
Rodrigo.Siqueira, roman.li, jerry.zuo, Aurabindo.Pillai,
hersenxs.wu, wayne.lin, Harry.Wentland, agustin.gutierrez
From: Charlene Liu <charlene.liu@amd.com>
[why]
Audio channel layout for 5.1ch is not correct
[how]
Add the audio layout for 5.1ch (channel_count = 6).
Add divided by zero check.
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 07b507150c51..12f3c35b3a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -282,7 +282,7 @@ static void get_audio_layout_config(
output->layouts_per_sample_denom = 4;
output->symbols_per_layout = 40;
output->max_layouts_per_audio_sdp = 1;
- } else if (channel_count == 8) {
+ } else if (channel_count == 8 || channel_count == 6) {
output->layouts_per_sample_denom = 1;
output->symbols_per_layout = 40;
output->max_layouts_per_audio_sdp = 1;
@@ -292,7 +292,7 @@ static void get_audio_layout_config(
output->layouts_per_sample_denom = 4;
output->symbols_per_layout = 10;
output->max_layouts_per_audio_sdp = 1;
- } else if (channel_count == 8) {
+ } else if (channel_count == 8 || channel_count == 6) {
output->layouts_per_sample_denom = 1;
output->symbols_per_layout = 10;
output->max_layouts_per_audio_sdp = 1;
@@ -489,6 +489,11 @@ static void check_audio_bandwidth_dp(
get_audio_layout_config(
channel_count, dp_link_info->encoding, &layout_config);
+ if (layout_config.max_layouts_per_audio_sdp == 0 ||
+ layout_config.symbols_per_layout == 0 ||
+ layout_config.layouts_per_sample_denom == 0) {
+ return;
+ }
if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
crtc_info, &layout_config, channel_count, 192000,
av_stream_map_lane_count, audio_sdp_overhead))
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 18/22] drm/amd/display: clkmgr unittest with removal of warn & rename DCN35 ips handshake for idle
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (16 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 17/22] drm/amd/display: fix DP audio settings Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 19/22] drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue Tom Chung
` (4 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Martin Leung, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
Mounika Adhuri, wayne.lin, Harry.Wentland, agustin.gutierrez
From: Mounika Adhuri <moadhuri@amd.com>
[why]
To Remove warnings of clk_mgr.
[How]
Added code to remove warnings by resolving redefinations.
Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Mounika Adhuri <moadhuri@amd.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index eda39d739ff9..06edca50a8fa 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -830,7 +830,7 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
}
}
-static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
+static void dcn35_set_ips_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc *dc = clk_mgr_base->ctx->dc;
@@ -878,7 +878,7 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
return ips_supported;
}
-static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
+static uint32_t dcn35_get_ips_idle_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -972,8 +972,8 @@ static struct clk_mgr_funcs dcn35_funcs = {
.set_low_power_state = dcn35_set_low_power_state,
.exit_low_power_state = dcn35_exit_low_power_state,
.is_ips_supported = dcn35_is_ips_supported,
- .set_idle_state = dcn35_set_idle_state,
- .get_idle_state = dcn35_get_idle_state
+ .set_idle_state = dcn35_set_ips_idle_state,
+ .get_idle_state = dcn35_get_ips_idle_state
};
struct clk_mgr_funcs dcn35_fpga_funcs = {
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 19/22] drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (17 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 18/22] drm/amd/display: clkmgr unittest with removal of warn & rename DCN35 ips handshake for idle Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 20/22] drm/amd/display: Populate invalid split index to be 0xF Tom Chung
` (3 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Charlene Liu, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira,
roman.li, stable, jerry.zuo, Aurabindo.Pillai, hersenxs.wu,
Mario Limonciello, wayne.lin, Alex Deucher, Harry.Wentland,
agustin.gutierrez
From: Fangzhi Zuo <jerry.zuo@amd.com>
[why]
odm calculation is missing for pipe split policy determination
and cause Underflow/Corruption issue.
[how]
Add the odm calculation.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
---
.../display/dc/dml2/dml2_translation_helper.c | 29 +++++++------------
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 ++
2 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 8b0f930be5ae..23a608274096 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -791,35 +791,28 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p
}
}
-/*TODO no support for mpc combine, need rework - should calculate scaling params based on plane+stream*/
-static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, const struct dc_state *context)
+static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context)
{
int i;
- struct scaler_data data = { 0 };
+ struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;
+
+ memset(temp_pipe, 0, sizeof(struct pipe_ctx));
for (i = 0; i < MAX_PIPES; i++) {
const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->plane_state == in && !pipe->prev_odm_pipe) {
- const struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
-
- data = context->res_ctx.pipe_ctx[i].plane_res.scl_data;
- while (next_pipe) {
- data.h_active += next_pipe->plane_res.scl_data.h_active;
- data.recout.width += next_pipe->plane_res.scl_data.recout.width;
- if (in->rotation == ROTATION_ANGLE_0 || in->rotation == ROTATION_ANGLE_180) {
- data.viewport.width += next_pipe->plane_res.scl_data.viewport.width;
- } else {
- data.viewport.height += next_pipe->plane_res.scl_data.viewport.height;
- }
- next_pipe = next_pipe->next_odm_pipe;
- }
+ temp_pipe->stream = pipe->stream;
+ temp_pipe->plane_state = pipe->plane_state;
+ temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
+
+ resource_build_scaling_params(temp_pipe);
break;
}
}
ASSERT(i < MAX_PIPES);
- return data;
+ return temp_pipe->plane_res.scl_data;
}
static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
@@ -864,7 +857,7 @@ static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned
out->ScalerEnabled[location] = false;
}
-static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, const struct dc_state *context)
+static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context)
{
const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index f74ae0d41d3c..3a6bf77a6873 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -469,6 +469,8 @@ struct resource_context {
unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
bool is_mpc_3dlut_acquired[MAX_PIPES];
+ /* solely used for build scalar data in dml2 */
+ struct pipe_ctx temp_pipe;
};
struct dce_bw_output {
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 20/22] drm/amd/display: Populate invalid split index to be 0xF
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (18 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 19/22] drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 21/22] drm/amd/display: [FW Promotion] Release 0.0.202.0 Tom Chung
` (2 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Wenjing Liu, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, Alvin Lee,
wayne.lin, Harry.Wentland, agustin.gutierrez
From: Alvin Lee <alvin.lee2@amd.com>
[why]
There exists scenarios where the split index for subvp can be
pipe index 0. The assumption in FW is that the split index
won't be 0 but this is incorrect.
[how]
Instead populate non-split cases to be 0xF to differentiate
between split and non-split.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 3d7252218ea9..0ccdc0c979a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -780,7 +780,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
} else if (subvp_pipe->next_odm_pipe) {
pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
} else {
- pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
+ pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF;
}
// Find phantom pipe index based on phantom stream
@@ -795,7 +795,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
} else if (phantom_pipe->next_odm_pipe) {
pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
} else {
- pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
+ pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF;
}
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 21/22] drm/amd/display: [FW Promotion] Release 0.0.202.0
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (19 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 20/22] drm/amd/display: Populate invalid split index to be 0xF Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-24 7:01 ` [PATCH 22/22] drm/amd/display: 3.2.270 Tom Chung
2024-01-29 14:36 ` [PATCH 00/22] DC Patches Jan 29 2024 Wheeler, Daniel
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: chiahsuan.chung, Sunpeng.Li, Anthony Koo, Rodrigo.Siqueira,
roman.li, jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, agustin.gutierrez
From: Anthony Koo <anthony.koo@amd.com>
- Add control flag for IPS residency profiling
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 49bc1e41ac67..aaa211c828ed 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -408,7 +408,13 @@ union replay_debug_flags {
*/
uint32_t enable_ips_visual_confirm : 1;
- uint32_t reserved : 21;
+ /**
+ * 0x800 (bit 11)
+ * @enable_ips_residency_profiling: Enable IPS residency profiling
+ */
+ uint32_t enable_ips_residency_profiling : 1;
+
+ uint32_t reserved : 20;
} bitfields;
uint32_t u32All;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 22/22] drm/amd/display: 3.2.270
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (20 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 21/22] drm/amd/display: [FW Promotion] Release 0.0.202.0 Tom Chung
@ 2024-01-24 7:01 ` Tom Chung
2024-01-29 14:36 ` [PATCH 00/22] DC Patches Jan 29 2024 Wheeler, Daniel
22 siblings, 0 replies; 24+ messages in thread
From: Tom Chung @ 2024-01-24 7:01 UTC (permalink / raw
To: amd-gfx
Cc: Aric Cyr, chiahsuan.chung, Sunpeng.Li, Rodrigo.Siqueira, roman.li,
jerry.zuo, Aurabindo.Pillai, hersenxs.wu, wayne.lin,
Harry.Wentland, agustin.gutierrez
From: Aric Cyr <aric.cyr@amd.com>
- Add control flag for IPS residency profiling
- Populate invalid split index to be 0xF
- Fix dcn35 8k30 Underflow/Corruption Issue
- Fix DP audio settings
- Use correct phantom pipe when populating subvp pipe info
- Fix incorrect mpc_combine array size
- Fix DPSTREAM CLK on and off sequence
- Fix USB-C flag update after enc10 feature init
- Add debugfs disallow edp psr
- Unify optimize_required flags and VRR adjustments
- Increased min_dcfclk_mhz and min_fclk_mhz
- Fix static screen event mask definition change
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ee561d941f53..5d95b1e9dafb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -51,7 +51,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.269"
+#define DC_VER "3.2.270"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* RE: [PATCH 00/22] DC Patches Jan 29 2024
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
` (21 preceding siblings ...)
2024-01-24 7:01 ` [PATCH 22/22] drm/amd/display: 3.2.270 Tom Chung
@ 2024-01-29 14:36 ` Wheeler, Daniel
22 siblings, 0 replies; 24+ messages in thread
From: Wheeler, Daniel @ 2024-01-29 14:36 UTC (permalink / raw
To: Chung, ChiaHsuan (Tom), amd-gfx@lists.freedesktop.org
Cc: Chung, ChiaHsuan (Tom), Li, Sun peng (Leo), Siqueira, Rodrigo,
Li, Roman, Zuo, Jerry, Pillai, Aurabindo, Wu, Hersen, Lin, Wayne,
Wentland, Harry, Gutierrez, Agustin
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U])
* VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI])
* DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters])
* Thunderbolt (LG Ultrafine 5k)
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays)
* DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display)
* USB 4 (Kensington SD5700T and 1x 4k 60Hz display)
* PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports])
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
* Changing display configurations and settings
* Benchmark testing
* Feature testing (Freesync, etc.)
Automated testing includes (but is not limited to):
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The patchset consists of the amd-staging-drm-next branch (Head commit - dbed0943b062d0837668fef7ad4af18639e9b241 -> drm/amdgpu: Show vram vendor only if available) with new patches added on top of it.
Tested on Ubuntu 22.04.3, on Wayland and X11, using KDE Plasma and Gnome.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: Tom Chung <chiahsuan.chung@amd.com>
Sent: Wednesday, January 24, 2024 2:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>
Subject: [PATCH 00/22] DC Patches Jan 29 2024
This DC patchset brings improvements in multiple areas.
In summary, we have:
- Add control flag for IPS residency profiling
- Populate invalid split index to be 0xF
- Fix dcn35 8k30 Underflow/Corruption Issue
- Fix DP audio settings
- Use correct phantom pipe when populating subvp pipe info
- Fix incorrect mpc_combine array size
- Fix DPSTREAM CLK on and off sequence
- Fix USB-C flag update after enc10 feature init
- Add debugfs disallow edp psr
- Unify optimize_required flags and VRR adjustments
- Increased min_dcfclk_mhz and min_fclk_mhz
- Fix static screen event mask definition change
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Alvin Lee (2):
drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel
drm/amd/display: Populate invalid split index to be 0xF
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.202.0
Aric Cyr (2):
drm/amd/display: Unify optimize_required flags and VRR adjustments
drm/amd/display: 3.2.270
Charlene Liu (3):
Revert "drm/amd/display: initialize all the dpm level's stutter
latency"
drm/amd/display: fix USB-C flag update after enc10 feature init
drm/amd/display: fix DP audio settings
Dmytro Laktyushkin (1):
drm/amd/display: Fix DPSTREAM CLK on and off sequence
Eric Yang (1):
drm/amd/display: fix invalid reg access on DCN35 FPGA
Fangzhi Zuo (1):
drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue
Fudongwang (1):
drm/amd/display: refine code for dmcub inbox1 ring buffer debug
Hersen Wu (1):
drm/amd/display: add debugfs disallow edp psr
Mounika Adhuri (1):
drm/amd/display: clkmgr unittest with removal of warn & rename DCN35
ips handshake for idle
Nicholas Kazlauskas (2):
drm/amd/display: Wait before sending idle allow and after idle
disallow
drm/amd/display: Wait for mailbox ready when powering up DMCUB
Nicholas Susanto (1):
drm/amd/display: Underflow workaround by increasing SR exit latency
Sohaib Nadeem (1):
drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
Taimur Hassan (1):
drm/amd/display: Send DTBCLK disable message on first commit
Wenjing Liu (2):
drm/amd/display: fix incorrect mpc_combine array size
drm/amd/display: use correct phantom pipe when populating subvp pipe
info
Yiling Chen (1):
drm/amd/display: Fix static screen event mask definition change
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 7 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 53 +++++++++++++++++++ .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 53 ++++++++++--------- .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 15 ++++++
drivers/gpu/drm/amd/display/dc/core/dc.c | 45 ++++++++++++----
.../gpu/drm/amd/display/dc/core/dc_resource.c | 14 +++++
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 14 +++--
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 -
.../gpu/drm/amd/display/dc/dce/dce_audio.c | 9 +++-
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 4 +- .../display/dc/dcn32/dcn32_resource_helpers.c | 14 ----- .../display/dc/dcn35/dcn35_dio_link_encoder.c | 4 +- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 15 +++--- .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 +- .../display/dc/dml2/dml2_translation_helper.c | 33 +++++------- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 20 ++++---
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 18 -------
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 3 --
.../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 +-
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 18 +++++++
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.h | 4 ++
.../amd/display/dc/hwss/dcn31/dcn31_init.c | 2 +-
.../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 +-
.../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 +-
.../amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 2 +-
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 ++
.../dc/resource/dcn32/dcn32_resource.c | 2 +-
.../dc/resource/dcn32/dcn32_resource.h | 3 --
.../dc/resource/dcn321/dcn321_resource.c | 2 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4 --
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 18 ++++---
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 ++++-
39 files changed, 274 insertions(+), 150 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 24+ messages in thread
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Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-24 7:01 [PATCH 00/22] DC Patches Jan 29 2024 Tom Chung
2024-01-24 7:01 ` [PATCH 01/22] drm/amd/display: Fix static screen event mask definition change Tom Chung
2024-01-24 7:01 ` [PATCH 02/22] Revert "drm/amd/display: initialize all the dpm level's stutter latency" Tom Chung
2024-01-24 7:01 ` [PATCH 03/22] drm/amd/display: Wait before sending idle allow and after idle disallow Tom Chung
2024-01-24 7:01 ` [PATCH 04/22] drm/amd/display: Wait for mailbox ready when powering up DMCUB Tom Chung
2024-01-24 7:01 ` [PATCH 05/22] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Tom Chung
2024-01-24 7:01 ` [PATCH 06/22] drm/amd/display: Unify optimize_required flags and VRR adjustments Tom Chung
2024-01-24 7:01 ` [PATCH 07/22] drm/amd/display: For FPO and SubVP/DRR configs program vmin/max sel Tom Chung
2024-01-24 7:01 ` [PATCH 08/22] drm/amd/display: add debugfs disallow edp psr Tom Chung
2024-01-24 7:01 ` [PATCH 09/22] drm/amd/display: fix USB-C flag update after enc10 feature init Tom Chung
2024-01-24 7:01 ` [PATCH 10/22] drm/amd/display: Send DTBCLK disable message on first commit Tom Chung
2024-01-24 7:01 ` [PATCH 11/22] drm/amd/display: refine code for dmcub inbox1 ring buffer debug Tom Chung
2024-01-24 7:01 ` [PATCH 12/22] drm/amd/display: fix invalid reg access on DCN35 FPGA Tom Chung
2024-01-24 7:01 ` [PATCH 13/22] drm/amd/display: Fix DPSTREAM CLK on and off sequence Tom Chung
2024-01-24 7:01 ` [PATCH 14/22] drm/amd/display: fix incorrect mpc_combine array size Tom Chung
2024-01-24 7:01 ` [PATCH 15/22] drm/amd/display: use correct phantom pipe when populating subvp pipe info Tom Chung
2024-01-24 7:01 ` [PATCH 16/22] drm/amd/display: Underflow workaround by increasing SR exit latency Tom Chung
2024-01-24 7:01 ` [PATCH 17/22] drm/amd/display: fix DP audio settings Tom Chung
2024-01-24 7:01 ` [PATCH 18/22] drm/amd/display: clkmgr unittest with removal of warn & rename DCN35 ips handshake for idle Tom Chung
2024-01-24 7:01 ` [PATCH 19/22] drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue Tom Chung
2024-01-24 7:01 ` [PATCH 20/22] drm/amd/display: Populate invalid split index to be 0xF Tom Chung
2024-01-24 7:01 ` [PATCH 21/22] drm/amd/display: [FW Promotion] Release 0.0.202.0 Tom Chung
2024-01-24 7:01 ` [PATCH 22/22] drm/amd/display: 3.2.270 Tom Chung
2024-01-29 14:36 ` [PATCH 00/22] DC Patches Jan 29 2024 Wheeler, Daniel
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