* [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations
@ 2019-08-09 4:27 Tao Zhou
[not found] ` <20190809042731.30491-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Tao Zhou @ 2019-08-09 4:27 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
alexander.deucher-5C7GfCeVMHo, hawking.zhang-5C7GfCeVMHo,
christian.koenig-5C7GfCeVMHo
Cc: Tao Zhou
implement 64 bits operations via 32 bits interface
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 9efdd66279e5..a617dcc9d257 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -21,6 +21,15 @@
#ifndef __AMDGPU_UMC_H__
#define __AMDGPU_UMC_H__
+/* implement 64 bits REG operations via 32 bits interface */
+#define RREG64_UMC(reg) (RREG32(reg) | \
+ ((uint64_t)RREG32((reg) + 1) << 32))
+#define WREG64_UMC(reg, v) \
+ do { \
+ WREG32((reg), (uint32_t)((v) & 0xffffffff)); \
+ WREG32((reg) + 1, (uint32_t)((v) >> 32)); \
+ } while (0)
+
/*
* void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
* uint32_t umc_reg_offset, uint32_t channel_index)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 64df37b860dd..8502e736f721 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
/* check for SRAM correctable error
MCUMC_STATUS is a 64 bit register */
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
@@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
/* check the MCUMC_STATUS */
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
@@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
/* skip error address process if -ENOMEM */
if (!err_data->err_addr) {
/* clear umc status */
- WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
return;
}
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
/* calculate error address if ue/ce error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
@@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
}
/* clear umc status */
- WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
}
static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
--
2.17.1
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* [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64
[not found] ` <20190809042731.30491-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 4:27 ` Tao Zhou
[not found] ` <20190809042731.30491-2-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 6:41 ` [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations Koenig, Christian
1 sibling, 1 reply; 7+ messages in thread
From: Tao Zhou @ 2019-08-09 4:27 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
alexander.deucher-5C7GfCeVMHo, hawking.zhang-5C7GfCeVMHo,
christian.koenig-5C7GfCeVMHo
Cc: Tao Zhou
atomic 64 bits REG operations are useless currently
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 ----------------------
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ed1a217e86e4..f6ae5652b2e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1042,8 +1042,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags);
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg);
-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
@@ -1071,8 +1069,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
-#define RREG64(reg) amdgpu_mm_rreg64(adev, (reg))
-#define WREG64(reg, v) amdgpu_mm_wreg64(adev, (reg), (v))
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7eb9e0b9235a..2f43c58f5d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -262,39 +262,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
}
}
-/**
- * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 64 bit value from the offset specified.
- */
-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
-{
- if ((reg * 4) < adev->rmmio_size)
- return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
- else
- BUG();
-}
-
-/**
- * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- * @v: 64 bit value to write to the register
- *
- * Writes the value specified to the offset specified.
- */
-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
-{
- if ((reg * 4) < adev->rmmio_size)
- atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
- else
- BUG();
-}
-
/**
* amdgpu_io_rreg - read an IO register
*
--
2.17.1
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* RE: [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64
[not found] ` <20190809042731.30491-2-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 4:41 ` Zhang, Hawking
2019-08-09 6:42 ` Koenig, Christian
1 sibling, 0 replies; 7+ messages in thread
From: Zhang, Hawking @ 2019-08-09 4:41 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Deucher, Alexander, Koenig, Christian
Cc: Zhou1, Tao
Series is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tao Zhou
Sent: 2019年8月9日 12:28
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64
atomic 64 bits REG operations are useless currently
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 ----------------------
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ed1a217e86e4..f6ae5652b2e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1042,8 +1042,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags);
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); -uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg); -void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); @@ -1071,8 +1069,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) -#define RREG64(reg) amdgpu_mm_rreg64(adev, (reg)) -#define WREG64(reg, v) amdgpu_mm_wreg64(adev, (reg), (v)) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7eb9e0b9235a..2f43c58f5d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -262,39 +262,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
}
}
-/**
- * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 64 bit value from the offset specified.
- */
-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg) -{
- if ((reg * 4) < adev->rmmio_size)
- return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
- else
- BUG();
-}
-
-/**
- * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- * @v: 64 bit value to write to the register
- *
- * Writes the value specified to the offset specified.
- */
-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) -{
- if ((reg * 4) < adev->rmmio_size)
- atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
- else
- BUG();
-}
-
/**
* amdgpu_io_rreg - read an IO register
*
--
2.17.1
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* Re: [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations
[not found] ` <20190809042731.30491-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 4:27 ` [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64 Tao Zhou
@ 2019-08-09 6:41 ` Koenig, Christian
1 sibling, 0 replies; 7+ messages in thread
From: Koenig, Christian @ 2019-08-09 6:41 UTC (permalink / raw
To: Zhou1, Tao,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Deucher, Alexander, Zhang, Hawking
Am 09.08.19 um 06:27 schrieb Tao Zhou:
> implement 64 bits operations via 32 bits interface
>
> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 9 +++++++++
> drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> index 9efdd66279e5..a617dcc9d257 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> @@ -21,6 +21,15 @@
> #ifndef __AMDGPU_UMC_H__
> #define __AMDGPU_UMC_H__
>
> +/* implement 64 bits REG operations via 32 bits interface */
> +#define RREG64_UMC(reg) (RREG32(reg) | \
> + ((uint64_t)RREG32((reg) + 1) << 32))
> +#define WREG64_UMC(reg, v) \
Maybe call this WREG_LO_HI and RREG_LO_HI to explicitly note what they
are doing. This way we can probably keep them in amdgpu.h as well.
> + do { \
> + WREG32((reg), (uint32_t)((v) & 0xffffffff)); \
> + WREG32((reg) + 1, (uint32_t)((v) >> 32)); \
I think I now understand why you wanted to have this macro.
We have explicit lower_32_bits() and upper_32_bits() functions to avoid
the masking and shifting and make the code more readable.
For example see the UVD code:
> WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> lower_32_bits(adev->vcn.gpu_addr));
> WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> upper_32_bits(adev->vcn.gpu_addr));
I suggest to use those in your macro here as well, apart from that the
patch looks good to me.
Thanks for taking care of this,
Christian.
> + } while (0)
> +
> /*
> * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
> * uint32_t umc_reg_offset, uint32_t channel_index)
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> index 64df37b860dd..8502e736f721 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> @@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
>
> /* check for SRAM correctable error
> MCUMC_STATUS is a 64 bit register */
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
> if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
> @@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
> SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
>
> /* check the MCUMC_STATUS */
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
> if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
> (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
> @@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
> /* skip error address process if -ENOMEM */
> if (!err_data->err_addr) {
> /* clear umc status */
> - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> return;
> }
>
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
>
> /* calculate error address if ue/ce error is detected */
> if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> @@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
> }
>
> /* clear umc status */
> - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> }
>
> static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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* Re: [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64
[not found] ` <20190809042731.30491-2-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 4:41 ` Zhang, Hawking
@ 2019-08-09 6:42 ` Koenig, Christian
1 sibling, 0 replies; 7+ messages in thread
From: Koenig, Christian @ 2019-08-09 6:42 UTC (permalink / raw
To: Zhou1, Tao,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Deucher, Alexander, Zhang, Hawking
Am 09.08.19 um 06:27 schrieb Tao Zhou:
> atomic 64 bits REG operations are useless currently
>
> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 ----------------------
> 2 files changed, 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ed1a217e86e4..f6ae5652b2e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1042,8 +1042,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> uint32_t acc_flags);
> void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
> uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
> -uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg);
> -void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
>
> u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
> void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
> @@ -1071,8 +1069,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
> #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
> #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
> -#define RREG64(reg) amdgpu_mm_rreg64(adev, (reg))
> -#define WREG64(reg, v) amdgpu_mm_wreg64(adev, (reg), (v))
> #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
> #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7eb9e0b9235a..2f43c58f5d03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -262,39 +262,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> }
> }
>
> -/**
> - * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
> - *
> - * @adev: amdgpu_device pointer
> - * @reg: dword aligned register offset
> - *
> - * Returns the 64 bit value from the offset specified.
> - */
> -uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
> -{
> - if ((reg * 4) < adev->rmmio_size)
> - return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
> - else
> - BUG();
> -}
> -
> -/**
> - * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
> - *
> - * @adev: amdgpu_device pointer
> - * @reg: dword aligned register offset
> - * @v: 64 bit value to write to the register
> - *
> - * Writes the value specified to the offset specified.
> - */
> -void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
> -{
> - if ((reg * 4) < adev->rmmio_size)
> - atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
> - else
> - BUG();
> -}
> -
> /**
> * amdgpu_io_rreg - read an IO register
> *
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations
@ 2019-08-09 7:57 Tao Zhou
[not found] ` <20190809075751.5078-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Tao Zhou @ 2019-08-09 7:57 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
alexander.deucher-5C7GfCeVMHo, hawking.zhang-5C7GfCeVMHo,
christian.koenig-5C7GfCeVMHo
Cc: Tao Zhou
implement 64 bits operations via 32 bits interface
v2: make use of lower_32_bits() and upper_32_bits() macros
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 9efdd66279e5..975afa04df09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -21,6 +21,15 @@
#ifndef __AMDGPU_UMC_H__
#define __AMDGPU_UMC_H__
+/* implement 64 bits REG operations via 32 bits interface */
+#define RREG64_UMC(reg) (RREG32(reg) | \
+ ((uint64_t)RREG32((reg) + 1) << 32))
+#define WREG64_UMC(reg, v) \
+ do { \
+ WREG32((reg), lower_32_bits(v)); \
+ WREG32((reg) + 1, upper_32_bits(v)); \
+ } while (0)
+
/*
* void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
* uint32_t umc_reg_offset, uint32_t channel_index)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 64df37b860dd..8502e736f721 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
/* check for SRAM correctable error
MCUMC_STATUS is a 64 bit register */
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
@@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
/* check the MCUMC_STATUS */
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
@@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
/* skip error address process if -ENOMEM */
if (!err_data->err_addr) {
/* clear umc status */
- WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
return;
}
- mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
/* calculate error address if ue/ce error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
@@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
}
/* clear umc status */
- WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
}
static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations
[not found] ` <20190809075751.5078-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 8:41 ` Koenig, Christian
0 siblings, 0 replies; 7+ messages in thread
From: Koenig, Christian @ 2019-08-09 8:41 UTC (permalink / raw
To: Zhou1, Tao,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Deucher, Alexander, Zhang, Hawking
Reviewed-by: Christian König <christian.koenig@amd.com> for the series.
Am 09.08.19 um 09:57 schrieb Tao Zhou:
> implement 64 bits operations via 32 bits interface
>
> v2: make use of lower_32_bits() and upper_32_bits() macros
>
> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 9 +++++++++
> drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> index 9efdd66279e5..975afa04df09 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> @@ -21,6 +21,15 @@
> #ifndef __AMDGPU_UMC_H__
> #define __AMDGPU_UMC_H__
>
> +/* implement 64 bits REG operations via 32 bits interface */
> +#define RREG64_UMC(reg) (RREG32(reg) | \
> + ((uint64_t)RREG32((reg) + 1) << 32))
> +#define WREG64_UMC(reg, v) \
> + do { \
> + WREG32((reg), lower_32_bits(v)); \
> + WREG32((reg) + 1, upper_32_bits(v)); \
> + } while (0)
> +
> /*
> * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
> * uint32_t umc_reg_offset, uint32_t channel_index)
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> index 64df37b860dd..8502e736f721 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
> @@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
>
> /* check for SRAM correctable error
> MCUMC_STATUS is a 64 bit register */
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
> if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
> @@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
> SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
>
> /* check the MCUMC_STATUS */
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
> if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
> (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
> REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
> @@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
> /* skip error address process if -ENOMEM */
> if (!err_data->err_addr) {
> /* clear umc status */
> - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> return;
> }
>
> - mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
> + mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
>
> /* calculate error address if ue/ce error is detected */
> if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> @@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
> }
>
> /* clear umc status */
> - WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> + WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
> }
>
> static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-08-09 8:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2019-08-09 4:27 [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations Tao Zhou
[not found] ` <20190809042731.30491-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 4:27 ` [PATCH 2/2] drm/amdgpu: remove RREG64/WREG64 Tao Zhou
[not found] ` <20190809042731.30491-2-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 4:41 ` Zhang, Hawking
2019-08-09 6:42 ` Koenig, Christian
2019-08-09 6:41 ` [PATCH 1/2] drm/amdgpu: implement UMC 64 bits REG operations Koenig, Christian
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2019-08-09 7:57 Tao Zhou
[not found] ` <20190809075751.5078-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-09 8:41 ` Koenig, Christian
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