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Sun, 31 Mar 2024 10:49:26 -0700 (PDT) Received: from [100.64.0.1] ([170.85.6.190]) by smtp.gmail.com with ESMTPSA id d11-20020a5d964b000000b007cc840d1d0bsm2217439ios.25.2024.03.31.10.49.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Mar 2024 10:49:26 -0700 (PDT) Message-ID: Date: Sun, 31 Mar 2024 12:49:23 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions To: Conor Dooley , Conor Dooley Cc: Stefan O'Rear , Pu Lehui , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Samuel Holland Content-Language: en-US In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240331_104928_672500_9F9266B5 X-CRM114-Status: GOOD ( 36.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Conor, Looks good except for one typo. On 2024-03-29 6:23 AM, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. s/vector/floating point/ here. Regards, Samuel > > If you don't know what to do here, say Y. > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EFFE2F3A for ; Sun, 31 Mar 2024 17:49:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711907370; cv=none; b=cTy3gCHKyMJMMYz294FqOMRDwUsMS5nz3yoqcYWoCIVSwuPV2I205QDj/J+D25RF6UnqLqX8gUoP+AviLtfG2MM1+DW4+pkeKoEK7SIcSz8LwtBjPTCCTl61oa7MVQ4kUijz5KiCj9Z5pI1RBKbHMapN+q+vfbtNzC5Qxef4ZU4= ARC-Message-Signature:i=1; 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Sun, 31 Mar 2024 10:49:26 -0700 (PDT) Message-ID: Date: Sun, 31 Mar 2024 12:49:23 -0500 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions To: Conor Dooley , Conor Dooley Cc: Stefan O'Rear , Pu Lehui , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Samuel Holland Content-Language: en-US In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Conor, Looks good except for one typo. On 2024-03-29 6:23 AM, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. s/vector/floating point/ here. Regards, Samuel > > If you don't know what to do here, say Y. > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv