* [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC
@ 2023-11-20 11:18 Claudiu
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
` (8 more replies)
0 siblings, 9 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
Series adds support for IA55 available on RZ/G3S SoC.
Patches are split as follows:
- 1/9 adds IA55 clock
- 2-4/9 minor cleanups to align with the suggestions at [1] and
coding style recommendations
- 5/9 implement restriction described in HW manual for ISCR register
- 6/9 add a macro to retrieve TITSR base address based on it's index
- 7/9 add suspend to RAM support
- 8/9 updates documentation
- 9/9 adds IA55 device tree node
Thank you,
Claudiu Beznea
[1] https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
Changes in v3:
- kept driver private data object as pointer
- moved patch 1/9 from v2 (dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S)
after IRQ controller driver feature patches
Changes in v2:
- collected Conor's tag
- updated commit description according to code review comments
- added patches 4, 5 according to review recommendations
- updated patch 7/9 to retrieve only TITSR base address; dropped the rest
of the changes for the moment
- in patch 8/9 use local variable in suspend/resume functions for controller's
base address, indent initialized structures members to tabs, updated
private driver data structure name
- patch 3/7 from v1 was replaced by patch 7/9 in v2
- patch 5/7 from v1 was renamed "Add support for suspend to RAM"
- cleanup patches were kept at the beginning of the series and features at the end
Claudiu Beznea (9):
clk: renesas: r9a08g045: Add IA55 pclk and its reset
irqchip/renesas-rzg2l: Use tabs instead of spaces
irqchip/renesas-rzg2l: Align struct member names to tabs
irqchip/renesas-rzg2l: Document structure members
irqchip/renesas-rzg2l: Implement restriction when writing ISCR
register
irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset
based on register's index
irqchip/renesas-rzg2l: Add support for suspend to RAM
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
.../renesas,rzg2l-irqc.yaml | 5 +-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 +++++++++++
drivers/clk/renesas/r9a08g045-cpg.c | 3 +
drivers/irqchip/irq-renesas-rzg2l.c | 110 +++++++++++++-----
4 files changed, 158 insertions(+), 28 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 9:59 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
` (7 subsequent siblings)
8 siblings, 2 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
its reset.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/clk/renesas/r9a08g045-cpg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 4394cb241d99..ea3beca8b4e0 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
@@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A08G045_IA55_PCLK,
MOD_CLK_BASE + R9A08G045_IA55_CLK,
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:07 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
` (6 subsequent siblings)
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ()
and TINT_EXTRACT_GPIOINT() macros to align with coding style
requirements described in Documentation/process/coding-style.rst,
"Indentation" chapter.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index fe8d516f3614..cc42cbd05762 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -53,8 +53,8 @@
#define IITSR_IITSEL_EDGE_BOTH 3
#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
-#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
-#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
+#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
void __iomem *base;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:09 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
` (5 subsequent siblings)
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Align struct member names to tabs to follow the requirements from
maintainer-tip file. 3 tabs were used at the moment as the next commits
will add a new member which requires 3 tabs for a better view.
Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index cc42cbd05762..90971ab06f0c 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -57,9 +57,9 @@
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
- void __iomem *base;
- struct irq_fwspec fwspec[IRQC_NUM_IRQ];
- raw_spinlock_t lock;
+ void __iomem *base;
+ struct irq_fwspec fwspec[IRQC_NUM_IRQ];
+ raw_spinlock_t lock;
};
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (2 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:10 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
` (4 subsequent siblings)
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Document structure members to follow the requirements specified in
maintainer-tip, section 4.3.7. Struct declarations and initializers.
Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 90971ab06f0c..d666912adc74 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -56,6 +56,12 @@
#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+/**
+ * struct rzg2l_irqc_priv - IRQ controller private data structure
+ * @base: controller's base address
+ * @fwspec: IRQ firmware specific data
+ * @lock: lock to protect concurrent access to hardware registers
+ */
struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (3 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:17 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
` (3 subsequent siblings)
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
the operation to clear interrupts through the ISCR register as follows:
[Write operation]
When "Falling-edge detection", "Rising-edge detection" or
"Falling/Rising-edge detection" is set in IITSR:
- In case ISTAT is 1
0: IRQn interrupt detection status is cleared.
1: Invalid to write.
- In case ISTAT is 0
Invalid to write.
When “Low-level detection” is set in IITSR.:
Invalid to write.
Take the interrupt type into account when clearing interrupts through
the ISCR register to avoid writing the ISCR when interrupt type is
level.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index d666912adc74..a77ac6e1606f 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)
unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
u32 bit = BIT(hw_irq);
- u32 reg;
+ u32 iitsr, iscr;
- reg = readl_relaxed(priv->base + ISCR);
- if (reg & bit)
- writel_relaxed(reg & ~bit, priv->base + ISCR);
+ iscr = readl_relaxed(priv->base + ISCR);
+ iitsr = readl_relaxed(priv->base + IITSR);
+
+ /*
+ * ISCR can only be cleared if the type is falling-edge, rising-edge or
+ * falling/rising-edge.
+ */
+ if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
+ writel_relaxed(iscr & ~bit, priv->base + ISCR);
}
static void rzg2l_tint_eoi(struct irq_data *d)
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (4 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:30 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
` (2 subsequent siblings)
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
There are 2 TITSR registers available on IA55 interrupt controller. A
single macro could be used to access both of them. Add a macro that
retrieves TITSR register offset based on it's index. This macro is
useful in commit that adds suspend/resume support to access both TITSR
registers in a for loop.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index a77ac6e1606f..45b696db220f 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -28,8 +28,7 @@
#define ISCR 0x10
#define IITSR 0x14
#define TSCR 0x20
-#define TITSR0 0x24
-#define TITSR1 0x28
+#define TITSR(n) (0x24 + (n) * 4)
#define TITSR0_MAX_INT 16
#define TITSEL_WIDTH 0x2
#define TSSR(n) (0x30 + ((n) * 4))
@@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
u32 titseln = hwirq - IRQC_TINT_START;
- u32 offset;
- u8 sense;
+ u8 index, sense;
u32 reg;
switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
return -EINVAL;
}
- offset = TITSR0;
+ index = 0;
if (titseln >= TITSR0_MAX_INT) {
titseln -= TITSR0_MAX_INT;
- offset = TITSR1;
+ index = 1;
}
raw_spin_lock(&priv->lock);
- reg = readl_relaxed(priv->base + offset);
+ reg = readl_relaxed(priv->base + TITSR(index));
reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
reg |= sense << (titseln * TITSEL_WIDTH);
- writel_relaxed(reg, priv->base + offset);
+ writel_relaxed(reg, priv->base + TITSR(index));
raw_spin_unlock(&priv->lock);
return 0;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (5 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
8 siblings, 2 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S could go to deep
sleep states where power to different SoC's parts are cut off and RAM is
switched to self-refresh. The resume from these states is done with the
help of bootloader.
IA55 IRQ controller needs to be reconfigured when resuming from deep sleep
state. For this the IA55 registers are cached in suspend and restored in
resume.
The IA55 IRQ controller is connected to GPIO controller and GIC as follows:
┌──────────┐ ┌──────────┐
│ │ SPIX │ │
│ ├─────────►│ │
│ │ │ │
│ │ │ │
┌────────┐IRQ0-7 │ IA55 │ │ GIC │
Pin0 ───────►│ ├─────────────►│ │ │ │
│ │ │ │ PPIY │ │
... │ GPIO │ │ ├─────────►│ │
│ │GPIOINT0-127 │ │ │ │
PinN ───────►│ ├─────────────►│ │ │ │
└────────┘ └──────────┘ └──────────┘
where:
- Pin0 is the first GPIO controller pin
- PinN is the last GPIO controller pin
- SPIX is the SPI interrupt with identifier X
- PPIY is the PPI interrupt with identifier Y
Suspend/resume functionality was implemented with syscore_ops to be able
to cache/restore the registers after/before GPIO controller suspend/resume
was called. As suspend/resume function members of syscore_ops doesn't take
any argument, to be able to access the cache data structure and
controller's base address from within suspend/resume functions, the driver
private data structure was declared as static in file, named
rzg2l_irqc_data and driver has been adjusted accordingly for this.
Because IA55 IRQC is resumed before GPIO controller and different GPIO
pins could be in unwanted state for IA55 IRQC (e.g. HiZ) when IA55
reconfiguration is done on resume path, to avoid spurious interrupts
the IA55 resume configures only interrupt type on resume. The interrupt
enable operation will be done at the end of GPIO controller resume.
The interrupt type reconfiguration was kept in IA55 driver to minimize
the number of subsystems interactions on suspend/resume b/w GPIO and
IA55 drivers (as the IRQ reconfiguration from GPIO driver is done with
IRQ specific APIs).
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzg2l.c | 68 ++++++++++++++++++++++++-----
1 file changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 45b696db220f..3c179ff0b2f0 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
#define IRQC_IRQ_START 1
#define IRQC_IRQ_COUNT 8
@@ -55,17 +56,29 @@
#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+/**
+ * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
+ * @iitsr: IITSR register
+ * @titsr: TITSR registers
+ */
+struct rzg2l_irqc_reg_cache {
+ u32 iitsr;
+ u32 titsr[2];
+};
+
/**
* struct rzg2l_irqc_priv - IRQ controller private data structure
* @base: controller's base address
* @fwspec: IRQ firmware specific data
* @lock: lock to protect concurrent access to hardware registers
+ * @cache: registers cache (necessary for suspend/resume)
*/
-struct rzg2l_irqc_priv {
+static struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
raw_spinlock_t lock;
-};
+ struct rzg2l_irqc_reg_cache cache;
+} *rzg2l_irqc_data;
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
{
@@ -246,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
}
+static int rzg2l_irqc_irq_suspend(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ cache->iitsr = readl_relaxed(base + IITSR);
+ for (u8 i = 0; i < 2; i++)
+ cache->titsr[i] = readl_relaxed(base + TITSR(i));
+
+ return 0;
+}
+
+static void rzg2l_irqc_irq_resume(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ /*
+ * Restore only interrupt type. TSSRx will be restored at the
+ * request of pin controller to avoid spurious interrupts due
+ * to invalid PIN states.
+ */
+ for (u8 i = 0; i < 2; i++)
+ writel_relaxed(cache->titsr[i], base + TITSR(i));
+ writel_relaxed(cache->iitsr, base + IITSR);
+}
+
+static struct syscore_ops rzg2l_irqc_syscore_ops = {
+ .suspend = rzg2l_irqc_irq_suspend,
+ .resume = rzg2l_irqc_irq_resume,
+};
+
static const struct irq_chip irqc_chip = {
.name = "rzg2l-irqc",
.irq_eoi = rzg2l_irqc_eoi,
@@ -331,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
struct irq_domain *irq_domain, *parent_domain;
struct platform_device *pdev;
struct reset_control *resetn;
- struct rzg2l_irqc_priv *priv;
int ret;
pdev = of_find_device_by_node(node);
@@ -344,15 +388,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
return -ENODEV;
}
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
+ rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
+ if (!rzg2l_irqc_data)
return -ENOMEM;
- priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+ if (IS_ERR(rzg2l_irqc_data->base))
+ return PTR_ERR(rzg2l_irqc_data->base);
- ret = rzg2l_irqc_parse_interrupts(priv, node);
+ ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
if (ret) {
dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
return ret;
@@ -375,17 +419,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
goto pm_disable;
}
- raw_spin_lock_init(&priv->lock);
+ raw_spin_lock_init(&rzg2l_irqc_data->lock);
irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
node, &rzg2l_irqc_domain_ops,
- priv);
+ rzg2l_irqc_data);
if (!irq_domain) {
dev_err(&pdev->dev, "failed to add irq domain\n");
ret = -ENOMEM;
goto pm_put;
}
+ register_syscore_ops(&rzg2l_irqc_syscore_ops);
+
return 0;
pm_put:
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (6 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-11-21 10:44 ` Geert Uytterhoeven
` (2 more replies)
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
8 siblings, 3 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea, Conor Dooley
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Document RZ/G3S (R9108G045) interrupt controller. This has few extra
functionalities compared with RZ/G2UL but the already existing driver
could still be used.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
.../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 2ef3081eaaf3..d3b5aec0a3f7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043u-irqc # RZ/G2UL
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
+ - renesas,r9a08g045-irqc # RZ/G3S
- const: renesas,rzg2l-irqc
'#interrupt-cells':
@@ -167,7 +168,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a07g043u-irqc
+ enum:
+ - renesas,r9a07g043u-irqc
+ - renesas,r9a08g045-irqc
then:
properties:
interrupts:
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
` (7 preceding siblings ...)
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
@ 2023-11-20 11:18 ` Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-13 14:18 ` [PATCH v3 9/9] " Geert Uytterhoeven
8 siblings, 2 replies; 39+ messages in thread
From: Claudiu @ 2023-11-20 11:18 UTC (permalink / raw
To: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add IA55 interrupt controller node and set it as interrupt parent for pin
controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 ++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 02a5dc9a0a3e..793512c4b31c 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -101,6 +101,7 @@ pinctrl: pinctrl@11030000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -109,6 +110,73 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@11050000 {
+ compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
+ <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_IA55_RESETN>;
+ };
+
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
@ 2023-11-21 9:59 ` Geert Uytterhoeven
2023-11-21 11:03 ` claudiu beznea
2023-12-13 14:11 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
1 sibling, 2 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 9:59 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj,
linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
Hi Claudiu,
On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
> its reset.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a08g045-cpg.c
> +++ b/drivers/clk/renesas/r9a08g045-cpg.c
> @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
>
> static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
> DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
> + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
This conflicts with [1], which you sent just before.
If that patch goes in first, I guess this new entry should gain
", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk?
> DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
> DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
> DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[1] "clk: renesas: rzg2l-cpg: Add support for MSTOP"
https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
@ 2023-11-21 10:07 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:07 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj,
linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ()
> and TINT_EXTRACT_GPIOINT() macros to align with coding style
> requirements described in Documentation/process/coding-style.rst,
> "Indentation" chapter.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
@ 2023-11-21 10:09 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:09 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
On Mon, Nov 20, 2023 at 1:00 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Align struct member names to tabs to follow the requirements from
> maintainer-tip file. 3 tabs were used at the moment as the next commits
> will add a new member which requires 3 tabs for a better view.
>
> Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
@ 2023-11-21 10:10 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:10 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
On Tue, Nov 21, 2023 at 7:16 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Document structure members to follow the requirements specified in
> maintainer-tip, section 4.3.7. Struct declarations and initializers.
>
> Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
@ 2023-11-21 10:17 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:17 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
[-- Attachment #1: Type: text/plain, Size: 1180 bytes --]
On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
> the operation to clear interrupts through the ISCR register as follows:
>
> [Write operation]
> When "Falling-edge detection", "Rising-edge detection" or
> "Falling/Rising-edge detection" is set in IITSR:
> - In case ISTAT is 1
> 0: IRQn interrupt detection status is cleared.
> 1: Invalid to write.
> - In case ISTAT is 0
> Invalid to write.
>
> When “Low-level detection” is set in IITSR.:
> Invalid to write.
>
> Take the interrupt type into account when clearing interrupts through
> the ISCR register to avoid writing the ISCR when interrupt type is
> level.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
@ 2023-11-21 10:30 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:30 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
Hi Claudiu,
Thanks for your patch!
On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> There are 2 TITSR registers available on IA55 interrupt controller. A
... the IA55 interrupt controller.
> single macro could be used to access both of them. Add a macro that
> retrieves TITSR register offset based on it's index. This macro is
the TITSR register offset ... its index
> useful in commit that adds suspend/resume support to access both TITSR
> registers in a for loop.
This macro will be useful to access both TITSR registers in a for loop
when adding suspend/resume support later/
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -28,8 +28,7 @@
> #define ISCR 0x10
> #define IITSR 0x14
> #define TSCR 0x20
> -#define TITSR0 0x24
> -#define TITSR1 0x28
> +#define TITSR(n) (0x24 + (n) * 4)
> #define TITSR0_MAX_INT 16
> #define TITSEL_WIDTH 0x2
> #define TSSR(n) (0x30 + ((n) * 4))
> @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
> struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> unsigned int hwirq = irqd_to_hwirq(d);
> u32 titseln = hwirq - IRQC_TINT_START;
> - u32 offset;
> - u8 sense;
> + u8 index, sense;
> u32 reg;
>
> switch (type & IRQ_TYPE_SENSE_MASK) {
> @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
> return -EINVAL;
> }
>
> - offset = TITSR0;
> + index = 0;
> if (titseln >= TITSR0_MAX_INT) {
> titseln -= TITSR0_MAX_INT;
> - offset = TITSR1;
> + index = 1;
> }
You can remove this if you would use ...
>
> raw_spin_lock(&priv->lock);
> - reg = readl_relaxed(priv->base + offset);
> + reg = readl_relaxed(priv->base + TITSR(index));
... TITSR(titseln / TITSR0_MAX_INT) here.
> reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
> reg |= sense << (titseln * TITSEL_WIDTH);
> - writel_relaxed(reg, priv->base + offset);
> + writel_relaxed(reg, priv->base + TITSR(index));
> raw_spin_unlock(&priv->lock);
>
> return 0;
> --
> 2.39.2
>
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
@ 2023-11-21 10:44 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-11-21 10:44 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea,
Conor Dooley
On Tue, Nov 21, 2023 at 9:25 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Document RZ/G3S (R9108G045) interrupt controller. This has few extra
> functionalities compared with RZ/G2UL but the already existing driver
> could still be used.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -26,6 +26,7 @@ properties:
> - renesas,r9a07g043u-irqc # RZ/G2UL
> - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> - renesas,r9a07g054-irqc # RZ/V2L
> + - renesas,r9a08g045-irqc # RZ/G3S
> - const: renesas,rzg2l-irqc
>
> '#interrupt-cells':
> @@ -167,7 +168,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: renesas,r9a07g043u-irqc
> + enum:
> + - renesas,r9a07g043u-irqc
> + - renesas,r9a08g045-irqc
> then:
> properties:
> interrupts:
Prabhakar: How come we thought RZ/G2L and RZ/V2L do not have the bus
error interrupt? Looks like all the conditional handling can be removed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-11-21 9:59 ` Geert Uytterhoeven
@ 2023-11-21 11:03 ` claudiu beznea
2023-12-13 14:11 ` Geert Uytterhoeven
1 sibling, 0 replies; 39+ messages in thread
From: claudiu beznea @ 2023-11-21 11:03 UTC (permalink / raw
To: Geert Uytterhoeven
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, geert+renesas,
magnus.damm, mturquette, sboyd, prabhakar.mahadev-lad.rj,
linux-kernel, devicetree, linux-renesas-soc, linux-clk,
Claudiu Beznea
Hi, Geert,
On 21.11.2023 11:59, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Mon, 20 Nov 2023, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
>> its reset.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/clk/renesas/r9a08g045-cpg.c
>> +++ b/drivers/clk/renesas/r9a08g045-cpg.c
>> @@ -188,6 +188,7 @@ static const struct cpg_core_clk
>> r9a08g045_core_clks[] __initconst = {
>>
>> static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
>> DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK,
>> R9A08G045_CLK_P1, 0x514, 0),
>> + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2,
>> 0x518, 0),
>
> This conflicts with [1], which you sent just before.
Sorry for that, I intended to adapt the one that will have ended up last in
your tree.
>
> If that patch goes in first, I guess this new entry should gain
> ", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk?
That's right.
Thank you,
Claudiu Beznea
>
>> DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1,
>> 0x518, 1),
>> DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3,
>> 0x52c, 0),
>> DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4,
>> 0x554, 0),
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> [1] "clk: renesas: rzg2l-cpg: Add support for MSTOP"
>
> https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* [tip: irq/core] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-09 16:24 ` Geert Uytterhoeven
2023-12-13 14:18 ` [PATCH v3 9/9] " Geert Uytterhoeven
1 sibling, 1 reply; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits; +Cc: Claudiu Beznea, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8794f5c3d2299670d16b2fb1e6657f5f33c1518c
Gitweb: https://git.kernel.org/tip/8794f5c3d2299670d16b2fb1e6657f5f33c1518c
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:20 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
Add IA55 interrupt controller node and set it as interrupt parent for pin
controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 +++++++++++++++++++++-
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 6c7b29b..010bca6 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -96,6 +96,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -104,6 +105,73 @@
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@11050000 {
+ compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
+ <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_IA55_RESETN>;
+ };
+
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
2023-11-21 10:44 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, Conor Dooley,
x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 7e8213bb5ded82dbc6164100fe0e80f7934e9e56
Gitweb: https://git.kernel.org/tip/7e8213bb5ded82dbc6164100fe0e80f7934e9e56
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:19 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
Document the RZ/G3S (R9108G045) interrupt controller. This has few extra
functionalities compared with RZ/G2UL but the already existing driver
can still be used.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231120111820.87398-9-claudiu.beznea.uj@bp.renesas.com
---
Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 2ef3081..d3b5aec 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043u-irqc # RZ/G2UL
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
+ - renesas,r9a08g045-irqc # RZ/G3S
- const: renesas,rzg2l-irqc
'#interrupt-cells':
@@ -167,7 +168,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a07g043u-irqc
+ enum:
+ - renesas,r9a07g043u-irqc
+ - renesas,r9a08g045-irqc
then:
properties:
interrupts:
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Add support for suspend to RAM
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
1 sibling, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits; +Cc: Claudiu Beznea, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: e1f581386680631316611d554e71523a087d8f58
Gitweb: https://git.kernel.org/tip/e1f581386680631316611d554e71523a087d8f58
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:18 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Add support for suspend to RAM
The irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S can go into
deep sleep states where power to different SoC's parts is cut off and RAM
is switched to self-refresh. The resume from these states is done with the
help of the bootloader.
The IA55 IRQ controller needs to be reconfigured when resuming from deep
sleep state. For this the IA55 registers are cached in suspend and restored
in resume.
The IA55 IRQ controller is connected to GPIO controller and GIC as follows:
┌──────────┐ ┌──────────┐
│ │ SPIX │ │
│ ├─────────►│ │
│ │ │ │
│ │ │ │
┌────────┐IRQ0-7 │ IA55 │ │ GIC │
Pin0 ───────►│ ├─────────────►│ │ │ │
│ │ │ │ PPIY │ │
... │ GPIO │ │ ├─────────►│ │
│ │GPIOINT0-127 │ │ │ │
PinN ───────►│ ├─────────────►│ │ │ │
└────────┘ └──────────┘ └──────────┘
where:
- Pin0 is the first GPIO controller pin
- PinN is the last GPIO controller pin
- SPIX is the SPI interrupt with identifier X
- PPIY is the PPI interrupt with identifier Y
Implement suspend/resume functionality with syscore_ops to be able to
cache/restore the registers after/before the GPIO controller suspend/resume
functions are invoked.
As the syscore_ops suspend/resume functions do not take any argument make
the driver private data static so it can be accessed from the
suspend/resume functions.
The IA55 interrupt controller is resumed before the GPIO controller. As
GPIO pins could be in an a state which causes spurious interrupts, the
reconfiguration of the interrupt controller is restricted to restore the
interrupt type and leave them disabled.
An eventually required interrupt enable operation will be done as part of
the GPIO controller resume function after restoring the GPIO state.
[ tglx: Massaged changelog ]
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-8-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 68 +++++++++++++++++++++++-----
1 file changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 34add75..9494fc2 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
#define IRQC_IRQ_START 1
#define IRQC_IRQ_COUNT 8
@@ -56,16 +57,28 @@
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
/**
+ * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
+ * @iitsr: IITSR register
+ * @titsr: TITSR registers
+ */
+struct rzg2l_irqc_reg_cache {
+ u32 iitsr;
+ u32 titsr[2];
+};
+
+/**
* struct rzg2l_irqc_priv - IRQ controller private data structure
* @base: Controller's base address
* @fwspec: IRQ firmware specific data
* @lock: Lock to serialize access to hardware registers
+ * @cache: Registers cache for suspend/resume
*/
-struct rzg2l_irqc_priv {
+static struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
raw_spinlock_t lock;
-};
+ struct rzg2l_irqc_reg_cache cache;
+} *rzg2l_irqc_data;
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
{
@@ -246,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
}
+static int rzg2l_irqc_irq_suspend(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ cache->iitsr = readl_relaxed(base + IITSR);
+ for (u8 i = 0; i < 2; i++)
+ cache->titsr[i] = readl_relaxed(base + TITSR(i));
+
+ return 0;
+}
+
+static void rzg2l_irqc_irq_resume(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ /*
+ * Restore only interrupt type. TSSRx will be restored at the
+ * request of pin controller to avoid spurious interrupts due
+ * to invalid PIN states.
+ */
+ for (u8 i = 0; i < 2; i++)
+ writel_relaxed(cache->titsr[i], base + TITSR(i));
+ writel_relaxed(cache->iitsr, base + IITSR);
+}
+
+static struct syscore_ops rzg2l_irqc_syscore_ops = {
+ .suspend = rzg2l_irqc_irq_suspend,
+ .resume = rzg2l_irqc_irq_resume,
+};
+
static const struct irq_chip irqc_chip = {
.name = "rzg2l-irqc",
.irq_eoi = rzg2l_irqc_eoi,
@@ -331,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
struct irq_domain *irq_domain, *parent_domain;
struct platform_device *pdev;
struct reset_control *resetn;
- struct rzg2l_irqc_priv *priv;
int ret;
pdev = of_find_device_by_node(node);
@@ -344,15 +388,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
return -ENODEV;
}
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
+ rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
+ if (!rzg2l_irqc_data)
return -ENOMEM;
- priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+ if (IS_ERR(rzg2l_irqc_data->base))
+ return PTR_ERR(rzg2l_irqc_data->base);
- ret = rzg2l_irqc_parse_interrupts(priv, node);
+ ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
if (ret) {
dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
return ret;
@@ -375,17 +419,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
goto pm_disable;
}
- raw_spin_lock_init(&priv->lock);
+ raw_spin_lock_init(&rzg2l_irqc_data->lock);
irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
node, &rzg2l_irqc_domain_ops,
- priv);
+ rzg2l_irqc_data);
if (!irq_domain) {
dev_err(&pdev->dev, "failed to add irq domain\n");
ret = -ENOMEM;
goto pm_put;
}
+ register_syscore_ops(&rzg2l_irqc_syscore_ops);
+
return 0;
pm_put:
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
2023-11-21 10:30 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits; +Cc: Claudiu Beznea, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 6789991d1049f194eb976d4b346b5def9cfc708a
Gitweb: https://git.kernel.org/tip/6789991d1049f194eb976d4b346b5def9cfc708a
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:17 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
There are 2 TITSR registers available on the IA55 interrupt controller.
Add a macro that retrieves the TITSR register offset based on it's
index. This macro is useful in when adding suspend/resume support so both
TITSR registers can be accessed in a for loop.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index d450417..34add75 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -28,8 +28,7 @@
#define ISCR 0x10
#define IITSR 0x14
#define TSCR 0x20
-#define TITSR0 0x24
-#define TITSR1 0x28
+#define TITSR(n) (0x24 + (n) * 4)
#define TITSR0_MAX_INT 16
#define TITSEL_WIDTH 0x2
#define TSSR(n) (0x30 + ((n) * 4))
@@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
u32 titseln = hwirq - IRQC_TINT_START;
- u32 offset;
- u8 sense;
+ u8 index, sense;
u32 reg;
switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
return -EINVAL;
}
- offset = TITSR0;
+ index = 0;
if (titseln >= TITSR0_MAX_INT) {
titseln -= TITSR0_MAX_INT;
- offset = TITSR1;
+ index = 1;
}
raw_spin_lock(&priv->lock);
- reg = readl_relaxed(priv->base + offset);
+ reg = readl_relaxed(priv->base + TITSR(index));
reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
reg |= sense << (titseln * TITSEL_WIDTH);
- writel_relaxed(reg, priv->base + offset);
+ writel_relaxed(reg, priv->base + TITSR(index));
raw_spin_unlock(&priv->lock);
return 0;
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
2023-11-21 10:17 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 0b57d3bb1cc5da335fd4c7a4b1996e7015f4b5d5
Gitweb: https://git.kernel.org/tip/0b57d3bb1cc5da335fd4c7a4b1996e7015f4b5d5
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:16 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
the operation to clear interrupts through the ISCR register as follows:
[Write operation]
When "Falling-edge detection", "Rising-edge detection" or
"Falling/Rising-edge detection" is set in IITSR:
- In case ISTAT is 1
0: IRQn interrupt detection status is cleared.
1: Invalid to write.
- In case ISTAT is 0
Invalid to write.
When "Low-level detection" is set in IITSR.:
Invalid to write.
Take the interrupt type into account when clearing interrupts through the
ISCR register to avoid writing the ISCR when the interrupt type is level.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 0a77927..d450417 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)
unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
u32 bit = BIT(hw_irq);
- u32 reg;
+ u32 iitsr, iscr;
- reg = readl_relaxed(priv->base + ISCR);
- if (reg & bit)
- writel_relaxed(reg & ~bit, priv->base + ISCR);
+ iscr = readl_relaxed(priv->base + ISCR);
+ iitsr = readl_relaxed(priv->base + IITSR);
+
+ /*
+ * ISCR can only be cleared if the type is falling-edge, rising-edge or
+ * falling/rising-edge.
+ */
+ if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
+ writel_relaxed(iscr & ~bit, priv->base + ISCR);
}
static void rzg2l_tint_eoi(struct irq_data *d)
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Document structure members
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
2023-11-21 10:10 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 72ee3924cdc8685cc12d29ac9cbbb6cb5c0256d1
Gitweb: https://git.kernel.org/tip/72ee3924cdc8685cc12d29ac9cbbb6cb5c0256d1
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:15 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Document structure members
Document structure members to follow the requirements specified in
maintainer-tip, section 4.3.7. Struct declarations and initializers.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-5-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 90971ab..0a77927 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -56,6 +56,12 @@
#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+/**
+ * struct rzg2l_irqc_priv - IRQ controller private data structure
+ * @base: Controller's base address
+ * @fwspec: IRQ firmware specific data
+ * @lock: Lock to serialize access to hardware registers
+ */
struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Align struct member names to tabs
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
2023-11-21 10:09 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 9f9dc0ff23a1c0418efec8c0e0479b267e436313
Gitweb: https://git.kernel.org/tip/9f9dc0ff23a1c0418efec8c0e0479b267e436313
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:14 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Align struct member names to tabs
Align struct member names to tabs to follow the requirements from
maintainer-tip file. 3 tabs were used at the moment as the next commits
will add a new member which requires 3 tabs for a better view.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-4-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index cc42cbd..90971ab 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -57,9 +57,9 @@
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
- void __iomem *base;
- struct irq_fwspec fwspec[IRQC_NUM_IRQ];
- raw_spinlock_t lock;
+ void __iomem *base;
+ struct irq_fwspec fwspec[IRQC_NUM_IRQ];
+ raw_spinlock_t lock;
};
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Use tabs instead of spaces
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
2023-11-21 10:07 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 663b1d8debac386b5cbcc1d65b92bbef6b9c9cc0
Gitweb: https://git.kernel.org/tip/663b1d8debac386b5cbcc1d65b92bbef6b9c9cc0
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:13 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
irqchip/renesas-rzg2l: Use tabs instead of spaces
Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ()
and TINT_EXTRACT_GPIOINT() macros to align with coding style
requirements described in Documentation/process/coding-style.rst,
"Indentation" chapter.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-3-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index fe8d516..cc42cbd 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -53,8 +53,8 @@
#define IITSR_IITSEL_EDGE_BOTH 3
#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
-#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
-#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
+#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
void __iomem *base;
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
2023-11-21 9:59 ` Geert Uytterhoeven
@ 2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea
2023-12-09 16:22 ` Geert Uytterhoeven
1 sibling, 1 reply; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-08 21:14 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 63385748bce1ef169438c123c7e32c021c0b9409
Gitweb: https://git.kernel.org/tip/63385748bce1ef169438c123c7e32c021c0b9409
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:12 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:34 +01:00
clk: renesas: r9a08g045: Add IA55 pclk and its reset
IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
its reset.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com
---
drivers/clk/renesas/r9a08g045-cpg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 4394cb2..ea3beca 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
@@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A08G045_IA55_PCLK,
MOD_CLK_BASE + R9A08G045_IA55_CLK,
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [tip: irq/core] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-09 16:22 ` Geert Uytterhoeven
0 siblings, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-12-09 16:22 UTC (permalink / raw
To: Thomas Gleixner; +Cc: linux-tip-commits, Claudiu Beznea, x86, linux-kernel, maz
Hi Thomas,
On Fri, Dec 8, 2023 at 10:14 PM tip-bot2 for Claudiu Beznea
<tip-bot2@linutronix.de> wrote:
> The following commit has been merged into the irq/core branch of tip:
>
> Commit-ID: 63385748bce1ef169438c123c7e32c021c0b9409
> Gitweb: https://git.kernel.org/tip/63385748bce1ef169438c123c7e32c021c0b9409
> Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> AuthorDate: Mon, 20 Nov 2023 13:18:12 +02:00
> Committer: Thomas Gleixner <tglx@linutronix.de>
> CommitterDate: Fri, 08 Dec 2023 22:06:34 +01:00
>
> clk: renesas: r9a08g045: Add IA55 pclk and its reset
Please do not apply Renesas clock patches to your tree without an
explicit ack (especially when there are nearby changes in flight).
Renesas clock patches are intended to go in through the renesas-clk
and clk trees.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [tip: irq/core] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-09 16:24 ` Geert Uytterhoeven
2023-12-12 14:41 ` Thomas Gleixner
0 siblings, 1 reply; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-12-09 16:24 UTC (permalink / raw
To: Thomas Gleixner; +Cc: linux-tip-commits, Claudiu Beznea, x86, linux-kernel, maz
Hi Thomas,
On Fri, Dec 8, 2023 at 10:16 PM tip-bot2 for Claudiu Beznea
<tip-bot2@linutronix.de> wrote:
> The following commit has been merged into the irq/core branch of tip:
>
> Commit-ID: 8794f5c3d2299670d16b2fb1e6657f5f33c1518c
> Gitweb: https://git.kernel.org/tip/8794f5c3d2299670d16b2fb1e6657f5f33c1518c
> Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> AuthorDate: Mon, 20 Nov 2023 13:18:20 +02:00
> Committer: Thomas Gleixner <tglx@linutronix.de>
> CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
>
> arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
Please do not apply Renesas DTS patches to your tree without an
explicit ack.
Renesas DTS patches are intended to go in through the renesas-devel
and soc trees.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [tip: irq/core] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
2023-12-09 16:24 ` Geert Uytterhoeven
@ 2023-12-12 14:41 ` Thomas Gleixner
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Gleixner @ 2023-12-12 14:41 UTC (permalink / raw
To: Geert Uytterhoeven
Cc: linux-tip-commits, Claudiu Beznea, x86, linux-kernel, maz
Geert!
On Sat, Dec 09 2023 at 17:24, Geert Uytterhoeven wrote:
> On Fri, Dec 8, 2023 at 10:16 PM tip-bot2 for Claudiu Beznea
> <tip-bot2@linutronix.de> wrote:
>> The following commit has been merged into the irq/core branch of tip:
>>
>> Commit-ID: 8794f5c3d2299670d16b2fb1e6657f5f33c1518c
>> Gitweb: https://git.kernel.org/tip/8794f5c3d2299670d16b2fb1e6657f5f33c1518c
>> Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> AuthorDate: Mon, 20 Nov 2023 13:18:20 +02:00
>> Committer: Thomas Gleixner <tglx@linutronix.de>
>> CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
>>
>> arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
>
> Please do not apply Renesas DTS patches to your tree without an
> explicit ack.
> Renesas DTS patches are intended to go in through the renesas-devel
> and soc trees.
Sorry. I had the impression this all belongs together. I zapped 1/9 and
9/9 and force pushed the branch. Should be gone in tomorrows next
^ permalink raw reply [flat|nested] 39+ messages in thread
* [tip: irq/core] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
2023-11-21 10:44 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, Conor Dooley,
x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 1cf0697a24ef60b3ce8be47090a6e8e79329d962
Gitweb: https://git.kernel.org/tip/1cf0697a24ef60b3ce8be47090a6e8e79329d962
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:19 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:42 +01:00
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
Document the RZ/G3S (R9108G045) interrupt controller. This has few extra
functionalities compared with RZ/G2UL but the already existing driver
can still be used.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231120111820.87398-9-claudiu.beznea.uj@bp.renesas.com
---
Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 2ef3081..d3b5aec 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043u-irqc # RZ/G2UL
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
+ - renesas,r9a08g045-irqc # RZ/G3S
- const: renesas,rzg2l-irqc
'#interrupt-cells':
@@ -167,7 +168,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a07g043u-irqc
+ enum:
+ - renesas,r9a07g043u-irqc
+ - renesas,r9a08g045-irqc
then:
properties:
interrupts:
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Add support for suspend to RAM
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
1 sibling, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits; +Cc: Claudiu Beznea, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 74d2ef5f6f4b2437e6292ab2502400e8048db4aa
Gitweb: https://git.kernel.org/tip/74d2ef5f6f4b2437e6292ab2502400e8048db4aa
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:18 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Add support for suspend to RAM
The irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S can go into
deep sleep states where power to different SoC's parts is cut off and RAM
is switched to self-refresh. The resume from these states is done with the
help of the bootloader.
The IA55 IRQ controller needs to be reconfigured when resuming from deep
sleep state. For this the IA55 registers are cached in suspend and restored
in resume.
The IA55 IRQ controller is connected to GPIO controller and GIC as follows:
┌──────────┐ ┌──────────┐
│ │ SPIX │ │
│ ├─────────►│ │
│ │ │ │
│ │ │ │
┌────────┐IRQ0-7 │ IA55 │ │ GIC │
Pin0 ───────►│ ├─────────────►│ │ │ │
│ │ │ │ PPIY │ │
... │ GPIO │ │ ├─────────►│ │
│ │GPIOINT0-127 │ │ │ │
PinN ───────►│ ├─────────────►│ │ │ │
└────────┘ └──────────┘ └──────────┘
where:
- Pin0 is the first GPIO controller pin
- PinN is the last GPIO controller pin
- SPIX is the SPI interrupt with identifier X
- PPIY is the PPI interrupt with identifier Y
Implement suspend/resume functionality with syscore_ops to be able to
cache/restore the registers after/before the GPIO controller suspend/resume
functions are invoked.
As the syscore_ops suspend/resume functions do not take any argument make
the driver private data static so it can be accessed from the
suspend/resume functions.
The IA55 interrupt controller is resumed before the GPIO controller. As
GPIO pins could be in an a state which causes spurious interrupts, the
reconfiguration of the interrupt controller is restricted to restore the
interrupt type and leave them disabled.
An eventually required interrupt enable operation will be done as part of
the GPIO controller resume function after restoring the GPIO state.
[ tglx: Massaged changelog ]
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-8-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 68 +++++++++++++++++++++++-----
1 file changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 34add75..9494fc2 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
#define IRQC_IRQ_START 1
#define IRQC_IRQ_COUNT 8
@@ -56,16 +57,28 @@
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
/**
+ * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
+ * @iitsr: IITSR register
+ * @titsr: TITSR registers
+ */
+struct rzg2l_irqc_reg_cache {
+ u32 iitsr;
+ u32 titsr[2];
+};
+
+/**
* struct rzg2l_irqc_priv - IRQ controller private data structure
* @base: Controller's base address
* @fwspec: IRQ firmware specific data
* @lock: Lock to serialize access to hardware registers
+ * @cache: Registers cache for suspend/resume
*/
-struct rzg2l_irqc_priv {
+static struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
raw_spinlock_t lock;
-};
+ struct rzg2l_irqc_reg_cache cache;
+} *rzg2l_irqc_data;
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
{
@@ -246,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
}
+static int rzg2l_irqc_irq_suspend(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ cache->iitsr = readl_relaxed(base + IITSR);
+ for (u8 i = 0; i < 2; i++)
+ cache->titsr[i] = readl_relaxed(base + TITSR(i));
+
+ return 0;
+}
+
+static void rzg2l_irqc_irq_resume(void)
+{
+ struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache;
+ void __iomem *base = rzg2l_irqc_data->base;
+
+ /*
+ * Restore only interrupt type. TSSRx will be restored at the
+ * request of pin controller to avoid spurious interrupts due
+ * to invalid PIN states.
+ */
+ for (u8 i = 0; i < 2; i++)
+ writel_relaxed(cache->titsr[i], base + TITSR(i));
+ writel_relaxed(cache->iitsr, base + IITSR);
+}
+
+static struct syscore_ops rzg2l_irqc_syscore_ops = {
+ .suspend = rzg2l_irqc_irq_suspend,
+ .resume = rzg2l_irqc_irq_resume,
+};
+
static const struct irq_chip irqc_chip = {
.name = "rzg2l-irqc",
.irq_eoi = rzg2l_irqc_eoi,
@@ -331,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
struct irq_domain *irq_domain, *parent_domain;
struct platform_device *pdev;
struct reset_control *resetn;
- struct rzg2l_irqc_priv *priv;
int ret;
pdev = of_find_device_by_node(node);
@@ -344,15 +388,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
return -ENODEV;
}
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
+ rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);
+ if (!rzg2l_irqc_data)
return -ENOMEM;
- priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+ if (IS_ERR(rzg2l_irqc_data->base))
+ return PTR_ERR(rzg2l_irqc_data->base);
- ret = rzg2l_irqc_parse_interrupts(priv, node);
+ ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);
if (ret) {
dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
return ret;
@@ -375,17 +419,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
goto pm_disable;
}
- raw_spin_lock_init(&priv->lock);
+ raw_spin_lock_init(&rzg2l_irqc_data->lock);
irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
node, &rzg2l_irqc_domain_ops,
- priv);
+ rzg2l_irqc_data);
if (!irq_domain) {
dev_err(&pdev->dev, "failed to add irq domain\n");
ret = -ENOMEM;
goto pm_put;
}
+ register_syscore_ops(&rzg2l_irqc_syscore_ops);
+
return 0;
pm_put:
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
2023-11-21 10:30 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits; +Cc: Claudiu Beznea, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 2eca4731cc66563b3919d8753dbd74d18c39f662
Gitweb: https://git.kernel.org/tip/2eca4731cc66563b3919d8753dbd74d18c39f662
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:17 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
There are 2 TITSR registers available on the IA55 interrupt controller.
Add a macro that retrieves the TITSR register offset based on it's
index. This macro is useful in when adding suspend/resume support so both
TITSR registers can be accessed in a for loop.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index d450417..34add75 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -28,8 +28,7 @@
#define ISCR 0x10
#define IITSR 0x14
#define TSCR 0x20
-#define TITSR0 0x24
-#define TITSR1 0x28
+#define TITSR(n) (0x24 + (n) * 4)
#define TITSR0_MAX_INT 16
#define TITSEL_WIDTH 0x2
#define TSSR(n) (0x30 + ((n) * 4))
@@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
u32 titseln = hwirq - IRQC_TINT_START;
- u32 offset;
- u8 sense;
+ u8 index, sense;
u32 reg;
switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
return -EINVAL;
}
- offset = TITSR0;
+ index = 0;
if (titseln >= TITSR0_MAX_INT) {
titseln -= TITSR0_MAX_INT;
- offset = TITSR1;
+ index = 1;
}
raw_spin_lock(&priv->lock);
- reg = readl_relaxed(priv->base + offset);
+ reg = readl_relaxed(priv->base + TITSR(index));
reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
reg |= sense << (titseln * TITSEL_WIDTH);
- writel_relaxed(reg, priv->base + offset);
+ writel_relaxed(reg, priv->base + TITSR(index));
raw_spin_unlock(&priv->lock);
return 0;
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
2023-11-21 10:17 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: ef88eefb1a81a8701eabb7d5ced761a66a465a49
Gitweb: https://git.kernel.org/tip/ef88eefb1a81a8701eabb7d5ced761a66a465a49
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:16 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
the operation to clear interrupts through the ISCR register as follows:
[Write operation]
When "Falling-edge detection", "Rising-edge detection" or
"Falling/Rising-edge detection" is set in IITSR:
- In case ISTAT is 1
0: IRQn interrupt detection status is cleared.
1: Invalid to write.
- In case ISTAT is 0
Invalid to write.
When "Low-level detection" is set in IITSR.:
Invalid to write.
Take the interrupt type into account when clearing interrupts through the
ISCR register to avoid writing the ISCR when the interrupt type is level.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 0a77927..d450417 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)
unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
u32 bit = BIT(hw_irq);
- u32 reg;
+ u32 iitsr, iscr;
- reg = readl_relaxed(priv->base + ISCR);
- if (reg & bit)
- writel_relaxed(reg & ~bit, priv->base + ISCR);
+ iscr = readl_relaxed(priv->base + ISCR);
+ iitsr = readl_relaxed(priv->base + IITSR);
+
+ /*
+ * ISCR can only be cleared if the type is falling-edge, rising-edge or
+ * falling/rising-edge.
+ */
+ if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
+ writel_relaxed(iscr & ~bit, priv->base + ISCR);
}
static void rzg2l_tint_eoi(struct irq_data *d)
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Document structure members
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
2023-11-21 10:10 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: b94f455372ad6e6b4da8e8ed9864d9c7daaf54b8
Gitweb: https://git.kernel.org/tip/b94f455372ad6e6b4da8e8ed9864d9c7daaf54b8
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:15 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Document structure members
Document structure members to follow the requirements specified in
maintainer-tip, section 4.3.7. Struct declarations and initializers.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-5-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 90971ab..0a77927 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -56,6 +56,12 @@
#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+/**
+ * struct rzg2l_irqc_priv - IRQ controller private data structure
+ * @base: Controller's base address
+ * @fwspec: IRQ firmware specific data
+ * @lock: Lock to serialize access to hardware registers
+ */
struct rzg2l_irqc_priv {
void __iomem *base;
struct irq_fwspec fwspec[IRQC_NUM_IRQ];
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Align struct member names to tabs
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
2023-11-21 10:09 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 02f6507640173addeeb3af035d2c6f0b3cff1567
Gitweb: https://git.kernel.org/tip/02f6507640173addeeb3af035d2c6f0b3cff1567
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:14 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Align struct member names to tabs
Align struct member names to tabs to follow the requirements from
maintainer-tip file. 3 tabs were used at the moment as the next commits
will add a new member which requires 3 tabs for a better view.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-4-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index cc42cbd..90971ab 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -57,9 +57,9 @@
#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
- void __iomem *base;
- struct irq_fwspec fwspec[IRQC_NUM_IRQ];
- raw_spinlock_t lock;
+ void __iomem *base;
+ struct irq_fwspec fwspec[IRQC_NUM_IRQ];
+ raw_spinlock_t lock;
};
static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [tip: irq/core] irqchip/renesas-rzg2l: Use tabs instead of spaces
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
2023-11-21 10:07 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2 siblings, 0 replies; 39+ messages in thread
From: tip-bot2 for Claudiu Beznea @ 2023-12-12 14:44 UTC (permalink / raw
To: linux-tip-commits
Cc: Claudiu Beznea, Thomas Gleixner, Geert Uytterhoeven, x86,
linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: c90b5c4e6554c1194d5f7cfe13dfd710a7661cab
Gitweb: https://git.kernel.org/tip/c90b5c4e6554c1194d5f7cfe13dfd710a7661cab
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:13 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00
irqchip/renesas-rzg2l: Use tabs instead of spaces
Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ()
and TINT_EXTRACT_GPIOINT() macros to align with coding style
requirements described in Documentation/process/coding-style.rst,
"Indentation" chapter.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-3-claudiu.beznea.uj@bp.renesas.com
---
drivers/irqchip/irq-renesas-rzg2l.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index fe8d516..cc42cbd 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -53,8 +53,8 @@
#define IITSR_IITSEL_EDGE_BOTH 3
#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
-#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
-#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
+#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
+#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
struct rzg2l_irqc_priv {
void __iomem *base;
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset
2023-11-21 9:59 ` Geert Uytterhoeven
2023-11-21 11:03 ` claudiu beznea
@ 2023-12-13 14:11 ` Geert Uytterhoeven
1 sibling, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-12-13 14:11 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
On Tue, Nov 21, 2023 at 10:59 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Mon, 20 Nov 2023, Claudiu wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and
> > its reset.
> >
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a08g045-cpg.c
> > +++ b/drivers/clk/renesas/r9a08g045-cpg.c
> > @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
> >
> > static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
> > DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
> > + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
>
> This conflicts with [1], which you sent just before.
>
> If that patch goes in first, I guess this new entry should gain
> ", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk?
>
> > DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
> > DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
> > DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> [1] "clk: renesas: rzg2l-cpg: Add support for MSTOP"
> https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com
As the MSTOP support is on hold, I will queue this in renesas-clk-for-v6.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
@ 2023-12-13 14:18 ` Geert Uytterhoeven
1 sibling, 0 replies; 39+ messages in thread
From: Geert Uytterhoeven @ 2023-12-13 14:18 UTC (permalink / raw
To: Claudiu
Cc: tglx, robh+dt, krzysztof.kozlowski+dt, conor+dt, magnus.damm,
mturquette, sboyd, prabhakar.mahadev-lad.rj, linux-kernel,
devicetree, linux-renesas-soc, linux-clk, Claudiu Beznea
On Wed, Nov 22, 2023 at 7:16 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add IA55 interrupt controller node and set it as interrupt parent for pin
> controller.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2023-12-13 14:18 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
2023-11-21 9:59 ` Geert Uytterhoeven
2023-11-21 11:03 ` claudiu beznea
2023-12-13 14:11 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-09 16:22 ` Geert Uytterhoeven
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
2023-11-21 10:07 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
2023-11-21 10:09 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
2023-11-21 10:10 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
2023-11-21 10:17 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
2023-11-21 10:30 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
2023-11-21 10:44 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-09 16:24 ` Geert Uytterhoeven
2023-12-12 14:41 ` Thomas Gleixner
2023-12-13 14:18 ` [PATCH v3 9/9] " Geert Uytterhoeven
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