* [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable
@ 2024-04-10 16:36 Jani Nikula
2024-04-10 16:36 ` [PATCH 1/3] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Jani Nikula @ 2024-04-10 16:36 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula
Rip the band-aid, it's not so bad after all. Well, at least for the
somewhat isolated VLV DSI. But it's a start.
Jani Nikula (3):
drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
drm/i915/dsi: add VLV_ prefix to VLV only register macros
drm/i915/dsi: pass i915 to register macros instead of implicit
variable
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 192 +++++------
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 6 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 325 +++++++++----------
4 files changed, 259 insertions(+), 266 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
@ 2024-04-10 16:36 ` Jani Nikula
2024-04-10 16:36 ` [PATCH 2/3] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2024-04-10 16:36 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula
There are other unused registers, but this is also unusable and
inadequate. Remove.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index abbe427e462e..b0cdaad7db9c 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -93,9 +93,6 @@
#define TEARING_EFFECT_DELAY_SHIFT 0
#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
-/* XXX: all bits reserved */
-#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
-
/* MIPI DSI Controller and D-PHY registers */
#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/i915/dsi: add VLV_ prefix to VLV only register macros
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
2024-04-10 16:36 ` [PATCH 1/3] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula
@ 2024-04-10 16:36 ` Jani Nikula
2024-04-10 16:36 ` [PATCH 3/3] drm/i915/dsi: pass i915 to register macros instead of implicit variable Jani Nikula
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2024-04-10 16:36 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula
All the BXT specific macros have BXT_ prefix, do the same for VLV for
consistency.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 +++---
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 63f4af601d15..665247a2e834 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -481,7 +481,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
* Common bit for both MIPI Port A & MIPI Port C
* No similar bit in MIPI Port C reg
*/
- intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
+ intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
@@ -563,7 +563,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port)
{
return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ?
- BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
+ BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
}
static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
@@ -576,7 +576,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
- BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
+ BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
DEVICE_READY | ULPS_STATE_ENTER);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index b0cdaad7db9c..12a608a73720 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -40,7 +40,7 @@
#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
-#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
+#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
/* BXT port control */
#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
@@ -89,7 +89,7 @@
#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
-#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
+#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
#define TEARING_EFFECT_DELAY_SHIFT 0
#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/i915/dsi: pass i915 to register macros instead of implicit variable
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
2024-04-10 16:36 ` [PATCH 1/3] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula
2024-04-10 16:36 ` [PATCH 2/3] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula
@ 2024-04-10 16:36 ` Jani Nikula
2024-04-10 18:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2024-04-10 16:36 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula
Stop relying on the dev_priv local variable in the DSI register
macros. Pass i915 pointer to the macros. Move the MIPI DSI MMIO base
selection to a different level, passing it to _MMIO_MIPI() and doing the
addition there.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Tip: Applying the patch and using 'git show --color-words' is probably
the easiest way to review.
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 186 +++++------
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 6 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 322 +++++++++----------
4 files changed, 256 insertions(+), 260 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 912213ee0250..f17c2ba537f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3742,7 +3742,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
if (!(tmp & DPI_ENABLE))
continue;
- tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
+ tmp = intel_de_read(dev_priv, MIPI_CTRL(dev_priv, port));
if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
continue;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 665247a2e834..3d9d9281882a 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -93,7 +93,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
- if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
+ if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(dev_priv, port),
mask, 100))
drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
}
@@ -148,20 +148,20 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
header = packet.header;
if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
- data_reg = MIPI_LP_GEN_DATA(port);
+ data_reg = MIPI_LP_GEN_DATA(dev_priv, port);
data_mask = LP_DATA_FIFO_FULL;
- ctrl_reg = MIPI_LP_GEN_CTRL(port);
+ ctrl_reg = MIPI_LP_GEN_CTRL(dev_priv, port);
ctrl_mask = LP_CTRL_FIFO_FULL;
} else {
- data_reg = MIPI_HS_GEN_DATA(port);
+ data_reg = MIPI_HS_GEN_DATA(dev_priv, port);
data_mask = HS_DATA_FIFO_FULL;
- ctrl_reg = MIPI_HS_GEN_CTRL(port);
+ ctrl_reg = MIPI_HS_GEN_CTRL(dev_priv, port);
ctrl_mask = HS_CTRL_FIFO_FULL;
}
/* note: this is never true for reads */
if (packet.payload_length) {
- if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(dev_priv, port),
data_mask, 50))
drm_err(&dev_priv->drm,
"Timeout waiting for HS/LP DATA FIFO !full\n");
@@ -171,11 +171,11 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
}
if (msg->rx_len) {
- intel_de_write(dev_priv, MIPI_INTR_STAT(port),
+ intel_de_write(dev_priv, MIPI_INTR_STAT(dev_priv, port),
GEN_READ_DATA_AVAIL);
}
- if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(dev_priv, port),
ctrl_mask, 50)) {
drm_err(&dev_priv->drm,
"Timeout waiting for HS/LP CTRL FIFO !full\n");
@@ -187,7 +187,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* ->rx_len is set only for reads */
if (msg->rx_len) {
data_mask = GEN_READ_DATA_AVAIL;
- if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
+ if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(dev_priv, port),
data_mask, 50))
drm_err(&dev_priv->drm,
"Timeout waiting for read data.\n");
@@ -237,17 +237,17 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
cmd |= DPI_LP_MODE;
/* clear bit */
- intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
+ intel_de_write(dev_priv, MIPI_INTR_STAT(dev_priv, port), SPL_PKT_SENT_INTERRUPT);
/* XXX: old code skips write if control unchanged */
- if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
+ if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(dev_priv, port)))
drm_dbg_kms(&dev_priv->drm,
"Same special packet %02x twice in a row.\n", cmd);
- intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
+ intel_de_write(dev_priv, MIPI_DPI_CONTROL(dev_priv, port), cmd);
mask = SPL_PKT_SENT_INTERRUPT;
- if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
+ if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(dev_priv, port), mask, 100))
drm_err(&dev_priv->drm,
"Video mode command 0x%08x send failed.\n", cmd);
@@ -338,21 +338,21 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
* Power ON MIPI IO first and then write into IO reset and LP wake bits
*/
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port), 0, GLK_MIPIIO_ENABLE);
/* Put the IO into reset */
- intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
/* Program LP Wake */
for_each_dsi_port(port, intel_dsi->ports) {
- u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
- intel_de_rmw(dev_priv, MIPI_CTRL(port),
+ u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port));
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
}
/* Wait for Pwr ACK */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_MIPIIO_PORT_POWERED, 20))
drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
}
@@ -360,7 +360,7 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
/* Check for cold boot scenario */
for_each_dsi_port(port, intel_dsi->ports) {
cold_boot |=
- !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
+ !(intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port)) & DEVICE_READY);
}
return cold_boot;
@@ -374,46 +374,46 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_PHY_STATUS_PORT_READY, 20))
drm_err(&dev_priv->drm, "PHY is not ON\n");
}
/* Get IO out of reset */
- intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
/* Get IO out of Low power state*/
for_each_dsi_port(port, intel_dsi->ports) {
- if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
- intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
+ if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port)) & DEVICE_READY)) {
+ intel_de_rmw(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_MASK, DEVICE_READY);
usleep_range(10, 15);
} else {
/* Enter ULPS */
- intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_rmw(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
/* Wait for ULPS active */
- if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_ULPS_NOT_ACTIVE, 20))
drm_err(&dev_priv->drm, "ULPS not active\n");
/* Exit ULPS */
- intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_rmw(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
/* Enter Normal Mode */
- intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_rmw(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_MASK,
ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
- intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port), GLK_LP_WAKE, 0);
}
}
/* Wait for Stop state */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_DATA_LANE_STOP_STATE, 20))
drm_err(&dev_priv->drm,
"Date lane not in STOP state\n");
@@ -445,12 +445,12 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
/* Clear ULPS and set device ready */
for_each_dsi_port(port, intel_dsi->ports) {
- val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
+ val = intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port));
val &= ~ULPS_STATE_MASK;
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port), val);
usleep_range(2000, 2500);
val |= DEVICE_READY;
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port), val);
}
}
@@ -473,7 +473,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_ENTER);
usleep_range(2500, 3000);
@@ -484,11 +484,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_EXIT);
usleep_range(2500, 3000);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
DEVICE_READY);
usleep_range(2500, 3000);
}
@@ -514,19 +514,19 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
/* Enter ULPS */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_rmw(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_PHY_STATUS_PORT_READY, 20))
drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
}
/* Wait for Pwr ACK bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_MIPIIO_PORT_POWERED, 20))
drm_err(&dev_priv->drm,
"MIPI IO Port is not powergated\n");
@@ -540,18 +540,18 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
enum port port;
/* Put the IO into reset */
- intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(dev_priv, port),
GLK_PHY_STATUS_PORT_READY, 20))
drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
}
/* Clear MIPI mode */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port), GLK_MIPIIO_ENABLE, 0);
}
static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
@@ -578,15 +578,15 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
DEVICE_READY | ULPS_STATE_ENTER);
usleep_range(2000, 2500);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
DEVICE_READY | ULPS_STATE_EXIT);
usleep_range(2000, 2500);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port),
DEVICE_READY | ULPS_STATE_ENTER);
usleep_range(2000, 2500);
@@ -603,7 +603,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
usleep_range(1000, 1500);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port), 0x00);
usleep_range(2000, 2500);
}
}
@@ -621,7 +621,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, MIPI_CTRL(port),
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port),
BXT_PIXEL_OVERLAP_CNT_MASK,
temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
} else {
@@ -798,7 +798,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
if (is_cmd_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports)
intel_de_write(dev_priv,
- MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
+ MIPI_MAX_RETURN_PKT_SIZE(dev_priv, port), 8 * 4);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
} else {
@@ -973,18 +973,18 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
/* Try command mode if video mode not enabled */
if (!enabled) {
u32 tmp = intel_de_read(dev_priv,
- MIPI_DSI_FUNC_PRG(port));
+ MIPI_DSI_FUNC_PRG(dev_priv, port));
enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
}
if (!enabled)
continue;
- if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
+ if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port)) & DEVICE_READY))
continue;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
+ u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(dev_priv, port));
tmp &= BXT_PIPE_SELECT_MASK;
tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -1036,7 +1036,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
break;
}
- fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
+ fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(dev_priv, port)) & VID_MODE_FORMAT_MASK;
bpp = mipi_dsi_pixel_format_to_bpp(
pixel_format_from_register_bits(fmt));
@@ -1058,14 +1058,14 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
BXT_MIPI_TRANS_VTOTAL(port));
hactive = adjusted_mode->crtc_hdisplay;
- hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
+ hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(dev_priv, port));
/*
* Meaningful for video mode non-burst sync pulse mode only,
* can be zero for non-burst sync events and burst modes
*/
- hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
- hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
+ hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(dev_priv, port));
+ hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(dev_priv, port));
/* harizontal values are in terms of high speed byte clock */
hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
@@ -1082,8 +1082,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
}
/* vertical values are in terms of lines */
- vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
- vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
+ vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(dev_priv, port));
+ vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(dev_priv, port));
adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
@@ -1263,21 +1263,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
adjusted_mode->crtc_vtotal);
}
- intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
+ intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(dev_priv, port),
hactive);
- intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
+ intel_de_write(dev_priv, MIPI_HFP_COUNT(dev_priv, port), hfp);
/* meaningful for video mode non-burst sync pulse mode only,
* can be zero for non-burst sync events and burst modes */
- intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
+ intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(dev_priv, port),
hsync);
- intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
+ intel_de_write(dev_priv, MIPI_HBP_COUNT(dev_priv, port), hbp);
/* vertical values are in terms of lines */
- intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
- intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
+ intel_de_write(dev_priv, MIPI_VFP_COUNT(dev_priv, port), vfp);
+ intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(dev_priv, port),
vsync);
- intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
+ intel_de_write(dev_priv, MIPI_VBP_COUNT(dev_priv, port), vbp);
}
}
@@ -1328,31 +1328,31 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
* escape clock divider, 20MHz, shared for A and C.
* device ready must be off when doing this! txclkesc?
*/
- tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
+ tmp = intel_de_read(dev_priv, MIPI_CTRL(dev_priv, PORT_A));
tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
- intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
+ intel_de_write(dev_priv, MIPI_CTRL(dev_priv, PORT_A),
tmp | ESCAPE_CLOCK_DIVIDER_1);
/* read request priority is per pipe */
- tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
+ tmp = intel_de_read(dev_priv, MIPI_CTRL(dev_priv, port));
tmp &= ~READ_REQUEST_PRIORITY_MASK;
- intel_de_write(dev_priv, MIPI_CTRL(port),
+ intel_de_write(dev_priv, MIPI_CTRL(dev_priv, port),
tmp | READ_REQUEST_PRIORITY_HIGH);
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
enum pipe pipe = crtc->pipe;
- intel_de_rmw(dev_priv, MIPI_CTRL(port),
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port),
BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
}
/* XXX: why here, why like this? handling in irq handler?! */
- intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
- intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
+ intel_de_write(dev_priv, MIPI_INTR_STAT(dev_priv, port), 0xffffffff);
+ intel_de_write(dev_priv, MIPI_INTR_EN(dev_priv, port), 0xffffffff);
- intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
+ intel_de_write(dev_priv, MIPI_DPHY_PARAM(dev_priv, port),
intel_dsi->dphy_reg);
- intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
+ intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(dev_priv, port),
adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
}
@@ -1380,7 +1380,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
}
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
+ intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(dev_priv, port), val);
/* timeouts for recovery. one frame IIUC. if counter expires,
* EOT and stop state. */
@@ -1401,23 +1401,23 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
if (is_vid_mode(intel_dsi) &&
intel_dsi->video_mode == BURST_MODE) {
- intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
+ intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(dev_priv, port),
txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
} else {
- intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
+ intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(dev_priv, port),
txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
}
- intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
+ intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(dev_priv, port),
intel_dsi->lp_rx_timeout);
- intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
+ intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(dev_priv, port),
intel_dsi->turn_arnd_val);
- intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
+ intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(dev_priv, port),
intel_dsi->rst_timer_val);
/* dphy stuff */
/* in terms of low power clock */
- intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
+ intel_de_write(dev_priv, MIPI_INIT_COUNT(dev_priv, port),
txclkesc(intel_dsi->escape_clk_div, 100));
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
@@ -1429,15 +1429,15 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
* if not in dual link mode.
*/
intel_de_write(dev_priv,
- MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
+ MIPI_INIT_COUNT(dev_priv, port == PORT_A ? PORT_C : PORT_A),
intel_dsi->init_count);
}
/* recovery disables */
- intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
+ intel_de_write(dev_priv, MIPI_EOT_DISABLE(dev_priv, port), tmp);
/* in terms of low power clock */
- intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
+ intel_de_write(dev_priv, MIPI_INIT_COUNT(dev_priv, port),
intel_dsi->init_count);
/* in terms of txbyteclkhs. actual high to low switch +
@@ -1445,7 +1445,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
*
* XXX: write MIPI_STOP_STATE_STALL?
*/
- intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
+ intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(dev_priv, port),
intel_dsi->hs_to_lp_count);
/* XXX: low power clock equivalence in terms of byte clock.
@@ -1454,14 +1454,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
* txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
* ) / 105.???
*/
- intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
+ intel_de_write(dev_priv, MIPI_LP_BYTECLK(dev_priv, port),
intel_dsi->lp_byte_clk);
if (IS_GEMINILAKE(dev_priv)) {
- intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
+ intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(dev_priv, port),
intel_dsi->lp_byte_clk);
/* Shadow of DPHY reg */
- intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
+ intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(dev_priv, port),
intel_dsi->dphy_reg);
}
@@ -1470,10 +1470,10 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
* this register in terms of byte clocks. based on dsi transfer
* rate and the number of lanes configured the time taken to
* transmit 16 long packets in a dsi stream varies. */
- intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
+ intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(dev_priv, port),
intel_dsi->bw_timer);
- intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
+ intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(dev_priv, port),
intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
if (is_vid_mode(intel_dsi)) {
@@ -1501,7 +1501,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
break;
}
- intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
+ intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(dev_priv, port), fmt);
}
}
}
@@ -1517,17 +1517,17 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
/* Panel commands can be sent when clock is in LP11 */
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port), 0x0);
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
else
vlv_dsi_reset_clocks(encoder, port);
- intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
+ intel_de_write(dev_priv, MIPI_EOT_DISABLE(dev_priv, port), CLOCKSTOP);
- intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
+ intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(dev_priv, port), VID_MODE_FORMAT_MASK, 0);
- intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
+ intel_de_write(dev_priv, MIPI_DEVICE_READY(dev_priv, port), 0x1);
}
}
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index ae0a0b11bae3..858ac5de4572 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -369,9 +369,9 @@ void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- temp = intel_de_read(dev_priv, MIPI_CTRL(port));
+ temp = intel_de_read(dev_priv, MIPI_CTRL(dev_priv, port));
temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
- intel_de_write(dev_priv, MIPI_CTRL(port),
+ intel_de_write(dev_priv, MIPI_CTRL(dev_priv, port),
temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);
}
@@ -587,7 +587,7 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);
}
- intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
+ intel_de_write(dev_priv, MIPI_EOT_DISABLE(dev_priv, port), CLOCKSTOP);
}
static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index 12a608a73720..a8e7036fcf45 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -14,23 +14,20 @@
#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
-#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
+#define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c))
/* BXT MIPI mode configure */
-#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
-#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
-#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
- _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
+#define _BXT_MIPIA_TRANS_HACTIVE 0xb0f8
+#define _BXT_MIPIC_TRANS_HACTIVE 0xb8f8
+#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
-#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
-#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
-#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
- _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
+#define _BXT_MIPIA_TRANS_VACTIVE 0xb0fc
+#define _BXT_MIPIC_TRANS_VACTIVE 0xb8fc
+#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
-#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
-#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
-#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
- _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
+#define _BXT_MIPIA_TRANS_VTOTAL 0xb100
+#define _BXT_MIPIC_TRANS_VTOTAL 0xb900
+#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
#define STAP_SELECT (1 << 0)
@@ -38,14 +35,14 @@
#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
#define HS_IO_CTRL_SELECT (1 << 0)
-#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
-#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
-#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
+#define _MIPIA_PORT_CTRL 0x61190
+#define _MIPIC_PORT_CTRL 0x61700
+#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
/* BXT port control */
-#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
-#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
-#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
+#define _BXT_MIPIA_PORT_CTRL 0xb0c0
+#define _BXT_MIPIC_PORT_CTRL 0xb8c0
+#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
#define DPI_ENABLE (1 << 31) /* A + C */
#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
@@ -87,17 +84,17 @@
#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
-#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
-#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
-#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
+#define _MIPIA_TEARING_CTRL 0x61194
+#define _MIPIC_TEARING_CTRL 0x61704
+#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
#define TEARING_EFFECT_DELAY_SHIFT 0
#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
-#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800)
-#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
+#define _MIPIA_DEVICE_READY 0xb000
+#define _MIPIC_DEVICE_READY 0xb800
+#define MIPI_DEVICE_READY(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
#define ULPS_STATE_ENTER (2 << 1)
@@ -105,12 +102,12 @@
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
-#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
-#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
-#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
-#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
+#define _MIPIA_INTR_STAT 0xb004
+#define _MIPIC_INTR_STAT 0xb804
+#define MIPI_INTR_STAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
+#define _MIPIA_INTR_EN 0xb008
+#define _MIPIC_INTR_EN 0xb808
+#define MIPI_INTR_EN(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
#define TEARING_EFFECT (1 << 31)
#define SPL_PKT_SENT_INTERRUPT (1 << 30)
#define GEN_READ_DATA_AVAIL (1 << 29)
@@ -144,9 +141,9 @@
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c)
-#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
+#define _MIPIA_DSI_FUNC_PRG 0xb00c
+#define _MIPIC_DSI_FUNC_PRG 0xb80c
+#define MIPI_DSI_FUNC_PRG(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED (0 << 13)
#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
@@ -167,77 +164,77 @@
#define DATA_LANES_PRG_REG_SHIFT 0
#define DATA_LANES_PRG_REG_MASK (7 << 0)
-#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010)
-#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810)
-#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
+#define _MIPIA_HS_TX_TIMEOUT 0xb010
+#define _MIPIC_HS_TX_TIMEOUT 0xb810
+#define MIPI_HS_TX_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014)
-#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814)
-#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
+#define _MIPIA_LP_RX_TIMEOUT 0xb014
+#define _MIPIC_LP_RX_TIMEOUT 0xb814
+#define MIPI_LP_RX_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018)
-#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818)
-#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
+#define _MIPIA_TURN_AROUND_TIMEOUT 0xb018
+#define _MIPIC_TURN_AROUND_TIMEOUT 0xb818
+#define MIPI_TURN_AROUND_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
#define TURN_AROUND_TIMEOUT_MASK 0x3f
-#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c)
-#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c)
-#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
+#define _MIPIA_DEVICE_RESET_TIMER 0xb01c
+#define _MIPIC_DEVICE_RESET_TIMER 0xb81c
+#define MIPI_DEVICE_RESET_TIMER(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
#define DEVICE_RESET_TIMER_MASK 0xffff
-#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020)
-#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820)
-#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
+#define _MIPIA_DPI_RESOLUTION 0xb020
+#define _MIPIC_DPI_RESOLUTION 0xb820
+#define MIPI_DPI_RESOLUTION(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
#define VERTICAL_ADDRESS_SHIFT 16
#define VERTICAL_ADDRESS_MASK (0xffff << 16)
#define HORIZONTAL_ADDRESS_SHIFT 0
#define HORIZONTAL_ADDRESS_MASK 0xffff
-#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024)
-#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824)
-#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
+#define _MIPIA_DBI_FIFO_THROTTLE 0xb024
+#define _MIPIC_DBI_FIFO_THROTTLE 0xb824
+#define MIPI_DBI_FIFO_THROTTLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
#define DBI_FIFO_EMPTY_HALF (0 << 0)
#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
/* regs below are bits 15:0 */
-#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028)
-#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828)
-#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
+#define _MIPIA_HSYNC_PADDING_COUNT 0xb028
+#define _MIPIC_HSYNC_PADDING_COUNT 0xb828
+#define MIPI_HSYNC_PADDING_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c)
-#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c)
-#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
+#define _MIPIA_HBP_COUNT 0xb02c
+#define _MIPIC_HBP_COUNT 0xb82c
+#define MIPI_HBP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030)
-#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830)
-#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
+#define _MIPIA_HFP_COUNT 0xb030
+#define _MIPIC_HFP_COUNT 0xb830
+#define MIPI_HFP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034)
-#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834)
-#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
+#define _MIPIA_HACTIVE_AREA_COUNT 0xb034
+#define _MIPIC_HACTIVE_AREA_COUNT 0xb834
+#define MIPI_HACTIVE_AREA_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038)
-#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838)
-#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
+#define _MIPIA_VSYNC_PADDING_COUNT 0xb038
+#define _MIPIC_VSYNC_PADDING_COUNT 0xb838
+#define MIPI_VSYNC_PADDING_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c)
-#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c)
-#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
+#define _MIPIA_VBP_COUNT 0xb03c
+#define _MIPIC_VBP_COUNT 0xb83c
+#define MIPI_VBP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040)
-#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840)
-#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
+#define _MIPIA_VFP_COUNT 0xb040
+#define _MIPIC_VFP_COUNT 0xb840
+#define MIPI_VFP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044)
-#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844)
-#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT 0xb044
+#define _MIPIC_HIGH_LOW_SWITCH_COUNT 0xb844
+#define MIPI_HIGH_LOW_SWITCH_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
-#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048)
-#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848)
-#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
+#define _MIPIA_DPI_CONTROL 0xb048
+#define _MIPIC_DPI_CONTROL 0xb848
+#define MIPI_DPI_CONTROL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
#define DPI_LP_MODE (1 << 6)
#define BACKLIGHT_OFF (1 << 5)
#define BACKLIGHT_ON (1 << 4)
@@ -246,28 +243,27 @@
#define TURN_ON (1 << 1)
#define SHUTDOWN (1 << 0)
-#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c)
-#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c)
-#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
+#define _MIPIA_DPI_DATA 0xb04c
+#define _MIPIC_DPI_DATA 0xb84c
+#define MIPI_DPI_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
#define COMMAND_BYTE_SHIFT 0
#define COMMAND_BYTE_MASK (0x3f << 0)
-#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050)
-#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850)
-#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
+#define _MIPIA_INIT_COUNT 0xb050
+#define _MIPIC_INIT_COUNT 0xb850
+#define MIPI_INIT_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
#define MASTER_INIT_TIMER_SHIFT 0
#define MASTER_INIT_TIMER_MASK (0xffff << 0)
-#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054)
-#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854)
-#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
- _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
+#define _MIPIA_MAX_RETURN_PKT_SIZE 0xb054
+#define _MIPIC_MAX_RETURN_PKT_SIZE 0xb854
+#define MIPI_MAX_RETURN_PKT_SIZE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
#define MAX_RETURN_PKT_SIZE_SHIFT 0
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
-#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058)
-#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858)
-#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
+#define _MIPIA_VIDEO_MODE_FORMAT 0xb058
+#define _MIPIC_VIDEO_MODE_FORMAT 0xb858
+#define MIPI_VIDEO_MODE_FORMAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
#define DISABLE_VIDEO_BTA (1 << 3)
#define IP_TG_CONFIG (1 << 2)
@@ -275,9 +271,9 @@
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
#define VIDEO_MODE_BURST (3 << 0)
-#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c)
-#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c)
-#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
+#define _MIPIA_EOT_DISABLE 0xb05c
+#define _MIPIC_EOT_DISABLE 0xb85c
+#define MIPI_EOT_DISABLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
#define BXT_DPHY_DEFEATURE_EN (1 << 8)
#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
@@ -289,36 +285,36 @@
#define CLOCKSTOP (1 << 1)
#define EOT_DISABLE (1 << 0)
-#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060)
-#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860)
-#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
+#define _MIPIA_LP_BYTECLK 0xb060
+#define _MIPIC_LP_BYTECLK 0xb860
+#define MIPI_LP_BYTECLK(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
-#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4)
-#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4)
-#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+#define _MIPIA_TLPX_TIME_COUNT 0xb0a4
+#define _MIPIC_TLPX_TIME_COUNT 0xb8a4
+#define MIPI_TLPX_TIME_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098)
-#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898)
-#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+#define _MIPIA_CLK_LANE_TIMING 0xb098
+#define _MIPIC_CLK_LANE_TIMING 0xb898
+#define MIPI_CLK_LANE_TIMING(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
/* bits 31:0 */
-#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064)
-#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864)
-#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
+#define _MIPIA_LP_GEN_DATA 0xb064
+#define _MIPIC_LP_GEN_DATA 0xb864
+#define MIPI_LP_GEN_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
/* bits 31:0 */
-#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068)
-#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868)
-#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-
-#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c)
-#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c)
-#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070)
-#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870)
-#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
+#define _MIPIA_HS_GEN_DATA 0xb068
+#define _MIPIC_HS_GEN_DATA 0xb868
+#define MIPI_HS_GEN_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
+
+#define _MIPIA_LP_GEN_CTRL 0xb06c
+#define _MIPIC_LP_GEN_CTRL 0xb86c
+#define MIPI_LP_GEN_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
+#define _MIPIA_HS_GEN_CTRL 0xb070
+#define _MIPIC_HS_GEN_CTRL 0xb870
+#define MIPI_HS_GEN_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
#define LONG_PACKET_WORD_COUNT_SHIFT 8
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
#define SHORT_PACKET_PARAM_SHIFT 8
@@ -329,9 +325,9 @@
#define DATA_TYPE_MASK (0x3f << 0)
/* data type values, see include/video/mipi_display.h */
-#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074)
-#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874)
-#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
+#define _MIPIA_GEN_FIFO_STAT 0xb074
+#define _MIPIC_GEN_FIFO_STAT 0xb874
+#define MIPI_GEN_FIFO_STAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
#define DPI_FIFO_EMPTY (1 << 28)
#define DBI_FIFO_EMPTY (1 << 27)
#define LP_CTRL_FIFO_EMPTY (1 << 26)
@@ -347,16 +343,16 @@
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
#define HS_DATA_FIFO_FULL (1 << 0)
-#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078)
-#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878)
-#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
+#define _MIPIA_HS_LS_DBI_ENABLE 0xb078
+#define _MIPIC_HS_LS_DBI_ENABLE 0xb878
+#define MIPI_HS_LP_DBI_ENABLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
#define DBI_HS_LP_MODE_MASK (1 << 0)
#define DBI_LP_MODE (1 << 0)
#define DBI_HS_MODE (0 << 0)
-#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080)
-#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880)
-#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
+#define _MIPIA_DPHY_PARAM 0xb080
+#define _MIPIC_DPHY_PARAM 0xb880
+#define MIPI_DPHY_PARAM(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
#define EXIT_ZERO_COUNT_SHIFT 24
#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
#define TRAIL_COUNT_SHIFT 16
@@ -366,34 +362,34 @@
#define PREPARE_COUNT_SHIFT 0
#define PREPARE_COUNT_MASK (0x3f << 0)
-#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084)
-#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884)
-#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
+#define _MIPIA_DBI_BW_CTRL 0xb084
+#define _MIPIC_DBI_BW_CTRL 0xb884
+#define MIPI_DBI_BW_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888)
-#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT 0xb088
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT 0xb888
+#define MIPI_CLK_LANE_SWITCH_TIME_CNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
#define LP_HS_SSW_CNT_SHIFT 16
#define LP_HS_SSW_CNT_MASK (0xffff << 16)
#define HS_LP_PWR_SW_CNT_SHIFT 0
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
-#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c)
-#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c)
-#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
+#define _MIPIA_STOP_STATE_STALL 0xb08c
+#define _MIPIC_STOP_STATE_STALL 0xb88c
+#define MIPI_STOP_STATE_STALL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
#define STOP_STATE_STALL_COUNTER_SHIFT 0
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
-#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090)
-#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890)
-#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094)
-#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894)
-#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
+#define _MIPIA_INTR_STAT_REG_1 0xb090
+#define _MIPIC_INTR_STAT_REG_1 0xb890
+#define MIPI_INTR_STAT_REG_1(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
+#define _MIPIA_INTR_EN_REG_1 0xb094
+#define _MIPIC_INTR_EN_REG_1 0xb894
+#define MIPI_INTR_EN_REG_1(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
#define RX_CONTENTION_DETECTED (1 << 0)
/* XXX: only pipe A ?!? */
-#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100)
+#define MIPIA_DBI_TYPEC_CTRL(i915) (_MIPI_MMIO_BASE(i915) + 0xb100)
#define DBI_TYPEC_ENABLE (1 << 31)
#define DBI_TYPEC_WIP (1 << 30)
#define DBI_TYPEC_OPTION_SHIFT 28
@@ -406,9 +402,9 @@
/* MIPI adapter registers */
-#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104)
-#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904)
-#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
+#define _MIPIA_CTRL 0xb104
+#define _MIPIC_CTRL 0xb904
+#define MIPI_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CTRL, _MIPIC_CTRL)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
@@ -439,41 +435,41 @@
#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
#define GLK_MIPIIO_ENABLE (1 << 0)
-#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108)
-#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908)
-#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
+#define _MIPIA_DATA_ADDRESS 0xb108
+#define _MIPIC_DATA_ADDRESS 0xb908
+#define MIPI_DATA_ADDRESS(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
#define DATA_MEM_ADDRESS_SHIFT 5
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define DATA_VALID (1 << 0)
-#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c)
-#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c)
-#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
+#define _MIPIA_DATA_LENGTH 0xb10c
+#define _MIPIC_DATA_LENGTH 0xb90c
+#define MIPI_DATA_LENGTH(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
#define DATA_LENGTH_SHIFT 0
#define DATA_LENGTH_MASK (0xfffff << 0)
-#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110)
-#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910)
-#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
+#define _MIPIA_COMMAND_ADDRESS 0xb110
+#define _MIPIC_COMMAND_ADDRESS 0xb910
+#define MIPI_COMMAND_ADDRESS(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
#define COMMAND_MEM_ADDRESS_SHIFT 5
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define AUTO_PWG_ENABLE (1 << 2)
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
#define COMMAND_VALID (1 << 0)
-#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114)
-#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914)
-#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
+#define _MIPIA_COMMAND_LENGTH 0xb114
+#define _MIPIC_COMMAND_LENGTH 0xb914
+#define MIPI_COMMAND_LENGTH(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
-#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118)
-#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918)
-#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
+#define _MIPIA_READ_DATA_RETURN0 0xb118
+#define _MIPIC_READ_DATA_RETURN0 0xb918
+#define MIPI_READ_DATA_RETURN(i915, port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138)
-#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938)
-#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
+#define _MIPIA_READ_DATA_VALID 0xb138
+#define _MIPIC_READ_DATA_VALID 0xb938
+#define MIPI_READ_DATA_VALID(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
#endif /* __VLV_DSI_REGS_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
` (2 preceding siblings ...)
2024-04-10 16:36 ` [PATCH 3/3] drm/i915/dsi: pass i915 to register macros instead of implicit variable Jani Nikula
@ 2024-04-10 18:48 ` Patchwork
2024-04-10 18:53 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-11 5:28 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2024-04-10 18:48 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: stop relying on implicit dev_priv variable
URL : https://patchwork.freedesktop.org/series/132285/
State : warning
== Summary ==
Error: dim checkpatch failed
02b70fe522db drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
1b83a12b11bd drm/i915/dsi: add VLV_ prefix to VLV only register macros
-:60: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:92:
+#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
total: 0 errors, 1 warnings, 0 checks, 40 lines checked
277cd13e43bc drm/i915/dsi: pass i915 to register macros instead of implicit variable
-:127: WARNING:LINE_SPACING: Missing a blank line after declarations
#127: FILE: drivers/gpu/drm/i915/display/vlv_dsi.c:349:
+ u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port));
+ intel_de_rmw(dev_priv, MIPI_CTRL(dev_priv, port),
-:143: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#143: FILE: drivers/gpu/drm/i915/display/vlv_dsi.c:363:
+ !(intel_de_read(dev_priv, MIPI_DEVICE_READY(dev_priv, port)) & DEVICE_READY);
-:636: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#636: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:22:
+#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
-:644: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#644: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:26:
+#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
-:652: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#652: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:30:
+#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
-:665: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#665: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:40:
+#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
-:673: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#673: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:45:
+#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
-:686: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#686: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:89:
+#define VLV_MIPI_TEARING_CTRL(port) _MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
-:697: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#697: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:97:
+#define MIPI_DEVICE_READY(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
-:713: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#713: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:107:
+#define MIPI_INTR_STAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-:716: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#716: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:110:
+#define MIPI_INTR_EN(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
-:729: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#729: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:146:
+#define MIPI_DSI_FUNC_PRG(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
-:742: WARNING:LONG_LINE: line length of 131 exceeds 100 columns
#742: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:169:
+#define MIPI_HS_TX_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
-:750: WARNING:LONG_LINE: line length of 131 exceeds 100 columns
#750: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:174:
+#define MIPI_LP_RX_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
-:758: WARNING:LONG_LINE: line length of 143 exceeds 100 columns
#758: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:179:
+#define MIPI_TURN_AROUND_TIMEOUT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
-:766: WARNING:LONG_LINE: line length of 141 exceeds 100 columns
#766: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:184:
+#define MIPI_DEVICE_RESET_TIMER(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
-:774: WARNING:LONG_LINE: line length of 133 exceeds 100 columns
#774: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:189:
+#define MIPI_DPI_RESOLUTION(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
-:785: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#785: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:197:
+#define MIPI_DBI_FIFO_THROTTLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
-:796: WARNING:LONG_LINE: line length of 143 exceeds 100 columns
#796: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:205:
+#define MIPI_HSYNC_PADDING_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-:803: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#803: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:209:
+#define MIPI_HBP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-:810: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#810: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:213:
+#define MIPI_HFP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-:817: WARNING:LONG_LINE: line length of 141 exceeds 100 columns
#817: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:217:
+#define MIPI_HACTIVE_AREA_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-:824: WARNING:LONG_LINE: line length of 143 exceeds 100 columns
#824: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:221:
+#define MIPI_VSYNC_PADDING_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-:831: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#831: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:225:
+#define MIPI_VBP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-:838: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#838: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:229:
+#define MIPI_VFP_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-:845: WARNING:LONG_LINE: line length of 147 exceeds 100 columns
#845: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:233:
+#define MIPI_HIGH_LOW_SWITCH_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
-:852: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#852: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:237:
+#define MIPI_DPI_CONTROL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
-:865: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#865: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:248:
+#define MIPI_DPI_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
-:874: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#874: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:254:
+#define MIPI_INIT_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
-:884: WARNING:LONG_LINE: line length of 143 exceeds 100 columns
#884: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:260:
+#define MIPI_MAX_RETURN_PKT_SIZE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
-:893: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#893: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:266:
+#define MIPI_VIDEO_MODE_FORMAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
-:906: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#906: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:276:
+#define MIPI_EOT_DISABLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
-:919: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#919: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:290:
+#define MIPI_LP_BYTECLK(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
-:928: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#928: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:296:
+#define MIPI_TLPX_TIME_COUNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-:935: WARNING:LONG_LINE: line length of 135 exceeds 100 columns
#935: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:300:
+#define MIPI_CLK_LANE_TIMING(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
-:943: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#943: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:305:
+#define MIPI_LP_GEN_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
-:958: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#958: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:310:
+#define MIPI_HS_GEN_DATA(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-:962: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#962: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:314:
+#define MIPI_LP_GEN_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-:965: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#965: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:317:
+#define MIPI_HS_GEN_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
-:978: WARNING:LONG_LINE: line length of 131 exceeds 100 columns
#978: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:330:
+#define MIPI_GEN_FIFO_STAT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
-:991: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#991: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:348:
+#define MIPI_HS_LP_DBI_ENABLE(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
-:1001: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#1001: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:355:
+#define MIPI_DPHY_PARAM(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
-:1014: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#1014: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:367:
+#define MIPI_DBI_BW_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-:1021: WARNING:LONG_LINE: line length of 161 exceeds 100 columns
#1021: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:371:
+#define MIPI_CLK_LANE_SWITCH_TIME_CNT(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
-:1032: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#1032: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:379:
+#define MIPI_STOP_STATE_STALL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
-:1044: WARNING:LONG_LINE: line length of 135 exceeds 100 columns
#1044: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:385:
+#define MIPI_INTR_STAT_REG_1(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-:1047: WARNING:LONG_LINE: line length of 131 exceeds 100 columns
#1047: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:388:
+#define MIPI_INTR_EN_REG_1(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
-:1065: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#1065: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:407:
+#define MIPI_CTRL(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_CTRL, _MIPIC_CTRL)
-:1078: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#1078: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:440:
+#define MIPI_DATA_ADDRESS(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
-:1088: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#1088: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:447:
+#define MIPI_DATA_LENGTH(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
-:1097: WARNING:LONG_LINE: line length of 135 exceeds 100 columns
#1097: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:453:
+#define MIPI_COMMAND_ADDRESS(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
-:1109: WARNING:LONG_LINE: line length of 133 exceeds 100 columns
#1109: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:462:
+#define MIPI_COMMAND_LENGTH(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
-:1118: WARNING:LONG_LINE: line length of 143 exceeds 100 columns
#1118: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:468:
+#define MIPI_READ_DATA_RETURN(i915, port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-:1125: WARNING:LONG_LINE: line length of 135 exceeds 100 columns
#1125: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:472:
+#define MIPI_READ_DATA_VALID(i915, port) _MMIO_MIPI(_MIPI_MMIO_BASE(i915), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
total: 0 errors, 54 warnings, 0 checks, 1051 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsi: stop relying on implicit dev_priv variable
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
` (3 preceding siblings ...)
2024-04-10 18:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable Patchwork
@ 2024-04-10 18:53 ` Patchwork
2024-04-11 5:28 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2024-04-10 18:53 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3067 bytes --]
== Series Details ==
Series: drm/i915/dsi: stop relying on implicit dev_priv variable
URL : https://patchwork.freedesktop.org/series/132285/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14559 -> Patchwork_132285v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/index.html
Participating hosts (39 -> 36)
------------------------------
Missing (3): fi-kbl-7567u fi-snb-2520m fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_132285v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [PASS][1] -> [FAIL][2] ([i915#10378])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][3] ([i915#10436]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gtt:
- bat-arls-2: [ABORT][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/bat-arls-2/igt@i915_selftest@live@gtt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/bat-arls-2/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@uncore:
- bat-dg2-14: [ABORT][7] ([i915#10366]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/bat-dg2-14/igt@i915_selftest@live@uncore.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/bat-dg2-14/igt@i915_selftest@live@uncore.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10436]: https://gitlab.freedesktop.org/drm/intel/issues/10436
Build changes
-------------
* Linux: CI_DRM_14559 -> Patchwork_132285v1
CI-20190529: 20190529
CI_DRM_14559: 3658e2ec471a1d67baa30a554583bcdd4be55857 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7804: 7804
Patchwork_132285v1: 3658e2ec471a1d67baa30a554583bcdd4be55857 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a456ef6d0d79 drm/i915/dsi: pass i915 to register macros instead of implicit variable
9024f5184152 drm/i915/dsi: add VLV_ prefix to VLV only register macros
bcea19177b09 drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/index.html
[-- Attachment #2: Type: text/html, Size: 3777 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/dsi: stop relying on implicit dev_priv variable
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
` (4 preceding siblings ...)
2024-04-10 18:53 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-04-11 5:28 ` Patchwork
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2024-04-11 5:28 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 96665 bytes --]
== Series Details ==
Series: drm/i915/dsi: stop relying on implicit dev_priv variable
URL : https://patchwork.freedesktop.org/series/132285/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14559_full -> Patchwork_132285v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_132285v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_132285v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_132285v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0:
- shard-dg1: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
* igt@i915_selftest@live@active:
- shard-glk: NOTRUN -> [DMESG-FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk2/igt@i915_selftest@live@active.html
* igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a4:
- shard-dg1: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-15/igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a4.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-17/igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a4.html
* igt@kms_flip@plain-flip-fb-recreate@d-hdmi-a1:
- shard-dg2: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_flip@plain-flip-fb-recreate@d-hdmi-a1.html
* igt@testdisplay:
- shard-snb: [PASS][6] -> [ABORT][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb1/igt@testdisplay.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb1/igt@testdisplay.html
Known issues
------------
Here are the changes found in Patchwork_132285v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8411])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#8411])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#7701])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#7701])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@device_reset@unbind-cold-reset-rebind.html
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: NOTRUN -> [INCOMPLETE][12] ([i915#9408] / [i915#9618])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#8414]) +6 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@drm_fdinfo@busy-hang@bcs0.html
* igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#8414]) +13 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@drm_fdinfo@busy-hang@rcs0.html
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: NOTRUN -> [FAIL][15] ([i915#7742])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#8414]) +15 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html
* igt@gem_busy@semaphore:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#3936])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_busy@semaphore.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9323])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#9323]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#9323])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#6335])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@hang:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#8555])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#8555]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#8555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][26] -> [FAIL][27] ([i915#5784])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-16/igt@gem_eio@reset-stress.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#4036])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-rkl: NOTRUN -> [SKIP][29] ([i915#4525]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@sliced:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812]) +2 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-glk: NOTRUN -> [SKIP][31] ([i915#6334])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk1/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@capture@vecs0-lmem0:
- shard-dg1: NOTRUN -> [FAIL][32] ([i915#10386]) +1 other test fail
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@gem_exec_capture@capture@vecs0-lmem0.html
* igt@gem_exec_capture@capture@vecs0-smem:
- shard-mtlp: NOTRUN -> [FAIL][33] ([i915#10386])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@gem_exec_capture@capture@vecs0-smem.html
* igt@gem_exec_capture@many-4k-zero:
- shard-glk: NOTRUN -> [FAIL][34] ([i915#9606])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk2/igt@gem_exec_capture@many-4k-zero.html
- shard-rkl: NOTRUN -> [FAIL][35] ([i915#9606])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#3539] / [i915#4852]) +2 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4473] / [i915#4771])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][38] ([i915#2842]) +2 other tests fail
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-rkl: NOTRUN -> [FAIL][39] ([i915#2842]) +3 other tests fail
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [PASS][40] -> [FAIL][41] ([i915#2842])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-3/igt@gem_exec_fair@basic-none@vecs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fence@concurrent:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4812])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3539] / [i915#4852]) +3 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-rkl: NOTRUN -> [SKIP][44] ([i915#3281]) +13 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-softpin:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#3281]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#3281]) +6 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_reloc@basic-write-wc:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#3281]) +7 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_exec_reloc@basic-write-wc.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#4812]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][49] ([i915#7975] / [i915#8213])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4860])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4860])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#4860])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_swapping@basic@lmem0:
- shard-dg2: [PASS][53] -> [FAIL][54] ([i915#10378]) +1 other test fail
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-5/igt@gem_lmem_swapping@basic@lmem0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-7/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4613]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg2: NOTRUN -> [FAIL][56] ([i915#10378])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][57] ([i915#10378])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#4613])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#4613]) +5 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][60] ([i915#4613]) +9 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk2/igt@gem_lmem_swapping@random-engines.html
* igt@gem_madvise@dontneed-before-exec:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#3282]) +6 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_madvise@dontneed-before-exec.html
* igt@gem_media_fill@media-fill:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#8289])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_media_fill@media-fill.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#284])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@gem_media_vme.html
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#284])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_media_vme.html
* igt@gem_mmap@short-mmap:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#4083]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_mmap@short-mmap.html
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#4083]) +4 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@gem_mmap@short-mmap.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#4077]) +13 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@read-write:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#4083]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_mmap_wc@read-write.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3282]) +4 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][70] ([i915#2658])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk7/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][71] ([i915#3282]) +6 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_pread@snoop.html
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#3282]) +6 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_pread@snoop.html
* igt@gem_pxp@create-regular-context-2:
- shard-dg1: NOTRUN -> [SKIP][73] ([i915#4270]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#4270]) +4 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#4270])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][76] ([i915#4270]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#4270]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-glk: NOTRUN -> [SKIP][78] +640 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk2/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#8428]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#5190] / [i915#8428]) +8 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_tiled_pread_basic:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4079]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#3297]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#3297]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3297])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#3297] / [i915#4880])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#3297])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gen7_exec_parse@basic-allocation:
- shard-mtlp: NOTRUN -> [SKIP][87] +15 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@batch-without-end:
- shard-mtlp: NOTRUN -> [SKIP][88] ([i915#2856])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu: NOTRUN -> [SKIP][89] ([i915#2527] / [i915#2856])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-oversize:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#2527]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#2527]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@gen9_exec_parse@secure-batches.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#2856]) +4 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#6227])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@i915_module_load@load.html
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#6227])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: NOTRUN -> [INCOMPLETE][95] ([i915#9849])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk4/igt@i915_module_load@reload-with-fault-injection.html
- shard-rkl: [PASS][96] -> [ABORT][97] ([i915#9820])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][98] -> [INCOMPLETE][99] ([i915#9849])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [PASS][100] -> [ABORT][101] ([i915#10131] / [i915#9820])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6412])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#6590])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@i915_pm_freq_mult@media-freq@gt0.html
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#6590])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][105] -> [FAIL][106] ([i915#3591])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][107] -> [INCOMPLETE][108] ([i915#7790])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb1/igt@i915_pm_rps@reset.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb1/igt@i915_pm_rps@reset.html
- shard-mtlp: NOTRUN -> [FAIL][109] ([i915#8346])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@i915_pm_rps@reset.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: NOTRUN -> [SKIP][110] ([i915#4387])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@i915_pm_sseu@full-enable.html
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#4387])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@test-query-geometry-subslices:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#5723])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][113] ([i915#9311])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@i915_selftest@mock@memory_region.html
- shard-dg1: NOTRUN -> [DMESG-WARN][114] ([i915#9311])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][115] -> [INCOMPLETE][116] ([i915#4817])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#4077]) +5 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#7707])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-mtlp: NOTRUN -> [SKIP][119] ([i915#4212]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#5190])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#4212]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#4212]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#8709]) +7 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#8709]) +11 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#9531])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][126] ([i915#1769])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#1769] / [i915#3555]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#5286])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#5286]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#4538] / [i915#5286]) +4 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][131] +23 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][132] ([i915#3638])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#3638]) +4 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [FAIL][134] ([i915#3743])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: [PASS][135] -> [FAIL][136] ([i915#3743]) +1 other test fail
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-tglu-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#4538] / [i915#5190]) +13 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#4538]) +2 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@basic:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#10656])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_big_joiner@basic.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#6095]) +31 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-b-edp-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#10278])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#10278]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][144] ([i915#6095]) +15 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#6095]) +77 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#6095]) +51 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-13/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#10307] / [i915#6095]) +136 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#10278])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#10278])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#3742])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#4087]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][152] +22 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
- shard-tglu: NOTRUN -> [SKIP][153] ([i915#7828]) +2 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#7828]) +9 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#7828]) +7 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#7828]) +8 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#7828]) +5 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#7118] / [i915#9424])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#3299])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-mtlp: NOTRUN -> [SKIP][160] ([i915#3299])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-1:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#6944] / [i915#9424])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_content_protection@lic-type-1.html
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#9424])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#9424])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_content_protection@mei-interface.html
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#9433])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@type1:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#7118] / [i915#9424])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_content_protection@type1.html
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#7116] / [i915#9424])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#3359]) +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#3359])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#8814])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#3555]) +7 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#3555]) +3 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#3359]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#3555] / [i915#8814]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3359]) +1 other test skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#9809]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#4103] / [i915#4213])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#4103] / [i915#4213]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#4103]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
- shard-tglu: NOTRUN -> [SKIP][180] ([i915#4103])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#9723])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#9723])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#8588])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_display_modes@mst-extended-mode-negative.html
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#8588])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#1257])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-basic:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#3555] / [i915#3840] / [i915#9159])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#3840])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3840])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#3840])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#3555] / [i915#3840])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#3840]) +1 other test skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats.html
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#3840])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3955])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#3469])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#9337])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#3637]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-tglu: NOTRUN -> [SKIP][197] ([i915#3637])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][198] +44 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#9934]) +3 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#8381])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_flip@flip-vs-fences.html
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#8381])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#2587] / [i915#2672]) +2 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#2672]) +2 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#2672]) +2 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#8810])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#2672]) +5 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#2587] / [i915#2672]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#2672] / [i915#3555])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#1825]) +23 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-snb: [PASS][210] -> [SKIP][211] +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#5354]) +41 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][213] +49 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#1825]) +44 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][215] ([i915#5439])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-dg1: NOTRUN -> [SKIP][216] ([i915#3458]) +13 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][217] ([i915#8708]) +17 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][218] ([i915#10070])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#3458]) +17 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][220] ([i915#8708]) +9 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][221] ([i915#8708]) +17 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][222] ([i915#3023]) +26 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#3555] / [i915#8228])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#3555] / [i915#8228]) +5 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-4/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#4816])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#1839])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#6301])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][228] ([i915#10647]) +3 other tests fail
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk4/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#3555] / [i915#8821])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#3555]) +6 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#9423]) +15 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][232] ([i915#5176]) +1 other test skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][233] ([i915#5176] / [i915#9423]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][234] ([i915#9423]) +3 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][235] ([i915#5235]) +2 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][236] ([i915#5235]) +5 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#3555] / [i915#5235])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#5235] / [i915#9423]) +11 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][239] ([i915#5235]) +3 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#5235]) +7 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-rkl: NOTRUN -> [SKIP][241] ([i915#5354])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_pm_backlight@fade-with-suspend.html
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#9812])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#9685])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-dpms-negative:
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#9293])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_pm_dc@dc5-dpms-negative.html
* igt@kms_pm_dc@dc5-psr:
- shard-rkl: NOTRUN -> [SKIP][245] ([i915#9685]) +1 other test skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][246] ([i915#3361])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][247] ([i915#9340])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#9340])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][249] -> [SKIP][250] ([i915#9519]) +1 other test skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#9519]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#9519])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#9519])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][254] -> [SKIP][255] ([i915#9519]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-11/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@pm-caching:
- shard-dg1: NOTRUN -> [SKIP][256] ([i915#4077]) +9 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_pm_rpm@pm-caching.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#6524])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_prime@d3hot:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#6524] / [i915#6805])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_prime@d3hot.html
- shard-dg1: NOTRUN -> [SKIP][259] ([i915#6524])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][260] ([i915#9808]) +1 other test skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf@psr2-pipe-a-edp-1.html
* igt@kms_psr2_su@page_flip-p010:
- shard-dg1: NOTRUN -> [SKIP][261] ([i915#9683])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#9683]) +1 other test skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-cursor-blt:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#9688]) +8 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_psr@fbc-pr-cursor-blt.html
* igt@kms_psr@fbc-psr-basic:
- shard-dg2: NOTRUN -> [SKIP][264] ([i915#1072] / [i915#9732]) +24 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][265] ([i915#9732]) +4 other tests skip
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][266] ([i915#1072] / [i915#9732]) +22 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][267] ([i915#1072] / [i915#9732]) +19 other tests skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_psr@psr2-sprite-mmap-cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg1: NOTRUN -> [SKIP][268] ([i915#9685]) +1 other test skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: NOTRUN -> [SKIP][269] ([i915#4235]) +1 other test skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][270] ([i915#5289])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-dg2: NOTRUN -> [SKIP][271] ([i915#5190]) +2 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][272] ([i915#4235] / [i915#5190]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-tglu: NOTRUN -> [SKIP][273] ([i915#3555])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-mtlp: NOTRUN -> [SKIP][274] ([i915#3555] / [i915#8809])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#8623])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-mtlp: NOTRUN -> [SKIP][276] ([i915#8623])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][277] -> [FAIL][278] ([i915#9196])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2:
- shard-rkl: [PASS][279] -> [FAIL][280] ([i915#9196])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-1/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-1/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2.html
* igt@kms_vrr@flip-suspend:
- shard-mtlp: NOTRUN -> [SKIP][281] ([i915#3555] / [i915#8808])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg1: NOTRUN -> [SKIP][282] ([i915#9906])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@kms_vrr@seamless-rr-switch-vrr.html
- shard-mtlp: NOTRUN -> [SKIP][283] ([i915#8808] / [i915#9906])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-glk: NOTRUN -> [SKIP][284] ([i915#2437])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-rkl: NOTRUN -> [SKIP][285] ([i915#2437] / [i915#9412])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-dg1: NOTRUN -> [SKIP][286] ([i915#2437] / [i915#9412])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglu: NOTRUN -> [SKIP][287] ([i915#2437])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_writeback@writeback-invalid-parameters.html
- shard-rkl: NOTRUN -> [SKIP][288] ([i915#2437])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][289] ([i915#2436] / [i915#7387])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][290] ([i915#2434])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@perf@mi-rpc.html
- shard-mtlp: NOTRUN -> [SKIP][291] ([i915#2434] / [i915#7387])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-dg1: NOTRUN -> [SKIP][292] ([i915#2433])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg2: NOTRUN -> [SKIP][293] ([i915#8850])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][294] ([i915#10537] / [i915#5793])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@perf_pmu@module-unload.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][295] ([i915#3291] / [i915#3708])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@prime_vgem@basic-fence-read.html
- shard-dg1: NOTRUN -> [SKIP][296] ([i915#3708])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][297] ([i915#3708] / [i915#4077])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- shard-rkl: NOTRUN -> [SKIP][298] ([i915#3291] / [i915#3708]) +1 other test skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-6/igt@prime_vgem@basic-write.html
- shard-mtlp: NOTRUN -> [SKIP][299] ([i915#10216] / [i915#3708])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-7/igt@prime_vgem@basic-write.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-tglu: NOTRUN -> [SKIP][300] ([i915#9917])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-mtlp: NOTRUN -> [SKIP][301] ([i915#9917])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-dg1: NOTRUN -> [SKIP][302] ([i915#9917])
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-rkl: NOTRUN -> [SKIP][303] ([i915#9917])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-glk: NOTRUN -> [FAIL][304] ([i915#9781])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk8/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-glk: NOTRUN -> [FAIL][305] ([i915#9779])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-glk4/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2: NOTRUN -> [SKIP][306] ([i915#4818])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@tools_test@sysfs_l3_parity.html
- shard-dg1: NOTRUN -> [SKIP][307] ([i915#4818])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_mmap@mmap-bo:
- shard-mtlp: NOTRUN -> [SKIP][308] ([i915#2575]) +7 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@v3d/v3d_mmap@mmap-bo.html
* igt@v3d/v3d_perfmon@get-values-invalid-pad:
- shard-tglu: NOTRUN -> [SKIP][309] ([i915#2575]) +4 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@v3d/v3d_perfmon@get-values-invalid-pad.html
* igt@v3d/v3d_submit_csd@single-out-sync:
- shard-dg2: NOTRUN -> [SKIP][310] ([i915#2575]) +14 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-3/igt@v3d/v3d_submit_csd@single-out-sync.html
* igt@v3d/v3d_submit_csd@valid-multisync-submission:
- shard-dg1: NOTRUN -> [SKIP][311] ([i915#2575]) +12 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@v3d/v3d_submit_csd@valid-multisync-submission.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg1: NOTRUN -> [SKIP][312] ([i915#7711]) +6 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-18/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_purgeable_bo@mark-purgeable-twice:
- shard-mtlp: NOTRUN -> [SKIP][313] ([i915#7711]) +5 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-5/igt@vc4/vc4_purgeable_bo@mark-purgeable-twice.html
* igt@vc4/vc4_tiling@set-get:
- shard-rkl: NOTRUN -> [SKIP][314] ([i915#7711]) +8 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-3/igt@vc4/vc4_tiling@set-get.html
* igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
- shard-dg2: NOTRUN -> [SKIP][315] ([i915#7711]) +6 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-6/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [FAIL][316] ([i915#2842]) -> [PASS][317] +1 other test pass
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-3/igt@gem_exec_fair@basic-none@bcs0.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_parallel@fds@vcs1:
- shard-mtlp: [ABORT][318] -> [PASS][319]
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-mtlp-7/igt@gem_exec_parallel@fds@vcs1.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-mtlp-1/igt@gem_exec_parallel@fds@vcs1.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-dg2: [INCOMPLETE][320] ([i915#9275]) -> [PASS][321]
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-10/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg2: [FAIL][322] ([i915#10378]) -> [PASS][323]
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-7/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][324] ([i915#3591]) -> [PASS][325]
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: [FAIL][326] ([i915#3743]) -> [PASS][327] +1 other test pass
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-tglu-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][328] ([i915#2122]) -> [PASS][329] +2 other tests pass
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb7/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb5/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-dg2: [FAIL][330] ([i915#6880]) -> [PASS][331]
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
- shard-dg2: [INCOMPLETE][332] -> [PASS][333]
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][334] ([i915#9519]) -> [PASS][335] +1 other test pass
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
- shard-rkl: [SKIP][336] ([i915#9519]) -> [PASS][337]
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_setmode@basic@pipe-b-hdmi-a-3:
- shard-dg2: [FAIL][338] ([i915#5465]) -> [PASS][339] +1 other test pass
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-6/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-5/igt@kms_setmode@basic@pipe-b-hdmi-a-3.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [FAIL][340] ([i915#9196]) -> [PASS][341] +1 other test pass
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@perf@blocking@0-rcs0:
- shard-dg1: [FAIL][342] ([i915#10538]) -> [PASS][343]
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-15/igt@perf@blocking@0-rcs0.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-17/igt@perf@blocking@0-rcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][344] ([i915#2842]) -> [FAIL][345] ([i915#2876])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-tglu-5/igt@gem_exec_fair@basic-pace@rcs0.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-tglu-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [INCOMPLETE][346] ([i915#9849]) -> [INCOMPLETE][347] ([i915#9820] / [i915#9849])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_content_protection@content-type-change:
- shard-snb: [INCOMPLETE][348] ([i915#8816]) -> [SKIP][349]
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-snb7/igt@kms_content_protection@content-type-change.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-snb5/igt@kms_content_protection@content-type-change.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-dg2: [SKIP][350] ([i915#3458]) -> [SKIP][351] ([i915#10433] / [i915#3458])
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][352] ([i915#4816]) -> [SKIP][353] ([i915#4070] / [i915#4816])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@fbc-psr-sprite-plane-move:
- shard-dg2: [SKIP][354] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][355] ([i915#1072] / [i915#9732]) +13 other tests skip
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-11/igt@kms_psr@fbc-psr-sprite-plane-move.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@kms_psr@fbc-psr-sprite-plane-move.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][356] ([i915#9100]) -> [FAIL][357] ([i915#7484])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14559/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
[i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
[i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10386]: https://gitlab.freedesktop.org/drm/intel/issues/10386
[i915#10433]: https://gitlab.freedesktop.org/drm/intel/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#10537]: https://gitlab.freedesktop.org/drm/intel/issues/10537
[i915#10538]: https://gitlab.freedesktop.org/drm/intel/issues/10538
[i915#10647]: https://gitlab.freedesktop.org/drm/intel/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/intel/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8346]: https://gitlab.freedesktop.org/drm/intel/issues/8346
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8816]: https://gitlab.freedesktop.org/drm/intel/issues/8816
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
[i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
[i915#9408]: https://gitlab.freedesktop.org/drm/intel/issues/9408
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9618]: https://gitlab.freedesktop.org/drm/intel/issues/9618
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
[i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14559 -> Patchwork_132285v1
CI-20190529: 20190529
CI_DRM_14559: 3658e2ec471a1d67baa30a554583bcdd4be55857 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7804: 7804
Patchwork_132285v1: 3658e2ec471a1d67baa30a554583bcdd4be55857 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v1/index.html
[-- Attachment #2: Type: text/html, Size: 118148 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-04-11 5:28 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-04-10 16:36 [PATCH 0/3] drm/i915/dsi: stop relying on implicit dev_priv variable Jani Nikula
2024-04-10 16:36 ` [PATCH 1/3] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition Jani Nikula
2024-04-10 16:36 ` [PATCH 2/3] drm/i915/dsi: add VLV_ prefix to VLV only register macros Jani Nikula
2024-04-10 16:36 ` [PATCH 3/3] drm/i915/dsi: pass i915 to register macros instead of implicit variable Jani Nikula
2024-04-10 18:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable Patchwork
2024-04-10 18:53 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-11 5:28 ` ✗ Fi.CI.IGT: failure " Patchwork
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