From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAAEBC2B9F4 for ; Wed, 23 Jun 2021 01:05:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE4FE6113E for ; Wed, 23 Jun 2021 01:05:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbhFWBHQ (ORCPT ); Tue, 22 Jun 2021 21:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbhFWBHP (ORCPT ); Tue, 22 Jun 2021 21:07:15 -0400 Received: from angie.orcam.me.uk (angie.orcam.me.uk [IPv6:2001:4190:8020::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 055E0C061574 for ; Tue, 22 Jun 2021 18:04:58 -0700 (PDT) Received: by angie.orcam.me.uk (Postfix, from userid 500) id 93C6B92009C; Wed, 23 Jun 2021 03:04:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 8C2E492009B; Wed, 23 Jun 2021 03:04:56 +0200 (CEST) Date: Wed, 23 Jun 2021 03:04:56 +0200 (CEST) From: "Maciej W. Rozycki" To: Arnd Bergmann cc: Nikolai Zhubr , Thomas Gleixner , Heiner Kallweit , netdev , the arch/x86 maintainers , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: Re: Realtek 8139 problem on 486. In-Reply-To: Message-ID: References: <60B24AC2.9050505@gmail.com> <60B41D00.8050801@gmail.com> <60B514A0.1020701@gmail.com> <60B560A8.8000800@gmail.com> <49f40dd8-da68-f579-b359-7a7e229565e1@gmail.com> <60B611C6.2000801@gmail.com> <60B65BBB.2040507@gmail.com> <877dipgyrb.ffs@nanos.tec.linutronix.de> <60D1DAC1.9060200@gmail.com> <60D22F1D.1000205@gmail.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, 22 Jun 2021, Arnd Bergmann wrote: > > This fix looks really nice. Maybe it is right thing to do. > > I'll leave that up to Thomas and Maciej to decide, they should have the > best idea of why the x86 pci-irq code looks the way it does today and > what the possible risk with my patch is. Ah, so this is the SiS 85C496/497 chipset; another one that does not have its southbridge visible in the PCI configuration space, perhaps because it doesn't put the southbridge on PCI in the first place, and instead it maps its configuration registers in the upper half of the northbridge's space. Oh, the joys of early attempts! It does PCI interrupt steering, it has the ELCR, but we don't have a PIRQ router implemented for it. I have a datasheet, so this should be fairly trivial to do, and hopefully things will then work automagically, no need for hacks. It's very late tonight here, so let me come back with something tomorrow. Maciej