* [PATCH 0/5] Enable fastset for mbus_join state change
@ 2024-03-22 11:40 Stanislav Lisovskiy
2024-03-22 11:40 ` [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
` (7 more replies)
0 siblings, 8 replies; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
Currently fastset is not supported, if mbus join state changes,
so whenever we have to switch mbus state, we have to force a full
modeset. This patch series makes fastset possible from MBUS state
point of view.
Stanislav Lisovskiy (5):
drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
drm/i915: Break intel_dbuf_mbus_update into 2 separate parts
drm/i915: Use old mbus_join value when increasing CDCLK
drm/i915: Loop over all active pipes in intel_mbus_dbox_update
drm/i915: Implement vblank synchronized MBUS join changes
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 155 ++++++++++++++-----
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +
4 files changed, 134 insertions(+), 41 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
@ 2024-03-22 11:40 ` Stanislav Lisovskiy
2024-03-22 17:46 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts Stanislav Lisovskiy
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
According to BSpec we need to do correspondent MBUS updates before
or after DBUF reallocation, depending on whether we are enabling
or disabling mbus joining(typical scenario is swithing between
multiple and single displays).
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index bc341abcab2fe..8ff69da664807 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3574,7 +3574,7 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl;
@@ -3632,7 +3632,9 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus)
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3653,6 +3655,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus)
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-03-22 11:40 ` [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
@ 2024-03-22 11:40 ` Stanislav Lisovskiy
2024-03-22 17:50 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK Stanislav Lisovskiy
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
We need to be able to update dbuf min tracker and mdclk ratio
separately if mbus_join state didn't change, so lets add one
degree of freedom and make it possible.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 55 ++++++++++++--------
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8ff69da664807..2b947870527fc 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3570,16 +3570,38 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
}
+static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+
+ if (DISPLAY_VER(i915) >= 20 &&
+ old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
+ /*
+ * For Xe2LPD and beyond, when there is a change in the ratio
+ * between MDCLK and CDCLK, updates to related registers need to
+ * happen at a specific point in the CDCLK change sequence. In
+ * that case, we defer to the call to
+ * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
+ */
+ return;
+ }
+
+ intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
+ new_dbuf_state->joined_mbus);
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl;
- const struct intel_dbuf_state *old_dbuf_state =
- intel_atomic_get_old_dbuf_state(state);
const struct intel_dbuf_state *new_dbuf_state =
intel_atomic_get_new_dbuf_state(state);
@@ -3600,21 +3622,6 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
-
- if (DISPLAY_VER(i915) >= 20 &&
- old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
- /*
- * For Xe2LPD and beyond, when there is a change in the ratio
- * between MDCLK and CDCLK, updates to related registers need to
- * happen at a specific point in the CDCLK change sequence. In
- * that case, we defer to the call to
- * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
- */
- return;
- }
-
- intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
- new_dbuf_state->joined_mbus);
}
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
@@ -3632,8 +3639,10 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus)
- intel_dbuf_mbus_update(state);
+ if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
+ intel_dbuf_mbus_join_update(state);
+ intel_dbuf_mdclk_min_tracker_update(state);
+ }
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
@@ -3655,8 +3664,10 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus)
- intel_dbuf_mbus_update(state);
+ if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
+ intel_dbuf_mbus_join_update(state);
+ intel_dbuf_mdclk_min_tracker_update(state);
+ }
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-03-22 11:40 ` [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
2024-03-22 11:40 ` [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts Stanislav Lisovskiy
@ 2024-03-22 11:40 ` Stanislav Lisovskiy
2024-03-22 17:45 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Stanislav Lisovskiy
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
In order to make sure we are not breaking the proper sequence
lets to updates step by step and don't change MBUS join value
during MDCLK/CDCLK programming stage.
MBUS join programming would be taken care by pre/post ddb hooks.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 31aaa9780dfcf..43a9616c78260 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2611,9 +2611,19 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
if (pipe == INVALID_PIPE ||
old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
+ struct intel_cdclk_config cdclk_config;
+
drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
- intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
+ /*
+ * By this hack we want to prevent mbus_join to be programmed
+ * beforehand - we will take care of this later in pre ddb
+ * programming hook.
+ */
+ cdclk_config = new_cdclk_state->actual;
+ cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
+
+ intel_set_cdclk(i915, &cdclk_config, pipe);
}
}
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (2 preceding siblings ...)
2024-03-22 11:40 ` [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK Stanislav Lisovskiy
@ 2024-03-22 11:40 ` Stanislav Lisovskiy
2024-03-22 17:51 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
` (3 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
We need to loop through all active pipes, not just the ones, that
are in current state, because disabling and enabling even a particular
pipe affects credits in another one.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2b947870527fc..7eb78e0c8c8e3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3696,10 +3696,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
- const struct intel_crtc_state *new_crtc_state;
const struct intel_crtc *crtc;
u32 val = 0;
- int i;
if (DISPLAY_VER(i915) < 11)
return;
@@ -3743,12 +3741,9 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
val |= MBUS_DBOX_B_CREDIT(8);
}
- for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
u32 pipe_val = val;
- if (!new_crtc_state->hw.active)
- continue;
-
if (DISPLAY_VER(i915) >= 14) {
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
new_dbuf_state->active_pipes))
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (3 preceding siblings ...)
2024-03-22 11:40 ` [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Stanislav Lisovskiy
@ 2024-03-22 11:40 ` Stanislav Lisovskiy
2024-03-22 18:06 ` Ville Syrjälä
2024-03-25 9:09 ` [PATCH 3/3] " Stanislav Lisovskiy
2024-03-22 12:28 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change (rev2) Patchwork
` (2 subsequent siblings)
7 siblings, 2 replies; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-22 11:40 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
Currently we can't change MBUS join status without doing a modeset,
because we are lacking mechanism to synchronize those with vblank.
However then this means that we can't do a fastset, if there is a need
to change MBUS join state. Fix that by implementing such change.
We already call correspondent check and update at pre_plane dbuf update,
so the only thing left is to have a non-modeset version of that.
If active pipes stay the same then fastset is possible and only MBUS
join state/ddb allocation updates would be committed.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 108 +++++++++++++++----
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +
3 files changed, 94 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b88f214e111ae..d5351f6fa2eb4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6895,6 +6895,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
intel_pre_update_crtc(state, crtc);
}
+ intel_dbuf_mbus_pre_ddb_update(state);
+
while (update_pipes) {
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -6925,6 +6927,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
}
}
+ intel_dbuf_mbus_post_ddb_update(state);
+
update_pipes = modeset_pipes;
/*
@@ -7169,9 +7173,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
intel_encoders_update_prepare(state);
-
intel_dbuf_pre_plane_update(state);
- intel_mbus_dbox_update(state);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7eb78e0c8c8e3..eee13b57d4830 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_blend.h>
+#include <drm/drm_print.h>
#include "i915_drv.h"
#include "i915_fixed.h"
@@ -2636,13 +2637,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
if (ret)
return ret;
- if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
- /* TODO: Implement vblank synchronized MBUS joining changes */
- ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
- if (ret)
- return ret;
- }
-
drm_dbg_kms(&i915->drm,
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
@@ -3594,30 +3588,57 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
new_dbuf_state->joined_mbus);
}
+static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
+ const struct intel_dbuf_state *dbuf_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ enum pipe sync_pipe = ffs(dbuf_state->active_pipes) - 1;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+
+ drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
+ drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
+
+ crtc = intel_crtc_for_pipe(i915, sync_pipe);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
+ return sync_pipe;
+ else
+ return INVALID_PIPE;
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_ctl_update(struct intel_atomic_state *state,
+ enum pipe sync_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl;
const struct intel_dbuf_state *new_dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ u32 pipe_select;
if (!HAS_MBUS_JOINING(i915))
return;
+ if (sync_pipe != INVALID_PIPE)
+ pipe_select = MBUS_JOIN_PIPE_SELECT(sync_pipe);
+ else
+ pipe_select = MBUS_JOIN_PIPE_SELECT_NONE;
+
/*
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
*/
if (new_dbuf_state->joined_mbus)
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
- MBUS_JOIN_PIPE_SELECT_NONE;
+ pipe_select;
else
mbus_ctl = MBUS_HASHING_MODE_2x2 |
- MBUS_JOIN_PIPE_SELECT_NONE;
+ pipe_select;
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
@@ -3632,6 +3653,42 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
+ return;
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ gen9_dbuf_slices_update(i915,
+ old_dbuf_state->enabled_slices |
+ new_dbuf_state->enabled_slices);
+}
+
+void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
+ return;
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ gen9_dbuf_slices_update(i915,
+ new_dbuf_state->enabled_slices);
+}
+
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
+{
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
@@ -3640,16 +3697,15 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
- intel_dbuf_mbus_join_update(state);
+ enum pipe sync_pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
+
+ intel_dbuf_mbus_ctl_update(state, sync_pipe);
+ intel_mbus_dbox_update(state);
intel_dbuf_mdclk_min_tracker_update(state);
}
-
- gen9_dbuf_slices_update(i915,
- old_dbuf_state->enabled_slices |
- new_dbuf_state->enabled_slices);
}
-void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_dbuf_state *new_dbuf_state =
@@ -3657,6 +3713,12 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state && old_dbuf_state &&
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus) {
+ intel_dbuf_mdclk_min_tracker_update(state);
+ intel_mbus_dbox_update(state);
+ }
+
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
@@ -3665,12 +3727,18 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
- intel_dbuf_mbus_join_update(state);
+ enum pipe sync_pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
+
intel_dbuf_mdclk_min_tracker_update(state);
- }
+ intel_mbus_dbox_update(state);
+ intel_dbuf_mbus_ctl_update(state, sync_pipe);
- gen9_dbuf_slices_update(i915,
- new_dbuf_state->enabled_slices);
+ if (sync_pipe != INVALID_PIPE) {
+ struct intel_crtc *crtc = intel_crtc_for_pipe(i915, sync_pipe);
+
+ intel_crtc_wait_for_next_vblank(crtc);
+ }
+ }
}
static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 3a90741cab06a..f6d38b41e3a6c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -77,6 +77,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
void intel_mbus_dbox_update(struct intel_atomic_state *state);
#endif /* __SKL_WATERMARK_H__ */
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change (rev2)
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (4 preceding siblings ...)
2024-03-22 11:40 ` [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
@ 2024-03-22 12:28 ` Patchwork
2024-03-22 12:41 ` ✓ Fi.CI.BAT: success " Patchwork
2024-03-23 8:31 ` ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-22 12:28 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable fastset for mbus_join state change (rev2)
URL : https://patchwork.freedesktop.org/series/130480/
State : warning
== Summary ==
Error: dim checkpatch failed
9509e256b405 drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
-:9: WARNING:TYPO_SPELLING: 'swithing' may be misspelled - perhaps 'switching'?
#9:
or disabling mbus joining(typical scenario is swithing between
^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 27 lines checked
cd3089203bd3 drm/i915: Break intel_dbuf_mbus_update into 2 separate parts
ea40cb166010 drm/i915: Use old mbus_join value when increasing CDCLK
466a77763a9b drm/i915: Loop over all active pipes in intel_mbus_dbox_update
4b6e068f01cf drm/i915: Implement vblank synchronized MBUS join changes
-:80: ERROR:CODE_INDENT: code indent should use tabs where possible
#80: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3592:
+^I^I^I^I const struct intel_dbuf_state *dbuf_state)$
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3592:
+static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
+ const struct intel_dbuf_state *dbuf_state)
-:140: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices'
#140: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3656:
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
-:159: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices'
#159: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3675:
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
total: 1 errors, 0 warnings, 3 checks, 210 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for Enable fastset for mbus_join state change (rev2)
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (5 preceding siblings ...)
2024-03-22 12:28 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change (rev2) Patchwork
@ 2024-03-22 12:41 ` Patchwork
2024-03-23 8:31 ` ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-22 12:41 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8315 bytes --]
== Series Details ==
Series: Enable fastset for mbus_join state change (rev2)
URL : https://patchwork.freedesktop.org/series/130480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14468 -> Patchwork_130480v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/index.html
Participating hosts (39 -> 37)
------------------------------
Additional (1): bat-kbl-2
Missing (3): bat-mtlp-8 fi-snb-2520m fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_130480v2 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- bat-jsl-1: [FAIL][1] ([i915#8293]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/bat-jsl-1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/boot.html
- fi-apl-guc: [FAIL][3] ([i915#8293]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/fi-apl-guc/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/fi-apl-guc/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][6] ([i915#1849])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-kbl-2/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][9] +39 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-jsl-1: NOTRUN -> [SKIP][11] ([i915#4613]) +3 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@i915_pm_rps@basic-api:
- bat-adlm-1: NOTRUN -> [SKIP][12] ([i915#6621])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@i915_pm_rps@basic-api.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-1: NOTRUN -> [SKIP][13] ([i915#4103]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-1: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#9886])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-edid:
- bat-dg2-8: [PASS][15] -> [INCOMPLETE][16] ([i915#10419])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-dg2-8/igt@kms_force_connector_basic@force-edid.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][17]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][18]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][19] ([i915#1849] / [i915#4342])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][20] +17 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/fi-apl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][21] ([i915#9875] / [i915#9900]) +6 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][22] ([i915#5354])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-adlm-1: NOTRUN -> [SKIP][23] ([i915#9673] / [i915#9732]) +3 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlm-1: NOTRUN -> [SKIP][24] ([i915#3555])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-1: NOTRUN -> [SKIP][25] ([i915#3555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlm-1: NOTRUN -> [SKIP][26] ([i915#3708] / [i915#9900])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- bat-adlm-1: NOTRUN -> [SKIP][27] ([i915#3708]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/bat-adlm-1/igt@prime_vgem@basic-write.html
[i915#10419]: https://gitlab.freedesktop.org/drm/intel/issues/10419
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9875]: https://gitlab.freedesktop.org/drm/intel/issues/9875
[i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886
[i915#9900]: https://gitlab.freedesktop.org/drm/intel/issues/9900
Build changes
-------------
* Linux: CI_DRM_14468 -> Patchwork_130480v2
CI-20190529: 20190529
CI_DRM_14468: a19e6423c2c21b8dc7ad79ca95cc24637b248bd0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7777: 7777
Patchwork_130480v2: a19e6423c2c21b8dc7ad79ca95cc24637b248bd0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
347600d5cd66 drm/i915: Implement vblank synchronized MBUS join changes
6d55b5ea2e00 drm/i915: Loop over all active pipes in intel_mbus_dbox_update
ad0103890024 drm/i915: Use old mbus_join value when increasing CDCLK
0b15b6283492 drm/i915: Break intel_dbuf_mbus_update into 2 separate parts
38bb770b85ea drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/index.html
[-- Attachment #2: Type: text/html, Size: 9999 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK
2024-03-22 11:40 ` [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK Stanislav Lisovskiy
@ 2024-03-22 17:45 ` Ville Syrjälä
2024-03-25 14:44 ` Gustavo Sousa
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-22 17:45 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 01:40:44PM +0200, Stanislav Lisovskiy wrote:
> In order to make sure we are not breaking the proper sequence
> lets to updates step by step and don't change MBUS join value
> during MDCLK/CDCLK programming stage.
> MBUS join programming would be taken care by pre/post ddb hooks.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 31aaa9780dfcf..43a9616c78260 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2611,9 +2611,19 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>
> if (pipe == INVALID_PIPE ||
> old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> + struct intel_cdclk_config cdclk_config;
> +
> drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>
> - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> + /*
> + * By this hack we want to prevent mbus_join to be programmed
> + * beforehand - we will take care of this later in pre ddb
> + * programming hook.
> + */
We're not doing anything to prevent mbus joining to be
programmed here. It will simply not be programmed here,
which is why we need to use the old mbus_join based ratio.
I would also include the actual function name here instead
of "pre ddb programming hook" since that's rather vague.
So this could use a bit of rewording. Otherwise lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + cdclk_config = new_cdclk_state->actual;
> + cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
> +
> + intel_set_cdclk(i915, &cdclk_config, pipe);
> }
> }
>
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
2024-03-22 11:40 ` [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
@ 2024-03-22 17:46 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-22 17:46 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 01:40:42PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec we need to do correspondent MBUS updates before
> or after DBUF reallocation, depending on whether we are enabling
> or disabling mbus joining(typical scenario is swithing between
> multiple and single displays).
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index bc341abcab2fe..8ff69da664807 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3574,7 +3574,7 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
> * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> * update the request state of all DBUS slices.
> */
> -static void update_mbus_pre_enable(struct intel_atomic_state *state)
> +static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> u32 mbus_ctl;
> @@ -3632,7 +3632,9 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>
> WARN_ON(!new_dbuf_state->base.changed);
>
> - update_mbus_pre_enable(state);
> + if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus)
> + intel_dbuf_mbus_update(state);
> +
Does this acutally do something sensible on its own?
If not I'd just squash this into the other patch.
> gen9_dbuf_slices_update(i915,
> old_dbuf_state->enabled_slices |
> new_dbuf_state->enabled_slices);
> @@ -3653,6 +3655,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>
> WARN_ON(!new_dbuf_state->base.changed);
>
> + if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus)
> + intel_dbuf_mbus_update(state);
> +
> gen9_dbuf_slices_update(i915,
> new_dbuf_state->enabled_slices);
> }
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts
2024-03-22 11:40 ` [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts Stanislav Lisovskiy
@ 2024-03-22 17:50 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-22 17:50 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 01:40:43PM +0200, Stanislav Lisovskiy wrote:
> We need to be able to update dbuf min tracker and mdclk ratio
> separately if mbus_join state didn't change, so lets add one
> degree of freedom and make it possible.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 55 ++++++++++++--------
> 1 file changed, 33 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8ff69da664807..2b947870527fc 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3570,16 +3570,38 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio
> DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> }
>
> +static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> +
> + if (DISPLAY_VER(i915) >= 20 &&
> + old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
> + /*
> + * For Xe2LPD and beyond, when there is a change in the ratio
> + * between MDCLK and CDCLK, updates to related registers need to
> + * happen at a specific point in the CDCLK change sequence. In
> + * that case, we defer to the call to
> + * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> + */
> + return;
> + }
That whole condition I think needs to go. We want to update the ratio
also when changing mbus joining. But that behavioural change doesn't
really belong in this patch, so this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
> + new_dbuf_state->joined_mbus);
> +}
> +
> /*
> * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> * update the request state of all DBUS slices.
> */
> -static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> +static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> u32 mbus_ctl;
> - const struct intel_dbuf_state *old_dbuf_state =
> - intel_atomic_get_old_dbuf_state(state);
> const struct intel_dbuf_state *new_dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
>
> @@ -3600,21 +3622,6 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> intel_de_rmw(i915, MBUS_CTL,
> MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
> -
> - if (DISPLAY_VER(i915) >= 20 &&
> - old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) {
> - /*
> - * For Xe2LPD and beyond, when there is a change in the ratio
> - * between MDCLK and CDCLK, updates to related registers need to
> - * happen at a specific point in the CDCLK change sequence. In
> - * that case, we defer to the call to
> - * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic.
> - */
> - return;
> - }
> -
> - intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio,
> - new_dbuf_state->joined_mbus);
> }
>
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> @@ -3632,8 +3639,10 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
>
> WARN_ON(!new_dbuf_state->base.changed);
>
> - if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus)
> - intel_dbuf_mbus_update(state);
> + if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
> + intel_dbuf_mbus_join_update(state);
> + intel_dbuf_mdclk_min_tracker_update(state);
> + }
>
> gen9_dbuf_slices_update(i915,
> old_dbuf_state->enabled_slices |
> @@ -3655,8 +3664,10 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>
> WARN_ON(!new_dbuf_state->base.changed);
>
> - if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus)
> - intel_dbuf_mbus_update(state);
> + if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
> + intel_dbuf_mbus_join_update(state);
> + intel_dbuf_mdclk_min_tracker_update(state);
> + }
>
> gen9_dbuf_slices_update(i915,
> new_dbuf_state->enabled_slices);
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update
2024-03-22 11:40 ` [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Stanislav Lisovskiy
@ 2024-03-22 17:51 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-22 17:51 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 01:40:45PM +0200, Stanislav Lisovskiy wrote:
> We need to loop through all active pipes, not just the ones, that
> are in current state, because disabling and enabling even a particular
> pipe affects credits in another one.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2b947870527fc..7eb78e0c8c8e3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3696,10 +3696,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> - const struct intel_crtc_state *new_crtc_state;
> const struct intel_crtc *crtc;
> u32 val = 0;
> - int i;
>
> if (DISPLAY_VER(i915) < 11)
> return;
> @@ -3743,12 +3741,9 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> val |= MBUS_DBOX_B_CREDIT(8);
> }
>
> - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
> u32 pipe_val = val;
>
> - if (!new_crtc_state->hw.active)
> - continue;
> -
> if (DISPLAY_VER(i915) >= 14) {
> if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> new_dbuf_state->active_pipes))
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-22 11:40 ` [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
@ 2024-03-22 18:06 ` Ville Syrjälä
2024-03-25 8:59 ` Lisovskiy, Stanislav
2024-03-25 9:09 ` [PATCH 3/3] " Stanislav Lisovskiy
1 sibling, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-22 18:06 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 01:40:46PM +0200, Stanislav Lisovskiy wrote:
> Currently we can't change MBUS join status without doing a modeset,
> because we are lacking mechanism to synchronize those with vblank.
> However then this means that we can't do a fastset, if there is a need
> to change MBUS join state. Fix that by implementing such change.
> We already call correspondent check and update at pre_plane dbuf update,
> so the only thing left is to have a non-modeset version of that.
> If active pipes stay the same then fastset is possible and only MBUS
> join state/ddb allocation updates would be committed.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 108 +++++++++++++++----
> drivers/gpu/drm/i915/display/skl_watermark.h | 2 +
> 3 files changed, 94 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b88f214e111ae..d5351f6fa2eb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6895,6 +6895,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> intel_pre_update_crtc(state, crtc);
> }
>
> + intel_dbuf_mbus_pre_ddb_update(state);
> +
> while (update_pipes) {
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> @@ -6925,6 +6927,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> }
> }
>
> + intel_dbuf_mbus_post_ddb_update(state);
> +
> update_pipes = modeset_pipes;
>
> /*
> @@ -7169,9 +7173,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
>
> intel_encoders_update_prepare(state);
> -
> intel_dbuf_pre_plane_update(state);
> - intel_mbus_dbox_update(state);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 7eb78e0c8c8e3..eee13b57d4830 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -4,6 +4,7 @@
> */
>
> #include <drm/drm_blend.h>
> +#include <drm/drm_print.h>
>
> #include "i915_drv.h"
> #include "i915_fixed.h"
> @@ -2636,13 +2637,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> - /* TODO: Implement vblank synchronized MBUS joining changes */
> - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> - if (ret)
> - return ret;
> - }
> -
> drm_dbg_kms(&i915->drm,
> "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> old_dbuf_state->enabled_slices,
> @@ -3594,30 +3588,57 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
> new_dbuf_state->joined_mbus);
> }
>
> +static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
> + const struct intel_dbuf_state *dbuf_state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + enum pipe sync_pipe = ffs(dbuf_state->active_pipes) - 1;
> + struct intel_crtc_state *new_crtc_state;
const
> + struct intel_crtc *crtc;
> +
> + drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
> + drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
> +
> + crtc = intel_crtc_for_pipe(i915, sync_pipe);
> + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
> + return sync_pipe;
> + else
> + return INVALID_PIPE;
> +}
> +
> /*
> * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> * update the request state of all DBUS slices.
> */
> -static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> +static void intel_dbuf_mbus_ctl_update(struct intel_atomic_state *state,
> + enum pipe sync_pipe)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> u32 mbus_ctl;
> const struct intel_dbuf_state *new_dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
> + u32 pipe_select;
>
> if (!HAS_MBUS_JOINING(i915))
> return;
>
> + if (sync_pipe != INVALID_PIPE)
> + pipe_select = MBUS_JOIN_PIPE_SELECT(sync_pipe);
> + else
> + pipe_select = MBUS_JOIN_PIPE_SELECT_NONE;
> +
> /*
> * TODO: Implement vblank synchronized MBUS joining changes.
> * Must be properly coordinated with dbuf reprogramming.
> */
> if (new_dbuf_state->joined_mbus)
> mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> - MBUS_JOIN_PIPE_SELECT_NONE;
> + pipe_select;
> else
> mbus_ctl = MBUS_HASHING_MODE_2x2 |
> - MBUS_JOIN_PIPE_SELECT_NONE;
> + pipe_select;
The 'pipe_select' variable looks completely redundant.
You can just do
if (sync_pipe != INVALID_PIPE)
mbus_ctl |= ...
else
mbus_ctl |= ...
directly here.
>
> intel_de_rmw(i915, MBUS_CTL,
> MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> @@ -3632,6 +3653,42 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> const struct intel_dbuf_state *old_dbuf_state =
> intel_atomic_get_old_dbuf_state(state);
>
> + if (!new_dbuf_state ||
> + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
redundant parens.
> + return;
> +
> + WARN_ON(!new_dbuf_state->base.changed);
> +
> + gen9_dbuf_slices_update(i915,
> + old_dbuf_state->enabled_slices |
> + new_dbuf_state->enabled_slices);
> +}
> +
> +void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> +
> + if (!new_dbuf_state ||
> + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
ditto
> + return;
> +
> + WARN_ON(!new_dbuf_state->base.changed);
> +
> + gen9_dbuf_slices_update(i915,
> + new_dbuf_state->enabled_slices);
> +}
> +
> +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
> +{
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> +
> if (!new_dbuf_state ||
> (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> @@ -3640,16 +3697,15 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> WARN_ON(!new_dbuf_state->base.changed);
>
> if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
> - intel_dbuf_mbus_join_update(state);
> + enum pipe sync_pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
> +
> + intel_dbuf_mbus_ctl_update(state, sync_pipe);
> + intel_mbus_dbox_update(state);
> intel_dbuf_mdclk_min_tracker_update(state);
> }
> -
> - gen9_dbuf_slices_update(i915,
> - old_dbuf_state->enabled_slices |
> - new_dbuf_state->enabled_slices);
> }
>
> -void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_dbuf_state *new_dbuf_state =
> @@ -3657,6 +3713,12 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> const struct intel_dbuf_state *old_dbuf_state =
> intel_atomic_get_old_dbuf_state(state);
>
> + if (new_dbuf_state && old_dbuf_state &&
> + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus) {
> + intel_dbuf_mdclk_min_tracker_update(state);
> + intel_mbus_dbox_update(state);
> + }
I still think should go into one of the new ddb hooks.
I think we want to program these before the new planes
get enabled. So I'd probably stuff this into the post ddb
hook.
> +
> if (!new_dbuf_state ||
> (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> @@ -3665,12 +3727,18 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> WARN_ON(!new_dbuf_state->base.changed);
>
> if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
> - intel_dbuf_mbus_join_update(state);
> + enum pipe sync_pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
> +
> intel_dbuf_mdclk_min_tracker_update(state);
> - }
> + intel_mbus_dbox_update(state);
> + intel_dbuf_mbus_ctl_update(state, sync_pipe);
>
> - gen9_dbuf_slices_update(i915,
> - new_dbuf_state->enabled_slices);
> + if (sync_pipe != INVALID_PIPE) {
> + struct intel_crtc *crtc = intel_crtc_for_pipe(i915, sync_pipe);
> +
> + intel_crtc_wait_for_next_vblank(crtc);
> + }
> + }
> }
>
> static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index 3a90741cab06a..f6d38b41e3a6c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -77,6 +77,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
> +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> void intel_mbus_dbox_update(struct intel_atomic_state *state);
>
> #endif /* __SKL_WATERMARK_H__ */
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for Enable fastset for mbus_join state change (rev2)
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (6 preceding siblings ...)
2024-03-22 12:41 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-03-23 8:31 ` Patchwork
7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-23 8:31 UTC (permalink / raw
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 81785 bytes --]
== Series Details ==
Series: Enable fastset for mbus_join state change (rev2)
URL : https://patchwork.freedesktop.org/series/130480/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14468_full -> Patchwork_130480v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_130480v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_130480v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_130480v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_gttfill@engines@ccs0:
- shard-dg2: NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-3/igt@gem_exec_gttfill@engines@ccs0.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
- shard-snb: [PASS][2] -> [ABORT][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-snb6/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-snb7/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
* igt@runner@aborted:
- shard-glk: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk3/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_130480v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8411])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@drm_fdinfo@isolation@vecs0:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8414]) +21 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@drm_fdinfo@isolation@vecs0.html
* igt@drm_fdinfo@most-busy-check-all@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8414]) +5 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@drm_fdinfo@most-busy-check-all@vcs0.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#3281]) +15 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_busy@semaphore:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#3936])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][11] ([i915#4873])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [PASS][14] -> [FAIL][15] ([i915#9561])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-7/igt@gem_ctx_freq@sysfs@gt0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-2/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#8555])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg1: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][18] -> [FAIL][19] ([i915#5784])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg1-18/igt@gem_eio@reset-stress.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#4771])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-pair:
- shard-mtlp: NOTRUN -> [SKIP][21] ([i915#4771])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#4771])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@hog:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#4812]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_exec_balancer@hog.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-glk: NOTRUN -> [SKIP][24] ([i915#6334])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk8/igt@gem_exec_capture@capture-invisible@smem0.html
- shard-mtlp: NOTRUN -> [SKIP][25] ([i915#6334])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][26] ([i915#2842]) +2 other tests fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-share:
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#4473] / [i915#4771])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_exec_fair@basic-pace-share.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4473])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu: [PASS][29] -> [FAIL][30] ([i915#2842]) +1 other test fail
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][31] -> [FAIL][32] ([i915#2842]) +2 other tests fail
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#3539])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg1: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852]) +4 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#7697])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#3281]) +7 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_exec_reloc@basic-wc-gtt-active:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#3281])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_exec_reloc@basic-wc-gtt-active.html
* igt@gem_exec_reloc@basic-write-gtt:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#3281]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@gem_exec_reloc@basic-write-gtt.html
* igt@gem_exec_schedule@deep@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4537])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_exec_schedule@deep@rcs0.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4812]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][42] ([i915#4860]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: [PASS][43] -> [FAIL][44] ([i915#10378])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg1-16/igt@gem_lmem_swapping@heavy-random@lmem0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-16/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4613]) +4 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [PASS][46] -> [FAIL][47] ([i915#10378])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][48] ([i915#10378])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#4613])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][50] ([i915#4613]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk8/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_fill@media-fill:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#8289])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_media_fill@media-fill.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#4077]) +14 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4077]) +4 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_wc@bad-size:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#4083])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_mmap_wc@bad-size.html
* igt@gem_mmap_wc@set-cache-level:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4083]) +4 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#4083]) +5 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3282]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads.html
- shard-dg1: NOTRUN -> [SKIP][58] ([i915#3282]) +9 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pwrite@basic-self:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#3282]) +4 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_pwrite@basic-self.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4270]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4270]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_readwrite@new-obj:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#3282])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_readwrite@new-obj.html
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#8428]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#5190] / [i915#8428]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#8411])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#4077]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_tiled_pread_basic:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4079]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gem_tiled_pread_basic.html
* igt@gem_unfence_active_buffers:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#4879])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3297])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#3297])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#3297] / [i915#4880])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#3297]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen3_render_tiledy_blits:
- shard-mtlp: NOTRUN -> [SKIP][73] +18 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#2856]) +2 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#2527]) +4 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@gen9_exec_parse@bb-secure.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4881])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@i915_fb_tiling.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu: NOTRUN -> [SKIP][77] ([i915#8399])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#8399])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rps@basic-api:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#6621])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#8925])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@i915_pm_rps@thresholds-park@gt0:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#8925])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@i915_pm_rps@thresholds-park@gt0.html
* igt@i915_query@hwconfig_table:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#6245])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@i915_query@hwconfig_table.html
* igt@i915_query@test-query-geometry-subslices:
- shard-dg1: NOTRUN -> [SKIP][83] ([i915#5723])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@mock@memory_region:
- shard-mtlp: NOTRUN -> [DMESG-WARN][84] ([i915#9311])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@i915_selftest@mock@memory_region.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#7707])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@intel_hwmon@hwmon-read.html
* igt@intel_hwmon@hwmon-write:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#7707])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#4212]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#4212]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#8709]) +11 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#1769] / [i915#3555])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#1769] / [i915#3555])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#5286]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#5286]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#5286])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#4538] / [i915#5286]) +6 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][96] -> [FAIL][97] ([i915#5138])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][98] ([i915#3638])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][99] +7 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][100] ([i915#3638]) +5 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#4538] / [i915#5190]) +2 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#4538]) +6 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@basic:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#2705])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_big_joiner@basic.html
* igt@kms_big_joiner@invalid-modeset:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#2705])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#10307]) +207 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#6095]) +41 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#6095]) +39 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-d-edp-1.html
* igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#10307] / [i915#10434]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][109] ([i915#6095]) +3 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#10278])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#6095]) +99 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][112] +200 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk8/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#7213]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-7/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#3742]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#4087]) +3 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-1/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#7828]) +4 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#7828]) +12 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#7828]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- shard-tglu: NOTRUN -> [SKIP][119] ([i915#7828]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_chamelium_hpd@dp-hpd-fast.html
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#7828]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#7118] / [i915#9424])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@srm:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#7116])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#6944] / [i915#9424]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#3555]) +7 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#3359])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#3555] / [i915#8814])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x21:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#8814]) +3 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#3555]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
- shard-tglu: NOTRUN -> [SKIP][130] ([i915#3555])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#3359]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#9809]) +1 other test skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#4103] / [i915#4213]) +2 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-snb: [PASS][134] -> [SKIP][135] +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-snb7/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-snb4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][136] -> [FAIL][137] ([i915#2346]) +1 other test fail
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#9833])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#9227])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#9723])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#8588])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][142] ([i915#8812])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#3840])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#3840])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#3555] / [i915#3840])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu: NOTRUN -> [SKIP][146] ([i915#3469])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_fbcon_fbt@psr-suspend.html
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#3469])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#9337])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-dg1: NOTRUN -> [SKIP][149] ([i915#658])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#3637]) +5 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#3637]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#8381]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][153] +13 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#9934]) +9 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-fences:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#8381])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#2672])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#3555] / [i915#8810])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#2672]) +1 other test skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][159] ([i915#2587] / [i915#2672])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][160] ([i915#2672] / [i915#3555])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][161] ([i915#2587] / [i915#2672]) +4 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#2672])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][163] ([i915#8708]) +5 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#1825]) +10 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][165] +58 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#5439])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#8708]) +5 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#8708]) +26 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#5354]) +10 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#1825]) +15 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#3458]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#10070])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#3023]) +5 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][174] +12 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#3458]) +22 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#3555] / [i915#8228])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#3555] / [i915#8228]) +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#4070] / [i915#4816])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#1839])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_lowres@tiling-yf:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#3555] / [i915#8821])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#5354] / [i915#9423])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#9423]) +11 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#5176]) +3 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#9423]) +7 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#9423]) +5 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#5176] / [i915#9423]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#5176] / [i915#9423]) +3 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#5235] / [i915#9423]) +11 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#5235]) +3 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#5235]) +9 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#5235]) +3 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#5235]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#5354])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_dc@dc5-dpms-negative:
- shard-mtlp: NOTRUN -> [SKIP][194] ([i915#9293])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_pm_dc@dc5-dpms-negative.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#9519])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][196] -> [SKIP][197] ([i915#9519]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-10/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#9519])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][199] ([i915#9808]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#4348])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#9683])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-pr-sprite-blt:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#9732]) +5 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_psr@fbc-pr-sprite-blt.html
* igt@kms_psr@fbc-psr-cursor-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][203] ([i915#9732]) +2 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@kms_psr@fbc-psr-cursor-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][204] ([i915#9732]) +28 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html
* igt@kms_psr@pr-primary-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#9688]) +10 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_psr@pr-primary-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#9673] / [i915#9732]) +4 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#9685])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg1: NOTRUN -> [SKIP][208] ([i915#4884])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#5289])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][210] ([i915#4235]) +1 other test skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#5190])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-mtlp: NOTRUN -> [SKIP][212] ([i915#5289])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#5289]) +2 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][214] -> [FAIL][215] ([IGT#2])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-1/igt@kms_sysfs_edid_timing.html
- shard-dg1: NOTRUN -> [FAIL][216] ([IGT#2] / [i915#6493])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg1: NOTRUN -> [SKIP][217] ([i915#8623])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg1: NOTRUN -> [SKIP][218] ([i915#9906])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#9906])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_vrr@seamless-rr-switch-drrs.html
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#9906])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-8/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output:
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#2437]) +1 other test skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@kms_writeback@writeback-check-output.html
- shard-glk: NOTRUN -> [SKIP][222] ([i915#2437])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk9/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#2437] / [i915#9412])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#2436] / [i915#7387])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config-invalid:
- shard-mtlp: NOTRUN -> [SKIP][225] ([i915#7387])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@perf@global-sseu-config-invalid.html
* igt@perf@mi-rpc:
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#2434])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#2435])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@faulting-read@gtt:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#8440])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@perf_pmu@faulting-read@gtt.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [INCOMPLETE][229] ([i915#5493])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-fence-mmap:
- shard-mtlp: NOTRUN -> [SKIP][230] ([i915#3708] / [i915#4077])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-gtt:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#3708] / [i915#4077])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#3708]) +1 other test skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-15/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#3708])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-mtlp: NOTRUN -> [SKIP][234] ([i915#9917])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg1: NOTRUN -> [SKIP][235] ([i915#9917])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-17/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-mtlp: NOTRUN -> [FAIL][236] ([i915#9781])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2: NOTRUN -> [SKIP][237] ([i915#4818])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#2575]) +8 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-7/igt@v3d/v3d_perfmon@create-perfmon-exceed.html
* igt@v3d/v3d_perfmon@create-single-perfmon:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#2575]) +3 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@v3d/v3d_perfmon@create-single-perfmon.html
* igt@v3d/v3d_submit_cl@job-perfmon:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#2575]) +15 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@v3d/v3d_submit_cl@job-perfmon.html
* igt@vc4/vc4_label_bo@set-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][241] ([i915#7711]) +4 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-1/igt@vc4/vc4_label_bo@set-bad-handle.html
* igt@vc4/vc4_label_bo@set-label:
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#2575]) +2 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_perfmon@destroy-invalid-perfmon:
- shard-rkl: NOTRUN -> [SKIP][243] ([i915#7711]) +1 other test skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@vc4/vc4_perfmon@destroy-invalid-perfmon.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged:
- shard-dg1: NOTRUN -> [SKIP][244] ([i915#7711]) +7 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-13/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged.html
* igt@vc4/vc4_wait_bo@unused-bo-1ns:
- shard-dg2: NOTRUN -> [SKIP][245] ([i915#7711]) +1 other test skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-11/igt@vc4/vc4_wait_bo@unused-bo-1ns.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][246] ([i915#6268]) -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
- shard-tglu: [FAIL][248] ([i915#6268]) -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@ccs3:
- shard-dg2: [FAIL][250] ([i915#10086]) -> [PASS][251]
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@ccs3.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-8/igt@gem_ctx_isolation@preservation-s3@ccs3.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][252] ([i915#10030] / [i915#7975] / [i915#8213]) -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-10/igt@gem_eio@hibernate.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-7/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg1: [INCOMPLETE][254] ([i915#10513]) -> [PASS][255]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg1-17/igt@gem_eio@kms.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-16/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][256] ([i915#2842]) -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_gttfill@engines@vcs1:
- shard-dg2: [INCOMPLETE][258] -> [PASS][259]
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-3/igt@gem_exec_gttfill@engines@vcs1.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-3/igt@gem_exec_gttfill@engines@vcs1.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-dg2: [INCOMPLETE][260] ([i915#9857]) -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-11/igt@gem_exec_whisper@basic-contexts-forked-all.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_lmem_swapping@heavy-multi@lmem0:
- shard-dg2: [FAIL][262] ([i915#10378]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-11/igt@gem_lmem_swapping@heavy-multi@lmem0.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@gem_lmem_swapping@heavy-multi@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [INCOMPLETE][264] ([i915#9820] / [i915#9849]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-suspend@gt0:
- shard-dg2: [FAIL][266] -> [PASS][267]
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-5/igt@i915_pm_freq_api@freq-suspend@gt0.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-8/igt@i915_pm_freq_api@freq-suspend@gt0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: [FAIL][268] ([i915#3743]) -> [PASS][269] +2 other tests pass
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][270] ([i915#79]) -> [PASS][271]
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1:
- shard-snb: [FAIL][272] ([i915#2122]) -> [PASS][273] +1 other test pass
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-snb7/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-snb4/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
- shard-dg2: [FAIL][274] ([i915#6880]) -> [PASS][275]
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2: [SKIP][276] ([i915#9519]) -> [PASS][277]
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-10/igt@kms_pm_rpm@dpms-non-lpsp.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-5/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg2: [FAIL][278] ([i915#8717]) -> [PASS][279]
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-2/igt@kms_pm_rpm@i2c.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-10/igt@kms_pm_rpm@i2c.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-rkl: [ABORT][280] ([i915#8875] / [i915#9926]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-rkl-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-rkl-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [FAIL][282] ([i915#9196]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
#### Warnings ####
* igt@gem_eio@kms:
- shard-dg2: [INCOMPLETE][284] ([i915#10513] / [i915#1982]) -> [INCOMPLETE][285] ([i915#10513])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-7/igt@gem_eio@kms.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-7/igt@gem_eio@kms.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [INCOMPLETE][286] ([i915#9820]) -> [INCOMPLETE][287] ([i915#9697] / [i915#9820])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-tglu: [FAIL][288] ([i915#3591]) -> [WARN][289] ([i915#2681])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@kms_psr@fbc-psr-primary-mmap-gtt:
- shard-dg2: [SKIP][290] ([i915#9673] / [i915#9732]) -> [SKIP][291] ([i915#9732]) +13 other tests skip
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-11/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-1/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][292] ([i915#7484]) -> [FAIL][293] ([i915#9100])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14468/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10030]: https://gitlab.freedesktop.org/drm/intel/issues/10030
[i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
[i915#10086]: https://gitlab.freedesktop.org/drm/intel/issues/10086
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/intel/issues/10513
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
[i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9561]: https://gitlab.freedesktop.org/drm/intel/issues/9561
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9697]: https://gitlab.freedesktop.org/drm/intel/issues/9697
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9857]: https://gitlab.freedesktop.org/drm/intel/issues/9857
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9926]: https://gitlab.freedesktop.org/drm/intel/issues/9926
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14468 -> Patchwork_130480v2
CI-20190529: 20190529
CI_DRM_14468: a19e6423c2c21b8dc7ad79ca95cc24637b248bd0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7777: 7777
Patchwork_130480v2: a19e6423c2c21b8dc7ad79ca95cc24637b248bd0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v2/index.html
[-- Attachment #2: Type: text/html, Size: 97749 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-22 18:06 ` Ville Syrjälä
@ 2024-03-25 8:59 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2024-03-25 8:59 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 22, 2024 at 08:06:46PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 22, 2024 at 01:40:46PM +0200, Stanislav Lisovskiy wrote:
> > Currently we can't change MBUS join status without doing a modeset,
> > because we are lacking mechanism to synchronize those with vblank.
> > However then this means that we can't do a fastset, if there is a need
> > to change MBUS join state. Fix that by implementing such change.
> > We already call correspondent check and update at pre_plane dbuf update,
> > so the only thing left is to have a non-modeset version of that.
> > If active pipes stay the same then fastset is possible and only MBUS
> > join state/ddb allocation updates would be committed.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 +-
> > drivers/gpu/drm/i915/display/skl_watermark.c | 108 +++++++++++++++----
> > drivers/gpu/drm/i915/display/skl_watermark.h | 2 +
> > 3 files changed, 94 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index b88f214e111ae..d5351f6fa2eb4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6895,6 +6895,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > intel_pre_update_crtc(state, crtc);
> > }
> >
> > + intel_dbuf_mbus_pre_ddb_update(state);
> > +
> > while (update_pipes) {
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > @@ -6925,6 +6927,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > }
> > }
> >
> > + intel_dbuf_mbus_post_ddb_update(state);
> > +
> > update_pipes = modeset_pipes;
> >
> > /*
> > @@ -7169,9 +7173,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > }
> >
> > intel_encoders_update_prepare(state);
> > -
> > intel_dbuf_pre_plane_update(state);
> > - intel_mbus_dbox_update(state);
> >
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (new_crtc_state->do_async_flip)
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 7eb78e0c8c8e3..eee13b57d4830 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include <drm/drm_blend.h>
> > +#include <drm/drm_print.h>
> >
> > #include "i915_drv.h"
> > #include "i915_fixed.h"
> > @@ -2636,13 +2637,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> > - /* TODO: Implement vblank synchronized MBUS joining changes */
> > - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> > - if (ret)
> > - return ret;
> > - }
> > -
> > drm_dbg_kms(&i915->drm,
> > "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> > old_dbuf_state->enabled_slices,
> > @@ -3594,30 +3588,57 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
> > new_dbuf_state->joined_mbus);
> > }
> >
> > +static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
> > + const struct intel_dbuf_state *dbuf_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + enum pipe sync_pipe = ffs(dbuf_state->active_pipes) - 1;
> > + struct intel_crtc_state *new_crtc_state;
>
> const
>
> > + struct intel_crtc *crtc;
> > +
> > + drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
> > + drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
> > +
> > + crtc = intel_crtc_for_pipe(i915, sync_pipe);
> > + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > +
> > + if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
> > + return sync_pipe;
> > + else
> > + return INVALID_PIPE;
> > +}
> > +
> > /*
> > * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
> > * update the request state of all DBUS slices.
> > */
> > -static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
> > +static void intel_dbuf_mbus_ctl_update(struct intel_atomic_state *state,
> > + enum pipe sync_pipe)
> > {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > u32 mbus_ctl;
> > const struct intel_dbuf_state *new_dbuf_state =
> > intel_atomic_get_new_dbuf_state(state);
> > + u32 pipe_select;
> >
> > if (!HAS_MBUS_JOINING(i915))
> > return;
> >
> > + if (sync_pipe != INVALID_PIPE)
> > + pipe_select = MBUS_JOIN_PIPE_SELECT(sync_pipe);
> > + else
> > + pipe_select = MBUS_JOIN_PIPE_SELECT_NONE;
> > +
> > /*
> > * TODO: Implement vblank synchronized MBUS joining changes.
> > * Must be properly coordinated with dbuf reprogramming.
> > */
> > if (new_dbuf_state->joined_mbus)
> > mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> > - MBUS_JOIN_PIPE_SELECT_NONE;
> > + pipe_select;
> > else
> > mbus_ctl = MBUS_HASHING_MODE_2x2 |
> > - MBUS_JOIN_PIPE_SELECT_NONE;
> > + pipe_select;
>
> The 'pipe_select' variable looks completely redundant.
> You can just do
> if (sync_pipe != INVALID_PIPE)
> mbus_ctl |= ...
> else
> mbus_ctl |= ...
> directly here.
>
> >
> > intel_de_rmw(i915, MBUS_CTL,
> > MBUS_HASHING_MODE_MASK | MBUS_JOIN |
> > @@ -3632,6 +3653,42 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> > const struct intel_dbuf_state *old_dbuf_state =
> > intel_atomic_get_old_dbuf_state(state);
> >
> > + if (!new_dbuf_state ||
> > + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
>
> redundant parens.
>
> > + return;
> > +
> > + WARN_ON(!new_dbuf_state->base.changed);
> > +
> > + gen9_dbuf_slices_update(i915,
> > + old_dbuf_state->enabled_slices |
> > + new_dbuf_state->enabled_slices);
> > +}
> > +
> > +void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + const struct intel_dbuf_state *new_dbuf_state =
> > + intel_atomic_get_new_dbuf_state(state);
> > + const struct intel_dbuf_state *old_dbuf_state =
> > + intel_atomic_get_old_dbuf_state(state);
> > +
> > + if (!new_dbuf_state ||
> > + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices))
>
> ditto
>
> > + return;
> > +
> > + WARN_ON(!new_dbuf_state->base.changed);
> > +
> > + gen9_dbuf_slices_update(i915,
> > + new_dbuf_state->enabled_slices);
> > +}
> > +
> > +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
> > +{
> > + const struct intel_dbuf_state *new_dbuf_state =
> > + intel_atomic_get_new_dbuf_state(state);
> > + const struct intel_dbuf_state *old_dbuf_state =
> > + intel_atomic_get_old_dbuf_state(state);
> > +
> > if (!new_dbuf_state ||
> > (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > @@ -3640,16 +3697,15 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> > WARN_ON(!new_dbuf_state->base.changed);
> >
> > if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
> > - intel_dbuf_mbus_join_update(state);
> > + enum pipe sync_pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
> > +
> > + intel_dbuf_mbus_ctl_update(state, sync_pipe);
> > + intel_mbus_dbox_update(state);
> > intel_dbuf_mdclk_min_tracker_update(state);
> > }
> > -
> > - gen9_dbuf_slices_update(i915,
> > - old_dbuf_state->enabled_slices |
> > - new_dbuf_state->enabled_slices);
> > }
> >
> > -void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > const struct intel_dbuf_state *new_dbuf_state =
> > @@ -3657,6 +3713,12 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > const struct intel_dbuf_state *old_dbuf_state =
> > intel_atomic_get_old_dbuf_state(state);
> >
> > + if (new_dbuf_state && old_dbuf_state &&
> > + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus) {
> > + intel_dbuf_mdclk_min_tracker_update(state);
> > + intel_mbus_dbox_update(state);
> > + }
>
> I still think should go into one of the new ddb hooks.
> I think we want to program these before the new planes
> get enabled. So I'd probably stuff this into the post ddb
> hook.
I almost got confused myself, because I was really sure I've done this.
Checked the code - it is exactly in intel_dbuf_mbus_post_ddb_update.
If you check above you will see
> > -void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
But was good one, already thought I messed up the commit or smth.
>
> > +
> > if (!new_dbuf_state ||
> > (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > @@ -3665,12 +3727,18 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > WARN_ON(!new_dbuf_state->base.changed);
> >
> > if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
> > - intel_dbuf_mbus_join_update(state);
> > + enum pipe sync_pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
> > +
> > intel_dbuf_mdclk_min_tracker_update(state);
> > - }
> > + intel_mbus_dbox_update(state);
> > + intel_dbuf_mbus_ctl_update(state, sync_pipe);
> >
> > - gen9_dbuf_slices_update(i915,
> > - new_dbuf_state->enabled_slices);
> > + if (sync_pipe != INVALID_PIPE) {
> > + struct intel_crtc *crtc = intel_crtc_for_pipe(i915, sync_pipe);
> > +
> > + intel_crtc_wait_for_next_vblank(crtc);
> > + }
> > + }
> > }
> >
> > static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> > index 3a90741cab06a..f6d38b41e3a6c 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> > @@ -77,6 +77,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> > void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> > void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> > void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
> > +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
> > +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> > void intel_mbus_dbox_update(struct intel_atomic_state *state);
> >
> > #endif /* __SKL_WATERMARK_H__ */
> > --
> > 2.37.3
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-22 11:40 ` [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
2024-03-22 18:06 ` Ville Syrjälä
@ 2024-03-25 9:09 ` Stanislav Lisovskiy
1 sibling, 0 replies; 18+ messages in thread
From: Stanislav Lisovskiy @ 2024-03-25 9:09 UTC (permalink / raw
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
Currently we can't change MBUS join status without doing a modeset,
because we are lacking mechanism to synchronize those with vblank.
However then this means that we can't do a fastset, if there is a need
to change MBUS join state. Fix that by implementing such change.
We already call correspondent check and update at pre_plane dbuf update,
so the only thing left is to have a non-modeset version of that.
If active pipes stay the same then fastset is possible and only MBUS
join state/ddb allocation updates would be committed.
v2: - Removed redundant parentheses(Ville Syrjälä)
- Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä)
- Removed pipe_select variable(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 119 +++++++++++++++----
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +
3 files changed, 101 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b88f214e111ae..d5351f6fa2eb4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6895,6 +6895,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
intel_pre_update_crtc(state, crtc);
}
+ intel_dbuf_mbus_pre_ddb_update(state);
+
while (update_pipes) {
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -6925,6 +6927,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
}
}
+ intel_dbuf_mbus_post_ddb_update(state);
+
update_pipes = modeset_pipes;
/*
@@ -7169,9 +7173,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
intel_encoders_update_prepare(state);
-
intel_dbuf_pre_plane_update(state);
- intel_mbus_dbox_update(state);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7eb78e0c8c8e3..7f2b4dc2a27d4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_blend.h>
+#include <drm/drm_print.h>
#include "i915_drv.h"
#include "i915_fixed.h"
@@ -2636,13 +2637,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
if (ret)
return ret;
- if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
- /* TODO: Implement vblank synchronized MBUS joining changes */
- ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
- if (ret)
- return ret;
- }
-
drm_dbg_kms(&i915->drm,
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
@@ -3594,11 +3588,32 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state
new_dbuf_state->joined_mbus);
}
+static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,
+ const struct intel_dbuf_state *dbuf_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ enum pipe sync_pipe = ffs(dbuf_state->active_pipes) - 1;
+ const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+
+ drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus);
+ drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes));
+
+ crtc = intel_crtc_for_pipe(i915, sync_pipe);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))
+ return sync_pipe;
+ else
+ return INVALID_PIPE;
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_ctl_update(struct intel_atomic_state *state,
+ enum pipe sync_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl;
@@ -3612,12 +3627,21 @@ static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state)
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
*/
- if (new_dbuf_state->joined_mbus)
- mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
- MBUS_JOIN_PIPE_SELECT_NONE;
- else
- mbus_ctl = MBUS_HASHING_MODE_2x2 |
- MBUS_JOIN_PIPE_SELECT_NONE;
+ if (new_dbuf_state->joined_mbus) {
+ if (sync_pipe != INVALID_PIPE)
+ mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
+ MBUS_JOIN_PIPE_SELECT(sync_pipe);
+ else
+ mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
+ MBUS_JOIN_PIPE_SELECT_NONE;
+ } else {
+ if (sync_pipe != INVALID_PIPE)
+ mbus_ctl = MBUS_HASHING_MODE_2x2 |
+ MBUS_JOIN_PIPE_SELECT(sync_pipe);
+ else
+ mbus_ctl = MBUS_HASHING_MODE_2x2 |
+ MBUS_JOIN_PIPE_SELECT_NONE;
+ }
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
@@ -3632,6 +3656,42 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
+ if (!new_dbuf_state ||
+ new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
+ return;
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ gen9_dbuf_slices_update(i915,
+ old_dbuf_state->enabled_slices |
+ new_dbuf_state->enabled_slices);
+}
+
+void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+
+ if (!new_dbuf_state ||
+ new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
+ return;
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ gen9_dbuf_slices_update(i915,
+ new_dbuf_state->enabled_slices);
+}
+
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)
+{
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
@@ -3640,16 +3700,15 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {
- intel_dbuf_mbus_join_update(state);
+ enum pipe sync_pipe = intel_mbus_joined_pipe(state, new_dbuf_state);
+
+ intel_dbuf_mbus_ctl_update(state, sync_pipe);
+ intel_mbus_dbox_update(state);
intel_dbuf_mdclk_min_tracker_update(state);
}
-
- gen9_dbuf_slices_update(i915,
- old_dbuf_state->enabled_slices |
- new_dbuf_state->enabled_slices);
}
-void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_dbuf_state *new_dbuf_state =
@@ -3657,6 +3716,12 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state && old_dbuf_state &&
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus) {
+ intel_dbuf_mdclk_min_tracker_update(state);
+ intel_mbus_dbox_update(state);
+ }
+
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
@@ -3665,12 +3730,18 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {
- intel_dbuf_mbus_join_update(state);
+ enum pipe sync_pipe = intel_mbus_joined_pipe(state, old_dbuf_state);
+
intel_dbuf_mdclk_min_tracker_update(state);
- }
+ intel_mbus_dbox_update(state);
+ intel_dbuf_mbus_ctl_update(state, sync_pipe);
- gen9_dbuf_slices_update(i915,
- new_dbuf_state->enabled_slices);
+ if (sync_pipe != INVALID_PIPE) {
+ struct intel_crtc *crtc = intel_crtc_for_pipe(i915, sync_pipe);
+
+ intel_crtc_wait_for_next_vblank(crtc);
+ }
+ }
}
static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 3a90741cab06a..f6d38b41e3a6c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -77,6 +77,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);
+void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
void intel_mbus_dbox_update(struct intel_atomic_state *state);
#endif /* __SKL_WATERMARK_H__ */
--
2.37.3
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK
2024-03-22 17:45 ` Ville Syrjälä
@ 2024-03-25 14:44 ` Gustavo Sousa
2024-03-25 14:55 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Gustavo Sousa @ 2024-03-25 14:44 UTC (permalink / raw
To: Stanislav Lisovskiy, Ville Syrjälä; +Cc: intel-gfx, jani.saarinen
Quoting Ville Syrjälä (2024-03-22 14:45:29-03:00)
>On Fri, Mar 22, 2024 at 01:40:44PM +0200, Stanislav Lisovskiy wrote:
>> In order to make sure we are not breaking the proper sequence
>> lets to updates step by step and don't change MBUS join value
>> during MDCLK/CDCLK programming stage.
>> MBUS join programming would be taken care by pre/post ddb hooks.
>>
>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 31aaa9780dfcf..43a9616c78260 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2611,9 +2611,19 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>>
>> if (pipe == INVALID_PIPE ||
>> old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
>> + struct intel_cdclk_config cdclk_config;
>> +
>> drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>>
>> - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
>> + /*
>> + * By this hack we want to prevent mbus_join to be programmed
>> + * beforehand - we will take care of this later in pre ddb
>> + * programming hook.
>> + */
>
>We're not doing anything to prevent mbus joining to be
>programmed here. It will simply not be programmed here,
>which is why we need to use the old mbus_join based ratio.
Hey, guys.
Just so I understand this better. What I understood from the
recent discussion was:
CDCLK programming should only care about the current MBus joining
state and not consider the new one in the current hardware commit,
which must actually be handled later in the sequence by the proper
"entity".
Is my understanding correct? If so, sorry for the confusion introduced
by my patches.
My previous understanding was that that the CDCLK change sequence would
need to consider the new MBus joining state in case we were in a modeset
where mbus joining changed, so I added that odd-looking condition in
update_mbus_pre_enable() (not moved into
intel_dbuf_mdclk_min_tracker_update()), thinking that the update should
be handled by the cdclk sequence.
--
Gustavo Sousa
>
>I would also include the actual function name here instead
>of "pre ddb programming hook" since that's rather vague.
>
>So this could use a bit of rewording. Otherwise lgtm
>Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> + cdclk_config = new_cdclk_state->actual;
>> + cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
>> +
>> + intel_set_cdclk(i915, &cdclk_config, pipe);
>> }
>> }
>>
>> --
>> 2.37.3
>
>--
>Ville Syrjälä
>Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK
2024-03-25 14:44 ` Gustavo Sousa
@ 2024-03-25 14:55 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-03-25 14:55 UTC (permalink / raw
To: Gustavo Sousa; +Cc: Stanislav Lisovskiy, intel-gfx, jani.saarinen
On Mon, Mar 25, 2024 at 11:44:59AM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjälä (2024-03-22 14:45:29-03:00)
> >On Fri, Mar 22, 2024 at 01:40:44PM +0200, Stanislav Lisovskiy wrote:
> >> In order to make sure we are not breaking the proper sequence
> >> lets to updates step by step and don't change MBUS join value
> >> during MDCLK/CDCLK programming stage.
> >> MBUS join programming would be taken care by pre/post ddb hooks.
> >>
> >> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++++++++-
> >> 1 file changed, 11 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 31aaa9780dfcf..43a9616c78260 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -2611,9 +2611,19 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> >>
> >> if (pipe == INVALID_PIPE ||
> >> old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
> >> + struct intel_cdclk_config cdclk_config;
> >> +
> >> drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> >>
> >> - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
> >> + /*
> >> + * By this hack we want to prevent mbus_join to be programmed
> >> + * beforehand - we will take care of this later in pre ddb
> >> + * programming hook.
> >> + */
> >
> >We're not doing anything to prevent mbus joining to be
> >programmed here. It will simply not be programmed here,
> >which is why we need to use the old mbus_join based ratio.
>
> Hey, guys.
>
> Just so I understand this better. What I understood from the
> recent discussion was:
>
> CDCLK programming should only care about the current MBus joining
> state and not consider the new one in the current hardware commit,
> which must actually be handled later in the sequence by the proper
> "entity".
>
> Is my understanding correct? If so, sorry for the confusion introduced
> by my patches.
>
> My previous understanding was that that the CDCLK change sequence would
> need to consider the new MBus joining state in case we were in a modeset
> where mbus joining changed, so I added that odd-looking condition in
> update_mbus_pre_enable() (not moved into
> intel_dbuf_mdclk_min_tracker_update()), thinking that the update should
> be handled by the cdclk sequence.
I don't think we can handle it from the cdclk code as
that can't handle the proper ordering between plane
ddb updates vs. mbus_join changes.
It's rather infuriating that we need to update the ratio
from both places. I'm not sure how careful we actually
have to be between programming the ratio vs. actually
changing mbus_join+mdclk/cdclk. I guess we should ask
the hardware folks for more details and if the sequence
doesn't have to super accurate then maybe think about
a simpler way to do things...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-03-25 14:55 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-22 11:40 [PATCH 0/5] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-03-22 11:40 ` [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
2024-03-22 17:46 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts Stanislav Lisovskiy
2024-03-22 17:50 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK Stanislav Lisovskiy
2024-03-22 17:45 ` Ville Syrjälä
2024-03-25 14:44 ` Gustavo Sousa
2024-03-25 14:55 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Stanislav Lisovskiy
2024-03-22 17:51 ` Ville Syrjälä
2024-03-22 11:40 ` [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
2024-03-22 18:06 ` Ville Syrjälä
2024-03-25 8:59 ` Lisovskiy, Stanislav
2024-03-25 9:09 ` [PATCH 3/3] " Stanislav Lisovskiy
2024-03-22 12:28 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change (rev2) Patchwork
2024-03-22 12:41 ` ✓ Fi.CI.BAT: success " Patchwork
2024-03-23 8:31 ` ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.