* [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
@ 2021-06-04 9:43 Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops Masami Hiramatsu
` (13 more replies)
0 siblings, 14 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:43 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Hi,
Here is the 5th version of the series (including some fixes for build
errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot.
This series includes not only DeveloperBox support but also some fixes
for the issues which I faced while porting U-Boot on the DeveloperBox.
First 3 patches are fixes, next 1 patch is a code cleanup for generic
gpio for arm. The next 7 patches adding DeveloperBox devices
and board support. The last 2 patches are related to the UEFI capsule
update.
Previous version is here:
https://lists.denx.de/pipermail/u-boot/2021-May/449305.html
Changes in v5
-------------
I dripped dfu_mtd bugfix patch (previous [12/14]) from this,
because Sughosh already fixed it.
[11/13]:
- Remove log level from config.
DeveloperBox
============
DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: -
* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard
* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
(1x slots are connected via PCIe bridge chip)
* 4 USB-3.0 ports
* 2 SATA ports
* 1 GbE network port
* 1 USB-UART serial port (micro USB)
* 64MB SPI NOR Flash
* 8GB eMMC Flash Storage
* 96boards LS connector
The DeveloperBox schematic can be found here: -
https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
And the other documents can be found here: -
https://www.96boards.org/documentation/enterprise/developerbox/
Currently, the U-Boot port supports: -
* USB
* eMMC
* SPI-NOR
* SATA
* GbE
The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
BL33, but no need to combine with it.
Thank you,
---
Jassi Brar (4):
mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
net: synquacer: Add netsec driver
i2c: synquacer: SNI Synquacer I2C controller
Masami Hiramatsu (9):
ata: ahci-pci: Use scsi_ops to initialize ops
dm: pci: Skip setting VGA bridge bits if parent device is the host bus
efi: Fix to use null handle to create new handle for efi_fmp_raw
gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
pci: synquacer: Add SynQuacer ECAM based PCIe driver
ARM: dts: synquacer: Add device trees for DeveloperBox
board: synquacer: Add DeveloperBox 96boards EE support
doc: qemu: arm64: Fix the documentation of capsule update
configs: synquacer: Enable EFI capsule update support
arch/arm/Kconfig | 108 ++
arch/arm/dts/Makefile | 2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 +
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 +
arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++++++++++
arch/arm/include/asm/gpio.h | 8
board/socionext/developerbox/Kconfig | 36 +
board/socionext/developerbox/MAINTAINERS | 14
board/socionext/developerbox/Makefile | 9
board/socionext/developerbox/developerbox.c | 146 +++
configs/synquacer_developerbox_defconfig | 129 ++
doc/board/emulation/qemu_capsule_update.rst | 11
doc/board/index.rst | 1
doc/board/socionext/developerbox.rst | 87 ++
doc/board/socionext/index.rst | 9
drivers/ata/ahci-pci.c | 2
drivers/i2c/Kconfig | 7
drivers/i2c/Makefile | 1
drivers/i2c/synquacer_i2c.c | 338 ++++++
drivers/mmc/Kconfig | 10
drivers/mmc/Makefile | 1
drivers/mmc/f_sdh30.c | 81 +
drivers/net/Kconfig | 8
drivers/net/Makefile | 1
drivers/net/sni_netsec.c | 1134 ++++++++++++++++++++
drivers/pci/Kconfig | 12
drivers/pci/Makefile | 1
drivers/pci/pci-uclass.c | 3
drivers/pci/pcie_ecam_synquacer.c | 600 +++++++++++
drivers/spi/Kconfig | 8
drivers/spi/Makefile | 1
drivers/spi/spi-synquacer.c | 491 +++++++++
include/configs/synquacer.h | 115 ++
lib/efi_loader/efi_capsule.c | 2
35 files changed, 4158 insertions(+), 17 deletions(-)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
create mode 100644 board/socionext/developerbox/Kconfig
create mode 100644 board/socionext/developerbox/MAINTAINERS
create mode 100644 board/socionext/developerbox/Makefile
create mode 100644 board/socionext/developerbox/developerbox.c
create mode 100644 configs/synquacer_developerbox_defconfig
create mode 100644 doc/board/socionext/developerbox.rst
create mode 100644 doc/board/socionext/index.rst
create mode 100644 drivers/i2c/synquacer_i2c.c
create mode 100644 drivers/mmc/f_sdh30.c
create mode 100644 drivers/net/sni_netsec.c
create mode 100644 drivers/pci/pcie_ecam_synquacer.c
create mode 100644 drivers/spi/spi-synquacer.c
create mode 100644 include/configs/synquacer.h
--
Masami Hiramatsu <masami.hiramatsu@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
@ 2021-06-04 9:43 ` Masami Hiramatsu
2021-07-06 22:50 ` Tom Rini
2021-06-04 9:43 ` [PATCH v5 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus Masami Hiramatsu
` (12 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:43 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
drivers/ata/ahci-pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f..b1d231e0f9 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <ahci.h>
+#include <scsi.h>
#include <dm.h>
#include <pci.h>
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops = &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops Masami Hiramatsu
@ 2021-06-04 9:43 ` Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw Masami Hiramatsu
` (11 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:43 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [78000000-7fffffff],
Physical Memory [78000000-7fffffffx]
PCI Autoconfig: Bus I/O region: [0-ffff],
Physical Memory [77f00000-77f0ffffx]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000
PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000
"Synchronous Abort" handler, esr 0x96000006
elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc)
elr: 00000000fff6fd28 lr : 00000000fff6fce8
x0 : 0000000000001041 x1 : 000000000000003e
x2 : 00000000ffb0f8c8 x3 : 0000000000000001
x4 : 0000000000000080 x5 : 0000000000000000
x6 : 00000000fff718fc x7 : 000000000000000f
x8 : 00000000ffb0f238 x9 : 0000000000000008
x10: 0000000000000000 x11: 0000000000000010
x12: 0000000000000006 x13: 000000000001869f
x14: 00000000ffb0fcd0 x15: 0000000000000020
x16: 00000000fff71cc4 x17: 0000000000000000
x18: 00000000ffb13d90 x19: 00000000ffb14320
x20: 0000000000000000 x21: 00000000ffb14090
x22: 00000000ffb0f8c8 x23: 0000000000000001
x24: 00000000ffb14c10 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000ffb14c70 x29: 00000000ffb0f830
Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
drivers/pci/pci-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e632..afe4f1974a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus Masami Hiramatsu
@ 2021-06-04 9:43 ` Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 04/13] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Masami Hiramatsu
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:43 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
When running the efidebug capsule disk-update command, the efi_fmp_raw
protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as
below. This is because the code passes efi_root instaed of handle.
=> efidebug capsule disk-update
EFI: Call: efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbaf5988)
EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(00000000fbaf5988, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6ee8)
EFI: new handle 00000000fbb37520
EFI: Exit: efi_install_protocol_interface: 0
EFI: 0 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 0
EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)
EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbfec648)
EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Entry efi_install_protocol_interface(00000000fbfec648, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6f18)
EFI: handle 00000000fbaf8520
EFI: Exit: efi_install_protocol_interface: 2
EFI: 2 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface)
EFI: Exit: efi_install_multiple_protocol_interfaces: 2
EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)
Command failed, result=1
To fix this issue, pass the handle variable as same as the efi_fmp_fit
installation.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
lib/efi_loader/efi_capsule.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 9ead0d2c78..71d3d1e523 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -939,7 +939,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
handle = NULL;
ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
- &efi_root,
+ &handle,
&efi_guid_firmware_management_protocol,
&efi_fmp_raw, NULL));
}
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 04/13] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (2 preceding siblings ...)
2021-06-04 9:43 ` [PATCH v5 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw Masami Hiramatsu
@ 2021-06-04 9:43 ` Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 05/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver Masami Hiramatsu
` (9 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:43 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Since some SoCs and boards do not hae extra asm/arch/gpio.h,
introduce CONFIG_GPIO_EXTRA_HEADER instead of adding
!define(CONFIG_ARCH_XXXX) in asm/gpio.h.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
Changes in v3:
- Change the config name to positive and selected by the
opposite CONFIG_ARCH_*. (Build checked by Github CI)
---
arch/arm/Kconfig | 94 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/gpio.h | 8 ----
2 files changed, 95 insertions(+), 7 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 31d687ea01..023824df77 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -90,6 +90,9 @@ config HAS_VBAR
config HAS_THUMB2
bool
+config GPIO_EXTRA_HEADER
+ bool
+
# Used for compatibility with asm files copied from the kernel
config ARM_ASM_UNIFIED
bool
@@ -518,25 +521,30 @@ choice
config ARCH_AT91
bool "Atmel AT91"
+ select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
+ select GPIO_EXTRA_HEADER
select PL010_SERIAL
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config TARGET_GPLUGD
bool "Support gplugd"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select SPL_DM_SPI if SPL
imply CMD_SAVES
help
@@ -547,6 +555,7 @@ config ARCH_KIRKWOOD
select ARCH_MISC_INIT
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@@ -555,6 +564,7 @@ config ARCH_MVEBU
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select GPIO_EXTRA_HEADER
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select OF_CONTROL
@@ -565,11 +575,13 @@ config ARCH_MVEBU
config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config TARGET_SPEAR300
bool "Support spear300"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -577,6 +589,7 @@ config TARGET_SPEAR310
bool "Support spear310"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -584,6 +597,7 @@ config TARGET_SPEAR320
bool "Support spear320"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -591,6 +605,7 @@ config TARGET_SPEAR600
bool "Support spear600"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -601,6 +616,7 @@ config TARGET_STV0991
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select SPI
select SPI_FLASH
@@ -610,18 +626,21 @@ config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
+ select GPIO_EXTRA_HEADER
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SERIAL_SEARCH_ALL
@@ -650,6 +669,7 @@ config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select OF_PRIOR_STAGE
imply CMD_DM
@@ -660,6 +680,7 @@ config ARCH_BCMSTB
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
imply BCM_SF2_ETH
imply BCM_SF2_ETH_GMAC
imply CMD_HASH
@@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
+ select GPIO_EXTRA_HEADER
help
Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
ARMv8 Cortex-A57 processors targeting a broad range of networking
@@ -695,6 +717,7 @@ config ARCH_EXYNOS
select DM_SPI
select DM_SPI_FLASH
select SPI
+ select GPIO_EXTRA_HEADER
imply SYS_THUMB_BUILD
imply CMD_DM
imply FAT_WRITE
@@ -706,6 +729,7 @@ config ARCH_S5PC1XX
select DM_GPIO
select DM_I2C
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_HIGHBANK
@@ -726,6 +750,7 @@ config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
imply CMD_DM
@@ -736,6 +761,7 @@ config ARCH_IPQ40XX
select DM_GPIO
select DM_SERIAL
select DM_RESET
+ select GPIO_EXTRA_HEADER
select MSM_SMEM
select PINCTRL
select CLK
@@ -747,6 +773,7 @@ config ARCH_KEYSTONE
bool "TI Keystone"
select CMD_POWEROFF
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select SYS_ARCH_TIMER
select SYS_THUMB_BUILD
@@ -763,6 +790,7 @@ config ARCH_K3
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
@@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS
config ARCH_MESON
bool "Amlogic Meson"
+ select GPIO_EXTRA_HEADER
imply DISTRO_DEFAULTS
imply DM_RNG
help
@@ -781,6 +810,7 @@ config ARCH_MESON
config ARCH_MEDIATEK
bool "MediaTek SoCs"
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_DM if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
@@ -797,6 +827,7 @@ config ARCH_LPC32XX
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SUPPORT_SPL
imply CMD_DM
@@ -805,12 +836,14 @@ config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARM64
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -823,33 +856,39 @@ config ARCH_IMXRT
select CPU_V7M
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
imply CMD_DM
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
imply MXC_GPIO
config ARCH_MX28
bool "NXP i.MX28 family"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
+ select GPIO_EXTRA_HEADER
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -861,6 +900,7 @@ config ARCH_MX7
bool "Freescale MX7"
select ARCH_MISC_INIT
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -871,6 +911,7 @@ config ARCH_MX7
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -886,18 +927,21 @@ config ARCH_MX5
bool "Freescale MX5"
select BOARD_EARLY_INIT_F
select CPU_V7A
+ select GPIO_EXTRA_HEADER
imply MXC_GPIO
config ARCH_NEXELL
bool "Nexell S5P4418/S5P6818 SoC"
select ENABLE_ARM_SOC_BOOT0_HOOK
select DM
+ select GPIO_EXTRA_HEADER
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
select DM_ETH
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OWL_SERIAL
select CLK
select CLK_OWL
@@ -920,6 +964,7 @@ config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
@@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
@@ -947,6 +993,7 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
@@ -998,6 +1045,7 @@ config ARCH_SUNXI
select DM_SCSI if SCSI
select DM_SERIAL
select DM_USB if DISTRO_DEFAULTS
+ select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
@@ -1057,6 +1105,7 @@ config ARCH_VERSAL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -1064,6 +1113,7 @@ config ARCH_VERSAL
config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply MTD_RAW_NAND
@@ -1080,6 +1130,7 @@ config ARCH_ZYNQ
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPI
select SPL_BOARD_INIT if SPL
@@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
imply CMD_DM
imply DM_USB_GADGET
@@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP
select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
select FIRMWARE
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
@@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP
config ARCH_TEGRA
bool "NVIDIA Tegra"
+ select GPIO_EXTRA_HEADER
imply DISTRO_DEFAULTS
imply FAT_WRITE
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select SEMIHOSTING
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select DM
select OF_CONTROL
@@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU
select ARM64
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS2080A_EMU platform.
The LS2080A Development System (EMULATOR) is a pre-silicon
@@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
@@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
imply SCSI
imply SCSI_AHCI
@@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
help
Support for Freescale LS2081ARDB platform.
@@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2160ARDB platform.
The lx2160ardb (LX2160A Reference design board (RDB)
@@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2160AQDS platform.
The lx2160aqds (LX2160A QorIQ Development System (QDS)
@@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2162AQDS platform.
The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
@@ -1302,6 +1367,7 @@ config TARGET_HIKEY
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SPECIFY_CONSOLE_INDEX
@@ -1315,6 +1381,7 @@ config TARGET_HIKEY960
select ARM64
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
@@ -1328,6 +1395,7 @@ config TARGET_POPLAR
select DM
select DM_SERIAL
select DM_USB
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
@@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1012AQDS platform.
The LS1012A Development System (QDS) is a high-performance
@@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1012A2G5RDB platform.
@@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM
select ARCH_LS1012A
select ARM64
select ARCH_SUPPORT_TFABOOT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1012AFRDM platform.
The LS1012A Freedom board (FRDM) is a high-performance
@@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
@@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
@@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
imply SCSI
@@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR
select LS1_DEEP_SLEEP
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
config TARGET_PG_WCOM_SELI8
@@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
+ select GPIO_EXTRA_HEADER
select VENDOR_KM
imply SCSI
help
@@ -1502,6 +1581,7 @@ config TARGET_LS1021ATSN
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
config TARGET_LS1021AIOT
@@ -1514,6 +1594,7 @@ config TARGET_LS1021AIOT
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1021AIOT platform.
@@ -1533,6 +1614,7 @@ config TARGET_LS1043AQDS
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1549,6 +1631,7 @@ config TARGET_LS1043ARDB
select SUPPORT_SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1043ARDB platform.
@@ -1565,6 +1648,7 @@ config TARGET_LS1046AQDS
select FSL_DDR_BIST if !SPL
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046AQDS platform.
@@ -1585,6 +1669,7 @@ config TARGET_LS1046ARDB
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046ARDB platform.
@@ -1601,6 +1686,7 @@ config TARGET_LS1046AFRWY
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046AFRWY platform.
@@ -1629,6 +1715,7 @@ config TARGET_SL28
select DM_SERIAL
select DM_SPI
select DM_USB
+ select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
@@ -1641,6 +1728,7 @@ config TARGET_SL28
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
+ select GPIO_EXTRA_HEADER
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
@@ -1677,6 +1765,7 @@ config ARCH_STM32
select CPU_V7M
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_STI
@@ -1702,6 +1791,7 @@ config ARCH_STM32MP
select DM_GPIO
select DM_RESET
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select MISC
select OF_CONTROL
select OF_LIBFDT
@@ -1764,6 +1854,7 @@ config ARCH_OCTEONTX
bool "Support OcteonTX SoCs"
select CLK
select DM
+ select GPIO_EXTRA_HEADER
select ARM64
select OF_CONTROL
select OF_LIVE
@@ -1774,6 +1865,7 @@ config ARCH_OCTEONTX2
bool "Support OcteonTX2 SoCs"
select CLK
select DM
+ select GPIO_EXTRA_HEADER
select ARM64
select OF_CONTROL
select OF_LIVE
@@ -1783,6 +1875,7 @@ config ARCH_OCTEONTX2
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SYS_CACHE_SHIFT_7
@@ -1796,6 +1889,7 @@ config ARCH_ASPEED
config TARGET_DURIAN
bool "Support Phytium Durian Platform"
select ARM64
+ select GPIO_EXTRA_HEADER
help
Support for durian platform.
It has 2GB Sdram, uart and pcie.
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 7609367884..650783ae73 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,10 +1,4 @@
-#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
- !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
- !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
- !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
- !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
- !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \
- !defined(CONFIG_ARCH_QEMU)
+#ifdef CONFIG_GPIO_EXTRA_HEADER
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 05/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (3 preceding siblings ...)
2021-06-04 9:43 ` [PATCH v5 04/13] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 06/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver Masami Hiramatsu
` (8 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Add ECAM based SynQuacer PCIe RC driver. This driver configures the
PCIe RC and filter out a ghost pcie config.
Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device
is configured by firmware (EDK2), it doesn't re-configure in the kernel.
So as same as EDK2, U-Boot needs to configure it before boot the kernel.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
drivers/pci/Kconfig | 12 +
drivers/pci/Makefile | 1
drivers/pci/pcie_ecam_synquacer.c | 600 +++++++++++++++++++++++++++++++++++++
3 files changed, 613 insertions(+)
create mode 100644 drivers/pci/pcie_ecam_synquacer.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b2b7b253f8..782179eb0f 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
+config PCIE_ECAM_SYNQUACER
+ bool "SynQuacer ECAM-based PCI host controller support"
+ default n
+ depends on DM_PCI
+ select PCI_INIT_R
+ select PCI_REGION_MULTI_ENTRY
+ help
+ Say Y here if you want to enable support for Socionext
+ SynQuacer SoC's ECAM-based PCIe host controllers.
+ Note that this must be configured when boot because Linux driver
+ expects the PCIe RC has been configured in the bootloader.
+
config PCI_PHYTIUM
bool "Phytium PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c742bb2c94..6568dc9a08 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -16,6 +16,7 @@ endif
obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
+obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c
new file mode 100644
index 0000000000..c6e7c59f8a
--- /dev/null
+++ b/drivers/pci/pcie_ecam_synquacer.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SynQuacer PCIE host driver
+ *
+ * Based on drivers/pci/pcie_ecam_generic.c
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ * Copyright (C) 2021 Linaro Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <log.h>
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+/* iATU registers */
+#define IATU_VIEWPORT_OFF 0x900
+#define IATU_VIEWPORT_INBOUND BIT(31)
+#define IATU_VIEWPORT_OUTBOUND 0
+#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7)
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT(12)
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31)
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT(28)
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
+
+/* Clock and resets */
+#define CORE_CONTROL 0x000
+#define APP_LTSSM_ENABLE BIT(4)
+#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0))
+
+#define AXI_CLK_STOP 0x004
+#define DBI_ACLK_STOP BIT(8)
+#define SLV_ACLK_STOP BIT(4)
+#define MSTR_ACLK_STOP BIT(0)
+#define DBI_CSYSREQ_REG BIT(9)
+#define SLV_CSYSREQ_REG BIT(5)
+#define MSTR_CSYSREQ_REG BIT(1)
+
+#define RESET_CONTROL_1 0x00C
+#define PERST_N_O_REG BIT(5)
+#define PERST_N_I_REG BIT(4)
+#define BUTTON_RST_N_REG BIT(1)
+#define PWUP_RST_N_REG BIT(0)
+
+#define RESET_CONTROL_2 0x010
+
+#define RESET_SELECT_1 0x014
+#define SQU_RST_SEL BIT(29)
+#define PHY_RST_SEL BIT(28)
+#define PWR_RST_SEL BIT(24)
+#define STI_RST_SEL BIT(20)
+#define N_STI_RST_SEL BIT(16)
+#define CORE_RST_SEL BIT(12)
+#define PERST_SEL BIT(4)
+#define BUTTON_RST_SEL BIT(1)
+#define PWUP_RST_SEL BIT(0)
+
+#define RESET_SELECT_2 0x018
+#define DBI_ARST_SEL BIT(8)
+#define SLV_ARST_SEL BIT(4)
+#define MSTR_ARST_SEL BIT(0)
+
+#define EM_CONTROL 0x030
+#define PRE_DET_STT_REG BIT(4)
+
+#define EM_SELECT 0x034
+#define PRE_DET_STT_SEL BIT(4)
+
+#define PM_CONTROL_2 0x050
+#define SYS_AUX_PWR_DET BIT(8)
+
+#define PHY_CONFIG_COM_6 0x114
+#define PIPE_PORT_SEL GENMASK(1, 0)
+
+#define LINK_MONITOR 0x210
+#define SMLH_LINK_UP BIT(0)
+
+#define LINK_CAPABILITIES_REG 0x07C
+#define PCIE_CAP_MAX_LINK_WIDTH GENMASK(7, 4)
+#define PCIE_CAP_MAX_LINK_SPEED GENMASK(3, 0)
+
+#define LINK_CONTROL_LINK_STATUS_REG 0x080
+#define PCIE_CAP_NEGO_LINK_WIDTH GENMASK(23, 20)
+#define PCIE_CAP_LINK_SPEED GENMASK(19, 16)
+
+#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
+#define BASE_CLASS_CODE 0xFF000000
+#define BASE_CLASS_CODE_VALUE 0x06
+#define SUBCLASS_CODE 0x00FF0000
+#define SUBCLASS_CODE_VALUE 0x04
+#define PROGRAM_INTERFACE 0x0000FF00
+#define PROGRAM_INTERFACE_VALUE 0x00
+
+#define GEN2_CONTROL_OFF 0x80c
+#define DIRECT_SPEED_CHANGE BIT(17)
+
+#define MISC_CONTROL_1_OFF 0x8BC
+#define DBI_RO_WR_EN BIT(0)
+
+static void or_writel(void *base, u32 offs, u32 val)
+{
+ writel(readl(base + offs) | val, base + offs);
+}
+
+static void masked_writel(void *base, u32 offs, u32 mask, u32 val)
+{
+ u32 data;
+ int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
+
+ if (val && shift > 1)
+ val <<= shift - 1;
+
+ if (mask != ~0)
+ data = (readl(base + offs) & ~mask) | val;
+ else
+ data = val;
+
+ writel(data, base + offs);
+}
+
+static u32 masked_readl(void *base, u32 offs, u32 mask)
+{
+ u32 data;
+ int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
+
+ data = readl(base + offs);
+
+ if (mask != ~0)
+ data &= mask;
+ if (shift > 1)
+ data >>= shift - 1;
+
+ return data;
+}
+
+/*
+ * Since SynQuacer's PCIe RC is expected to be initialized in the
+ * firmware (including U-Boot), devicetree doesn't have control
+ * blocks.
+ *
+ * Thus, this will initialize the PCIe RC with fixed addresses.
+ */
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
+#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
+#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
+
+#define SIZE_16KB 0x00004000
+#define SIZE_64KB 0x00010000
+#define SIZE_1MB 0x00100000
+
+#define SYNQUACER_PCI_DBI_SIZE SIZE_16KB
+#define SYNQUACER_PCI_EXS_SIZE SIZE_64KB
+
+#define NUM_SQ_PCI_RC 2
+
+static const struct synquacer_pcie_base {
+ phys_addr_t cfg_base;
+ phys_addr_t dbi_base;
+ phys_addr_t exs_base;
+} synquacer_pci_bases[NUM_SQ_PCI_RC] = {
+ {
+ .cfg_base = SYNQUACER_PCI_SEG0_CONFIG_BASE,
+ .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE,
+ .exs_base = SYNQUACER_PCI_SEG0_EXS_BASE,
+ }, {
+ .cfg_base = SYNQUACER_PCI_SEG1_CONFIG_BASE,
+ .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE,
+ .exs_base = SYNQUACER_PCI_SEG1_EXS_BASE,
+ },
+};
+
+/**
+ * struct synquacer_ecam_pcie - synquacer_ecam PCIe controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct synquacer_ecam_pcie {
+ void *cfg_base;
+ pci_size_t size;
+ void *dbi_base;
+ void *exs_base;
+ int first_busno;
+
+ struct pci_region mem;
+ struct pci_region io;
+ struct pci_region mem64;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * pci_synquacer_ecam_conf_address() - Calculate the address of a config access
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ */
+static int pci_synquacer_ecam_conf_address(const struct udevice *bus,
+ pci_dev_t bdf, uint offset,
+ void **paddress)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
+ void *addr;
+
+ addr = pcie->cfg_base;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
+ addr += PCI_DEV(bdf) << 15;
+ addr += PCI_FUNC(bdf) << 12;
+ addr += offset;
+ *paddress = addr;
+
+ return 0;
+}
+
+static bool pci_synquacer_ecam_addr_valid(const struct udevice *bus,
+ pci_dev_t bdf)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ /*
+ * The Synopsys DesignWare PCIe controller in ECAM mode will not filter
+ * type 0 config TLPs sent to devices 1 and up on its downstream port,
+ * resulting in devices appearing multiple times on bus 0 unless we
+ * filter out those accesses here.
+ */
+ if (PCI_BUS(bdf) == pcie->first_busno && PCI_DEV(bdf) > 0)
+ return false;
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
+/**
+ * pci_synquacer_ecam_read_config() - Read from configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ */
+static int pci_synquacer_ecam_read_config(const struct udevice *bus,
+ pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size)
+{
+ if (!pci_synquacer_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ return pci_generic_mmap_read_config(bus, pci_synquacer_ecam_conf_address,
+ bdf, offset, valuep, size);
+}
+
+/**
+ * pci_synquacer_ecam_write_config() - Write to configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ */
+static int pci_synquacer_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ if (!pci_synquacer_ecam_addr_valid(bus, bdf))
+ return 0;
+
+ return pci_generic_mmap_write_config(bus, pci_synquacer_ecam_conf_address,
+ bdf, offset, value, size);
+}
+
+/**
+ * pci_synquacer_ecam_of_to_plat() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pci_synquacer_ecam_of_to_plat(struct udevice *dev)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
+ struct fdt_resource reg_res;
+ int i, err;
+
+ debug("%s: called for %s\n", __func__, dev->name);
+
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
+ 0, ®_res);
+ if (err < 0) {
+ pr_err("\"reg\" resource not found\n");
+ return err;
+ }
+
+ /* Find the correct pair of the DBI/EXS base address */
+ for (i = 0; i < NUM_SQ_PCI_RC; i++) {
+ if (synquacer_pci_bases[i].cfg_base == reg_res.start)
+ break;
+ }
+ if (i == NUM_SQ_PCI_RC) {
+ pr_err("Unknown ECAM base address %lx.\n",
+ (unsigned long)reg_res.start);
+ return -ENOENT;
+ }
+ pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base,
+ SYNQUACER_PCI_DBI_SIZE, MAP_NOCACHE);
+ if (!pcie->dbi_base) {
+ pr_err("Failed to map DBI for %s\n", dev->name);
+ return -ENOMEM;
+ }
+
+ pcie->exs_base = map_physmem(synquacer_pci_bases[i].exs_base,
+ SYNQUACER_PCI_EXS_SIZE, MAP_NOCACHE);
+ if (!pcie->exs_base) {
+ pr_err("Failed to map EXS for %s\n", dev->name);
+ return -ENOMEM;
+ }
+
+ pcie->size = fdt_resource_size(®_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+ if (!pcie->cfg_base) {
+ pr_err("Failed to map config space for %s\n", dev->name);
+ return -ENOMEM;
+ }
+ debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base);
+
+ return 0;
+}
+
+static void pci_synquacer_pre_init(struct synquacer_ecam_pcie *pcie)
+{
+ void *base = pcie->exs_base;
+
+ masked_writel(base, EM_SELECT, PRE_DET_STT_SEL, 0);
+ masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 0);
+ masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 1);
+
+ /* 1: Assert all PHY / LINK resets */
+ masked_writel(base, RESET_SELECT_1, PERST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 0);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 0);
+
+ /* Device Reset(PERST#) is effective afrer Set device_type (RC) */
+ masked_writel(base, RESET_SELECT_1, PWUP_RST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
+ masked_writel(base, RESET_SELECT_1, BUTTON_RST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
+ masked_writel(base, RESET_SELECT_1, PWR_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, MSTR_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, SLV_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, DBI_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, CORE_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, STI_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, N_STI_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, SQU_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, PHY_RST_SEL, 1);
+
+ /* 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup. */
+ masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
+
+ /* 3: Set device_type (RC) */
+ masked_writel(base, CORE_CONTROL, DEVICE_TYPE, 4);
+}
+
+static void pci_synquacer_dbi_init(void *dbi_base)
+{
+ masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
+ /* 4 Lanes */
+ masked_writel(dbi_base, LINK_CAPABILITIES_REG,
+ PCIE_CAP_MAX_LINK_WIDTH, 4);
+ /* Gen 2 */
+ masked_writel(dbi_base, LINK_CAPABILITIES_REG,
+ PCIE_CAP_MAX_LINK_SPEED, 2);
+
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
+
+ masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
+}
+
+static void pcie_sq_prog_outbound_atu(void *dbi_base, int index,
+ u64 cpu_base, u64 pci_base, u64 size,
+ u32 type, u32 flags)
+{
+ debug("%s: %p, %d, %llx, %llx, %llx, %x, %x\n", __func__,
+ dbi_base, index, cpu_base, pci_base, size, type, flags);
+
+ writel(IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX(index),
+ dbi_base + IATU_VIEWPORT_OFF);
+
+ writel((u32)(cpu_base & 0xffffffff),
+ dbi_base + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(cpu_base >> 32),
+ dbi_base + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(cpu_base + size - 1),
+ dbi_base + IATU_LIMIT_ADDR_OFF_OUTBOUND_0);
+
+ writel((u32)(pci_base & 0xffffffff),
+ dbi_base + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(pci_base >> 32),
+ dbi_base + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0);
+
+ writel(type, dbi_base + IATU_REGION_CTRL_1_OFF_OUTBOUND_0);
+ writel(IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | flags,
+ dbi_base + IATU_REGION_CTRL_2_OFF_OUTBOUND_0);
+}
+
+static void pci_synquacer_post_init(struct synquacer_ecam_pcie *pcie)
+{
+ void *base = pcie->exs_base;
+
+ /*
+ * 4: Set Bifurcation 1=disable 4=able
+ * 5: Supply Reference (It has executed)
+ * 6: Wait for 10usec (Reference Clocks is stable)
+ * 7: De assert PERST#
+ */
+ masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 1);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 1);
+
+ /* 8: Assert SYS_AUX_PWR_DET */
+ masked_writel(base, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
+
+ /* 9: Supply following clocks */
+ masked_writel(base, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
+ masked_writel(base, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
+ masked_writel(base, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
+
+ /*
+ * 10: De assert PHY reset
+ * 11: De assert LINK's PMC reset
+ */
+ masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
+ masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
+
+ /* 12: PHY auto
+ * 13: Wrapper auto
+ * 14-17: PHY auto
+ * 18: Wrapper auto
+ * 19: Update registers through DBI AXI Slave interface
+ */
+ pci_synquacer_dbi_init(pcie->dbi_base);
+
+ or_writel(pcie->dbi_base, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Force link speed change to Gen2 at link up */
+ or_writel(pcie->dbi_base, GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+
+ /* Region 0: MMIO32 range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 0,
+ pcie->mem.phys_start,
+ pcie->mem.bus_start,
+ pcie->mem.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
+
+ /* Region 1: Type 0 config space */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 1,
+ (u64)pcie->cfg_base,
+ 0,
+ SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ /* Region 2: Type 1 config space */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 2,
+ (u64)pcie->cfg_base + SIZE_64KB,
+ 0,
+ (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ /* Region 3: port I/O range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 3,
+ pcie->io.phys_start,
+ pcie->io.bus_start,
+ pcie->io.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+ 0);
+
+ /* Region 4: MMIO64 range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 4,
+ pcie->mem64.phys_start,
+ pcie->mem64.bus_start,
+ pcie->mem64.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
+
+ /* enable link */
+ if (masked_readl(base, CORE_CONTROL, APP_LTSSM_ENABLE) == 0)
+ masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
+}
+
+static int pci_synquacer_ecam_probe(struct udevice *dev)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+
+ debug("Probe synquacer pcie for bus %d\n", dev_seq(dev));
+ pcie->first_busno = dev_seq(dev);
+
+ /* Store the IO and MEM windows settings for configuring ATU */
+ pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
+ pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
+ pcie->io.size = hose->regions[0].size; /* IO size */
+
+ pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+ pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
+ pcie->mem.size = hose->regions[1].size; /* MEM size */
+
+ pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */
+ pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */
+ pcie->mem64.size = hose->regions[2].size; /* MEM64 size */
+
+ pci_synquacer_pre_init(pcie);
+
+ mdelay(150);
+
+ pci_synquacer_post_init(pcie);
+
+ /* It takes a while to stabilize the PCIe bus for scanning */
+ mdelay(100);
+
+ return 0;
+}
+
+static const struct dm_pci_ops pci_synquacer_ecam_ops = {
+ .read_config = pci_synquacer_ecam_read_config,
+ .write_config = pci_synquacer_ecam_write_config,
+};
+
+static const struct udevice_id pci_synquacer_ecam_ids[] = {
+ { .compatible = "socionext,synquacer-pcie-ecam" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_synquacer_ecam) = {
+ .name = "pci_synquacer_ecam",
+ .id = UCLASS_PCI,
+ .of_match = pci_synquacer_ecam_ids,
+ .ops = &pci_synquacer_ecam_ops,
+ .probe = pci_synquacer_ecam_probe,
+ .of_to_plat = pci_synquacer_ecam_of_to_plat,
+ .priv_auto = sizeof(struct synquacer_ecam_pcie),
+};
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 06/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (4 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 05/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 07/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer Masami Hiramatsu
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
From: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---
Changes in v4:
- Add Jaehoon's reviewed-by.
Changes in v3:
- Rename config name to MMC_SDHCI_F_SDH30.
- Remove unneeded wait in drivers/mmc/sdhci.c.
- Rename probe function to f_sdh30_sdhci_probe.
---
drivers/mmc/Kconfig | 10 ++++++
drivers/mmc/Makefile | 1 +
drivers/mmc/f_sdh30.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+)
create mode 100644 drivers/mmc/f_sdh30.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8901456967..1c5aecfa5c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -561,6 +561,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config MMC_SDHCI_F_SDH30
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db3..f5fd59093e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 0000000000..3a85d9e348
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops = &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 07/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (5 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 06/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 08/13] net: synquacer: Add netsec driver Masami Hiramatsu
` (6 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
From: Jassi Brar <jaswinder.singh@linaro.org>
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1
drivers/spi/spi-synquacer.c | 491 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 500 insertions(+)
create mode 100644 drivers/spi/spi-synquacer.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..62d9676550 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -481,4 +481,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..98c95323d1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 0000000000..ce558c4bc0
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <time.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <spi.h>
+#include <wait_bit.h>
+
+#define MCTRL 0x0
+#define MEN 0
+#define CSEN 1
+#define IPCLK 3
+#define MES 4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM 3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN 8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF 0x14
+#define TXE 0x18
+#define TXC 0x1c
+#define RXF 0x20
+#define RXE 0x24
+#define RXC 0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART 0x38
+#define TRIGGER 0
+#define DMSTOP 8
+#define CS_MASK 3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX 1
+#define DATA_TX 2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG 0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT 0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT 4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID 0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
+
+static void write_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ const u8 *buf = priv->tx_buf;
+ int i;
+
+ len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
+ len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words);
+
+ for (i = 0; i < len; i++)
+ writeb(*buf++, priv->base + TXFIFO);
+
+ priv->tx_buf = buf;
+ priv->tx_words -= len;
+}
+
+static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
+{
+ u32 val;
+
+ val = readl(priv->base + DMSTART);
+ val &= ~(CS_MASK << CS_SHIFT);
+ val |= priv->cs << CS_SHIFT;
+
+ if (active) {
+ writel(val, priv->base + DMSTART);
+
+ val = readl(priv->base + DMSTART);
+ val &= ~BIT(DMSTOP);
+ writel(val, priv->base + DMSTART);
+ } else {
+ val |= BIT(DMSTOP);
+ writel(val, priv->base + DMSTART);
+
+ if (priv->rx_buf) {
+ u32 buf[16];
+
+ priv->rx_buf = buf;
+ priv->rx_words = 16;
+ read_fifo(priv);
+ }
+ }
+}
+
+static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
+{
+ struct udevice *bus = dev->parent;
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ u32 val, div, bus_width;
+ int rwflag;
+
+ rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
+
+ /* if nothing to do */
+ if (slave_plat->mode == priv->mode &&
+ rwflag == priv->rwflag &&
+ slave_plat->cs == priv->cs &&
+ slave_plat->max_hz == priv->speed)
+ return;
+
+ priv->rwflag = rwflag;
+ priv->cs = slave_plat->cs;
+ priv->mode = slave_plat->mode;
+ priv->speed = slave_plat->max_hz;
+
+ if (priv->mode & SPI_TX_BYTE)
+ bus_width = 1;
+ else if (priv->mode & SPI_TX_DUAL)
+ bus_width = 2;
+ else if (priv->mode & SPI_TX_QUAD)
+ bus_width = 4;
+ else if (priv->mode & SPI_TX_OCTAL)
+ bus_width = 8;
+
+ div = DIV_ROUND_UP(125000000, priv->speed);
+
+ val = readl(priv->base + PCC(priv->cs));
+ val &= ~BIT(RTM);
+ val &= ~BIT(ACES);
+ val &= ~BIT(SAFESYNC);
+ if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3)
+ val |= BIT(SAFESYNC);
+ if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6)
+ val |= BIT(SAFESYNC);
+
+ if (priv->mode & SPI_CPHA)
+ val |= BIT(CPHA);
+ else
+ val &= ~BIT(CPHA);
+
+ if (priv->mode & SPI_CPOL)
+ val |= BIT(CPOL);
+ else
+ val &= ~BIT(CPOL);
+
+ if (priv->mode & SPI_CS_HIGH)
+ val |= BIT(SSPOL);
+ else
+ val &= ~BIT(SSPOL);
+
+ if (priv->mode & SPI_LSB_FIRST)
+ val |= BIT(SDIR);
+ else
+ val &= ~BIT(SDIR);
+
+ if (priv->aces)
+ val |= BIT(ACES);
+
+ if (priv->rtm)
+ val |= BIT(RTM);
+
+ val |= (3 << SS2CD);
+ val |= BIT(SENDIAN);
+
+ val &= ~(CDRS_MASK << CDRS_SHIFT);
+ val |= ((div >> 1) << CDRS_SHIFT);
+
+ writel(val, priv->base + PCC(priv->cs));
+
+ val = readl(priv->base + FIFOCFG);
+ val &= ~(BPW_MASK << BPW_SHIFT);
+ val |= (0 << BPW_SHIFT);
+ writel(val, priv->base + FIFOCFG);
+
+ val = readl(priv->base + DMSTART);
+ val &= ~(DATA_MASK << DATA_SHIFT);
+
+ if (tx && rx)
+ val |= (DATA_TXRX << DATA_SHIFT);
+ else if (rx)
+ val |= (DATA_RX << DATA_SHIFT);
+ else
+ val |= (DATA_TX << DATA_SHIFT);
+
+ val &= ~(3 << BUS_WIDTH);
+ val |= ((bus_width >> 1) << BUS_WIDTH);
+ writel(val, priv->base + DMSTART);
+}
+
+static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *tx_buf, void *rx_buf,
+ unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+ u32 val, words, busy;
+
+ val = readl(priv->base + FIFOCFG);
+ val |= (1 << RX_FLUSH);
+ val |= (1 << TX_FLUSH);
+ writel(val, priv->base + FIFOCFG);
+
+ synquacer_spi_config(dev, rx_buf, tx_buf);
+
+ priv->tx_buf = tx_buf;
+ priv->rx_buf = rx_buf;
+
+ words = bitlen / 8;
+
+ if (tx_buf) {
+ busy |= BIT(TXBIT);
+ priv->tx_words = words;
+ } else {
+ busy &= ~BIT(TXBIT);
+ priv->tx_words = 0;
+ }
+
+ if (rx_buf) {
+ busy |= BIT(RXBIT);
+ priv->rx_words = words;
+ } else {
+ busy &= ~BIT(RXBIT);
+ priv->rx_words = 0;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ synquacer_cs_set(priv, true);
+
+ if (tx_buf)
+ write_fifo(priv);
+
+ if (rx_buf) {
+ val = readl(priv->base + FIFOCFG);
+ val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT);
+ val |= ((priv->rx_words > FIFO_DEPTH ?
+ RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT);
+ writel(val, priv->base + FIFOCFG);
+ }
+
+ writel(~0, priv->base + TXC);
+ writel(~0, priv->base + RXC);
+
+ /* Trigger */
+ val = readl(priv->base + DMSTART);
+ val |= BIT(TRIGGER);
+ writel(val, priv->base + DMSTART);
+
+ while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
+ if (priv->rx_words)
+ read_fifo(priv);
+ else
+ busy &= ~BIT(RXBIT);
+
+ if (priv->tx_words) {
+ write_fifo(priv);
+ } else {
+ u32 len;
+
+ do { /* wait for shifter to empty out */
+ cpu_relax();
+ len = readl(priv->base + DMSTATUS);
+ len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
+ } while (tx_buf && len);
+ busy &= ~BIT(TXBIT);
+ }
+ }
+
+ if (flags & SPI_XFER_END)
+ synquacer_cs_set(priv, false);
+
+ return 0;
+}
+
+static int synquacer_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int synquacer_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int synquacer_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int synquacer_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv)
+{
+ writel(0, priv->base + MCTRL);
+ while (readl(priv->base + MCTRL) & BIT(MES))
+ cpu_relax();
+}
+
+static void synquacer_spi_init(struct synquacer_spi_priv *priv)
+{
+ u32 val;
+
+ synquacer_spi_disable_module(priv);
+
+ writel(0, priv->base + TXE);
+ writel(0, priv->base + RXE);
+ val = readl(priv->base + TXF);
+ writel(val, priv->base + TXC);
+ val = readl(priv->base + RXF);
+ writel(val, priv->base + RXC);
+ val = readl(priv->base + FAULTF);
+ writel(val, priv->base + FAULTC);
+
+ val = readl(priv->base + DMCFG);
+ val &= ~BIT(SSDC);
+ val &= ~BIT(MSTARTEN);
+ writel(val, priv->base + DMCFG);
+
+ /* Enable module with direct mode */
+ val = readl(priv->base + MCTRL);
+ val &= ~BIT(IPCLK);
+ val &= ~BIT(CSEN);
+ val |= BIT(MEN);
+ val |= BIT(SYNCON);
+ writel(val, priv->base + MCTRL);
+}
+
+static void synquacer_spi_exit(struct synquacer_spi_priv *priv)
+{
+ u32 val;
+
+ synquacer_spi_disable_module(priv);
+
+ /* Enable module with command sequence mode */
+ val = readl(priv->base + MCTRL);
+ val &= ~BIT(IPCLK);
+ val |= BIT(CSEN);
+ val |= BIT(MEN);
+ val |= BIT(SYNCON);
+ writel(val, priv->base + MCTRL);
+
+ while (!(readl(priv->base + MCTRL) & BIT(MES)))
+ cpu_relax();
+}
+
+static int synquacer_spi_probe(struct udevice *bus)
+{
+ struct synquacer_spi_plat *plat = dev_get_plat(bus);
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+
+ priv->base = plat->base;
+ priv->aces = plat->aces;
+ priv->rtm = plat->rtm;
+
+ synquacer_spi_init(priv);
+ return 0;
+}
+
+static int synquacer_spi_remove(struct udevice *bus)
+{
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+
+ synquacer_spi_exit(priv);
+ return 0;
+}
+
+static int synquacer_spi_of_to_plat(struct udevice *bus)
+{
+ struct synquacer_spi_plat *plat = dev_get_plat(bus);
+ struct clk clk;
+
+ plat->base = dev_read_addr_ptr(bus);
+
+ plat->aces = dev_read_bool(bus, "socionext,set-aces");
+ plat->rtm = dev_read_bool(bus, "socionext,use-rtm");
+
+ clk_get_by_name(bus, "iHCLK", &clk);
+ clk_enable(&clk);
+
+ return 0;
+}
+
+static const struct dm_spi_ops synquacer_spi_ops = {
+ .claim_bus = synquacer_spi_claim_bus,
+ .release_bus = synquacer_spi_release_bus,
+ .xfer = synquacer_spi_xfer,
+ .set_speed = synquacer_spi_set_speed,
+ .set_mode = synquacer_spi_set_mode,
+};
+
+static const struct udevice_id synquacer_spi_ids[] = {
+ { .compatible = "socionext,synquacer-spi" },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(synquacer_spi) = {
+ .name = "synquacer_spi",
+ .id = UCLASS_SPI,
+ .of_match = synquacer_spi_ids,
+ .ops = &synquacer_spi_ops,
+ .of_to_plat = synquacer_spi_of_to_plat,
+ .plat_auto = sizeof(struct synquacer_spi_plat),
+ .priv_auto = sizeof(struct synquacer_spi_priv),
+ .probe = synquacer_spi_probe,
+ .flags = DM_FLAG_OS_PREPARE,
+ .remove = synquacer_spi_remove,
+};
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 08/13] net: synquacer: Add netsec driver
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (6 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 07/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-12 18:32 ` Ramon Fried
2021-06-12 18:39 ` Ramon Fried
2021-06-04 9:44 ` [PATCH v5 09/13] i2c: synquacer: SNI Synquacer I2C controller Masami Hiramatsu
` (5 subsequent siblings)
13 siblings, 2 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
From: Jassi Brar <jaswinder.singh@linaro.org>
Add SynQuacer's NETSEC GbE controller driver.
Since this driver will load the firmware from SPI NOR flash,
this depends on CONFIG_SYNQUACER_SPI=y.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
drivers/net/Kconfig | 8
drivers/net/Makefile | 1
drivers/net/sni_netsec.c | 1134 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1143 insertions(+)
create mode 100644 drivers/net/sni_netsec.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 382639044b..9fc28b149d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -673,6 +673,14 @@ config SNI_AVE
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
+config SNI_NETSEC
+ bool "Socionext NETSEC Ethernet support"
+ depends on DM_ETH && SYNQUACER_SPI
+ select PHYLIB
+ help
+ This driver implements support for the Socionext SynQuacer NETSEC
+ ethernet controller, as found on the Socionext SynQuacer family.
+
source "drivers/net/mscc_eswitch/Kconfig"
config ETHER_ON_FEC1
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a44a7d3f56..d56baa65b2 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-y += qe/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
+obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/
diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c
new file mode 100644
index 0000000000..a9ebf6af9c
--- /dev/null
+++ b/drivers/net/sni_netsec.c
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * netsec.c - Socionext Synquacer Netsec driver
+ * Copyright 2021 Linaro Ltd.
+ */
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <log.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+#define NETSEC_REG_SOFT_RST 0x104
+#define NETSEC_REG_COM_INIT 0x120
+
+#define NETSEC_REG_TOP_STATUS 0x200
+#define NETSEC_IRQ_RX BIT(1)
+#define NETSEC_IRQ_TX BIT(0)
+
+#define NETSEC_REG_TOP_INTEN 0x204
+#define NETSEC_REG_INTEN_SET 0x234
+#define NETSEC_REG_INTEN_CLR 0x238
+
+#define NETSEC_REG_NRM_TX_STATUS 0x400
+#define NETSEC_REG_NRM_TX_INTEN 0x404
+#define NETSEC_REG_NRM_TX_INTEN_SET 0x428
+#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
+#define NRM_TX_ST_NTOWNR BIT(17)
+#define NRM_TX_ST_TR_ERR BIT(16)
+#define NRM_TX_ST_TXDONE BIT(15)
+#define NRM_TX_ST_TMREXP BIT(14)
+
+#define NETSEC_REG_NRM_RX_STATUS 0x440
+#define NETSEC_REG_NRM_RX_INTEN 0x444
+#define NETSEC_REG_NRM_RX_INTEN_SET 0x468
+#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
+#define NRM_RX_ST_RC_ERR BIT(16)
+#define NRM_RX_ST_PKTCNT BIT(15)
+#define NRM_RX_ST_TMREXP BIT(14)
+
+#define NETSEC_REG_PKT_CMD_BUF 0xd0
+
+#define NETSEC_REG_CLK_EN 0x100
+
+#define NETSEC_REG_PKT_CTRL 0x140
+
+#define NETSEC_REG_DMA_TMR_CTRL 0x20c
+#define NETSEC_REG_F_TAIKI_MC_VER 0x22c
+#define NETSEC_REG_F_TAIKI_VER 0x230
+#define NETSEC_REG_DMA_HM_CTRL 0x214
+#define NETSEC_REG_DMA_MH_CTRL 0x220
+#define NETSEC_REG_ADDR_DIS_CORE 0x218
+#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
+#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
+
+#define NETSEC_REG_NRM_TX_PKTCNT 0x410
+
+#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
+#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
+
+#define NETSEC_REG_NRM_TX_TMR 0x41c
+
+#define NETSEC_REG_NRM_RX_PKTCNT 0x454
+#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
+#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
+#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
+
+#define NETSEC_REG_NRM_RX_TMR 0x45c
+
+#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
+#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
+#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
+#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
+
+#define NETSEC_REG_NRM_TX_CONFIG 0x430
+#define NETSEC_REG_NRM_RX_CONFIG 0x470
+
+#define MAC_REG_STATUS 0x1024
+#define MAC_REG_DATA 0x11c0
+#define MAC_REG_CMD 0x11c4
+#define MAC_REG_FLOW_TH 0x11cc
+#define MAC_REG_INTF_SEL 0x11d4
+#define MAC_REG_DESC_INIT 0x11fc
+#define MAC_REG_DESC_SOFT_RST 0x1204
+#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
+
+#define GMAC_REG_MCR 0x0000
+#define GMAC_REG_MFFR 0x0004
+#define GMAC_REG_GAR 0x0010
+#define GMAC_REG_GDR 0x0014
+#define GMAC_REG_FCR 0x0018
+#define GMAC_REG_BMR 0x1000
+#define GMAC_REG_RDLAR 0x100c
+#define GMAC_REG_TDLAR 0x1010
+#define GMAC_REG_OMR 0x1018
+
+#define MHZ(n) ((n) * 1000 * 1000)
+
+#define NETSEC_TX_SHIFT_OWN_FIELD 31
+#define NETSEC_TX_SHIFT_LD_FIELD 30
+#define NETSEC_TX_SHIFT_DRID_FIELD 24
+#define NETSEC_TX_SHIFT_PT_FIELD 21
+#define NETSEC_TX_SHIFT_TDRID_FIELD 16
+#define NETSEC_TX_SHIFT_CC_FIELD 15
+#define NETSEC_TX_SHIFT_FS_FIELD 9
+#define NETSEC_TX_LAST 8
+#define NETSEC_TX_SHIFT_CO 7
+#define NETSEC_TX_SHIFT_SO 6
+#define NETSEC_TX_SHIFT_TRS_FIELD 4
+
+#define NETSEC_RX_PKT_OWN_FIELD 31
+#define NETSEC_RX_PKT_LD_FIELD 30
+#define NETSEC_RX_PKT_SDRID_FIELD 24
+#define NETSEC_RX_PKT_FR_FIELD 23
+#define NETSEC_RX_PKT_ER_FIELD 21
+#define NETSEC_RX_PKT_ERR_FIELD 16
+#define NETSEC_RX_PKT_TDRID_FIELD 12
+#define NETSEC_RX_PKT_FS_FIELD 9
+#define NETSEC_RX_PKT_LS_FIELD 8
+#define NETSEC_RX_PKT_CO_FIELD 6
+
+#define NETSEC_RX_PKT_ERR_MASK 3
+
+#define NETSEC_MAX_TX_PKT_LEN 1518
+#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
+
+#define NETSEC_RING_GMAC 15
+#define NETSEC_RING_MAX 2
+
+#define NETSEC_TCP_SEG_LEN_MAX 1460
+#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
+
+#define NETSEC_RX_CKSUM_NOTAVAIL 0
+#define NETSEC_RX_CKSUM_OK 1
+#define NETSEC_RX_CKSUM_NG 2
+
+#define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
+#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
+
+#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
+#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
+
+#define NETSEC_INT_PKTCNT_MAX 2047
+
+#define NETSEC_FLOW_START_TH_MAX 95
+#define NETSEC_FLOW_STOP_TH_MAX 95
+#define NETSEC_FLOW_PAUSE_TIME_MIN 5
+
+#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
+
+#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
+#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
+#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
+#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
+#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
+#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
+
+#define NETSEC_CLK_EN_REG_DOM_G BIT(5)
+#define NETSEC_CLK_EN_REG_DOM_C BIT(1)
+#define NETSEC_CLK_EN_REG_DOM_D BIT(0)
+
+#define NETSEC_COM_INIT_REG_DB BIT(2)
+#define NETSEC_COM_INIT_REG_CLS BIT(1)
+#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
+ NETSEC_COM_INIT_REG_DB)
+
+#define NETSEC_SOFT_RST_REG_RESET 0
+#define NETSEC_SOFT_RST_REG_RUN BIT(31)
+
+#define NETSEC_DMA_CTRL_REG_STOP 1
+#define MH_CTRL__MODE_TRANS BIT(20)
+
+#define NETSEC_GMAC_CMD_ST_READ 0
+#define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
+#define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
+
+#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
+#define NETSEC_GMAC_BMR_REG_RESET 0x00020181
+#define NETSEC_GMAC_BMR_REG_SWR 0x00000001
+
+#define NETSEC_GMAC_OMR_REG_ST BIT(13)
+#define NETSEC_GMAC_OMR_REG_SR BIT(1)
+
+#define NETSEC_GMAC_MCR_REG_IBN BIT(30)
+#define NETSEC_GMAC_MCR_REG_CST BIT(25)
+#define NETSEC_GMAC_MCR_REG_JE BIT(20)
+#define NETSEC_MCR_PS BIT(15)
+#define NETSEC_GMAC_MCR_REG_FES BIT(14)
+#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
+#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
+
+#define NETSEC_FCR_RFE BIT(2)
+#define NETSEC_FCR_TFE BIT(1)
+
+#define NETSEC_GMAC_GAR_REG_GW BIT(1)
+#define NETSEC_GMAC_GAR_REG_GB BIT(0)
+
+#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
+#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
+#define GMAC_REG_SHIFT_CR_GAR 2
+
+#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
+#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
+#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
+#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
+#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
+#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
+
+#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
+#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
+
+#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
+
+#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
+#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
+#define NETSEC_REG_DESC_TMR_MODE 4
+#define NETSEC_REG_DESC_ENDIAN 0
+
+#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
+#define NETSEC_MAC_DESC_INIT_REG_INIT 1
+
+#define NETSEC_EEPROM_MAC_ADDRESS 0x00
+#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
+#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
+#define NETSEC_EEPROM_HM_ME_SIZE 0x10
+#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
+#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
+#define NETSEC_EEPROM_MH_ME_SIZE 0x1C
+#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
+#define NETSEC_EEPROM_PKT_ME_SIZE 0x24
+
+#define DESC_SZ sizeof(struct netsec_de)
+
+#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
+
+#define EERPROM_MAP_OFFSET 0x8000000
+#define NOR_BLOCK 1024
+
+struct netsec_de { /* Netsec Descriptor layout */
+ u32 attr;
+ u32 data_buf_addr_up;
+ u32 data_buf_addr_lw;
+ u32 buf_len_info;
+};
+
+struct netsec_priv {
+ struct netsec_de rxde[PKTBUFSRX];
+ struct netsec_de txde[1];
+ u16 rxat;
+
+ phys_addr_t eeprom_base;
+ phys_addr_t ioaddr;
+
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+ u32 phy_addr, freq;
+ int phy_mode;
+ int max_speed;
+};
+
+struct netsec_tx_pkt_ctrl {
+ u16 tcp_seg_len;
+ bool tcp_seg_offload_flag;
+ bool cksum_offload_flag;
+};
+
+struct netsec_rx_pkt_info {
+ int rx_cksum_result;
+ int err_code;
+ bool err_flag;
+};
+
+static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
+{
+ writel(val, priv->ioaddr + reg_addr);
+}
+
+static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
+{
+ return readl(priv->ioaddr + reg_addr);
+}
+
+/************* MDIO BUS OPS FOLLOW *************/
+
+#define TIMEOUT_SPINS_MAC 1000
+#define TIMEOUT_SECONDARY_MS_MAC 100
+
+static u32 netsec_clk_type(u32 freq)
+{
+ if (freq < MHZ(35))
+ return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
+ if (freq < MHZ(60))
+ return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
+ if (freq < MHZ(100))
+ return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
+ if (freq < MHZ(150))
+ return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
+ if (freq < MHZ(250))
+ return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
+
+ return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
+}
+
+static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
+{
+ u32 timeout = TIMEOUT_SPINS_MAC;
+
+ while (--timeout && netsec_read_reg(priv, addr) & mask)
+ cpu_relax();
+ if (timeout)
+ return 0;
+
+ timeout = TIMEOUT_SECONDARY_MS_MAC;
+ while (--timeout && netsec_read_reg(priv, addr) & mask)
+ udelay(2000);
+
+ if (timeout)
+ return 0;
+
+ pr_err("%s: timeout\n", __func__);
+
+ return -ETIMEDOUT;
+}
+
+static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
+{
+ netsec_write_reg(priv, MAC_REG_DATA, value);
+ netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
+ return netsec_wait_while_busy(priv,
+ MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
+}
+
+static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
+{
+ int ret;
+
+ netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
+ ret = netsec_wait_while_busy(priv,
+ MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
+ if (ret)
+ return ret;
+
+ *read = netsec_read_reg(priv, MAC_REG_DATA);
+
+ return 0;
+}
+
+static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
+ u32 addr, u32 mask)
+{
+ u32 timeout = TIMEOUT_SPINS_MAC;
+ u32 data;
+ int ret;
+
+ do {
+ ret = netsec_get_mac_reg(priv, addr, &data);
+ if (ret)
+ break;
+ udelay(1);
+ } while (--timeout && (data & mask));
+
+ if (timeout)
+ return 0;
+
+ timeout = TIMEOUT_SECONDARY_MS_MAC;
+ do {
+ udelay(2000);
+
+ ret = netsec_get_mac_reg(priv, addr, &data);
+ if (ret)
+ break;
+ cpu_relax();
+ } while (--timeout && (data & mask));
+
+ if (timeout && !ret)
+ return 0;
+
+ return -ETIMEDOUT;
+}
+
+static void netsec_cache_invalidate(uintptr_t vaddr, int len)
+{
+ invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
+ roundup(vaddr + len, ARCH_DMA_MINALIGN));
+}
+
+static void netsec_cache_flush(uintptr_t vaddr, int len)
+{
+ flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
+ roundup(vaddr + len, ARCH_DMA_MINALIGN));
+}
+
+static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
+{
+ struct netsec_de *de = &priv->rxde[idx];
+ u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
+ (1 << NETSEC_RX_PKT_FS_FIELD) |
+ (1 << NETSEC_RX_PKT_LS_FIELD);
+
+ if (idx == PKTBUFSRX - 1)
+ attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
+
+ de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
+ de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
+ de->buf_len_info = PKTSIZE;
+ de->attr = attr;
+ dmb();
+ netsec_cache_flush((uintptr_t)de, sizeof(*de));
+}
+
+static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
+{
+ struct netsec_de *de = &priv->txde[0];
+ u32 attr;
+
+ attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
+ (1 << NETSEC_TX_SHIFT_PT_FIELD) |
+ (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
+ (1 << NETSEC_TX_SHIFT_FS_FIELD) |
+ (1 << NETSEC_TX_LAST) |
+ (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
+ (1 << NETSEC_TX_SHIFT_LD_FIELD);
+
+ de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
+ de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
+ de->buf_len_info = len;
+ de->attr = attr;
+ dmb();
+ netsec_cache_flush((uintptr_t)de, sizeof(*de));
+}
+
+static int netsec_get_phy_reg(struct netsec_priv *priv,
+ int phy_addr, int reg_addr)
+{
+ u32 data;
+ int ret;
+
+ if (phy_addr != 7)
+ return -EINVAL;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
+ phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
+ reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
+ (netsec_clk_type(priv->freq) <<
+ GMAC_REG_SHIFT_CR_GAR)))
+ return -ETIMEDOUT;
+
+ ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
+ NETSEC_GMAC_GAR_REG_GB);
+ if (ret)
+ return ret;
+
+ ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
+ if (ret)
+ return ret;
+
+ return data;
+}
+
+static int netsec_set_phy_reg(struct netsec_priv *priv,
+ int phy_addr, int reg_addr, u16 val)
+{
+ int ret;
+
+ if (phy_addr != 7)
+ return -EINVAL;
+ if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
+ phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
+ reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
+ NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
+ (netsec_clk_type(priv->freq) <<
+ GMAC_REG_SHIFT_CR_GAR)))
+ return -ETIMEDOUT;
+
+ ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
+ NETSEC_GMAC_GAR_REG_GB);
+
+ /* Developerbox implements RTL8211E PHY and there is
+ * a compatibility problem with F_GMAC4.
+ * RTL8211E expects MDC clock must be kept toggling for several
+ * clock cycle with MDIO high before entering the IDLE state.
+ * To meet this requirement, netsec driver needs to issue dummy
+ * read(e.g. read PHYID1(offset 0x2) register) right after write.
+ */
+ netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
+
+ return ret;
+}
+
+static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
+{
+ struct phy_device *phydev = priv->phydev;
+ u32 value = 0;
+
+ value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
+ NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
+
+ if (phydev->speed != SPEED_1000)
+ value |= NETSEC_MCR_PS;
+
+ if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
+ phydev->speed == SPEED_100)
+ value |= NETSEC_GMAC_MCR_REG_FES;
+
+ value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
+
+ if (phy_interface_is_rgmii(phydev))
+ value |= NETSEC_GMAC_MCR_REG_IBN;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int netsec_start_gmac(struct netsec_priv *priv)
+{
+ u32 value = 0;
+ int ret;
+
+ if (priv->max_speed != SPEED_1000)
+ value = (NETSEC_GMAC_MCR_REG_CST |
+ NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
+ NETSEC_GMAC_BMR_REG_RESET))
+ return -ETIMEDOUT;
+
+ /* Wait soft reset */
+ mdelay(5);
+
+ ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
+ if (ret)
+ return ret;
+
+ if (value & NETSEC_GMAC_BMR_REG_SWR)
+ return -EAGAIN;
+
+ netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
+ if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
+ return -ETIMEDOUT;
+
+ netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
+ if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
+ NETSEC_GMAC_BMR_REG_COMMON))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
+ NETSEC_GMAC_RDLAR_REG_COMMON))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
+ NETSEC_GMAC_TDLAR_REG_COMMON))
+ return -ETIMEDOUT;
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
+ return -ETIMEDOUT;
+
+ ret = netsec_mac_update_to_phy_state(priv);
+ if (ret)
+ return ret;
+
+ ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
+ if (ret)
+ return ret;
+
+ value |= NETSEC_GMAC_OMR_REG_SR;
+ value |= NETSEC_GMAC_OMR_REG_ST;
+
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
+
+ if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int netsec_stop_gmac(struct netsec_priv *priv)
+{
+ u32 value;
+ int ret;
+
+ ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
+ if (ret)
+ return ret;
+ value &= ~NETSEC_GMAC_OMR_REG_SR;
+ value &= ~NETSEC_GMAC_OMR_REG_ST;
+
+ /* disable all interrupts */
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
+
+ return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
+}
+
+static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
+{
+ struct udevice *new;
+ struct spi_flash *flash;
+
+ spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
+ flash = dev_get_uclass_priv(new);
+
+ spi_flash_read(flash, offset, len, buf);
+}
+
+static int netsec_read_rom_hwaddr(struct udevice *dev)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ char macp[NOR_BLOCK];
+
+ netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
+
+ pdata->enetaddr[0] = readb(macp + 3);
+ pdata->enetaddr[1] = readb(macp + 2);
+ pdata->enetaddr[2] = readb(macp + 1);
+ pdata->enetaddr[3] = readb(macp + 0);
+ pdata->enetaddr[4] = readb(macp + 7);
+ pdata->enetaddr[5] = readb(macp + 6);
+ return 0;
+}
+
+static int netsec_send(struct udevice *dev, void *packet, int length)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+ u32 val, tout;
+
+ val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
+ netsec_cache_flush((uintptr_t)packet, length);
+ netsec_set_tx_de(priv, packet, length);
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
+
+ val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
+
+ tout = 10000;
+ do {
+ val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
+ udelay(2);
+ } while (--tout && !val);
+
+ if (!tout) {
+ val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
+ pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+
+ netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
+
+ priv->rxat++;
+ if (priv->rxat == PKTBUFSRX)
+ priv->rxat = 0;
+
+ return 0;
+}
+
+static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+ int idx = priv->rxat;
+ uchar *ptr = net_rx_packets[idx];
+ struct netsec_de *de = &priv->rxde[idx];
+ int length = 0;
+
+ netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
+
+ if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
+ return -EAGAIN;
+
+ length = de->buf_len_info >> 16;
+
+ /* invalidate after DMA is done */
+ netsec_cache_invalidate((uintptr_t)ptr, length);
+ *packetp = ptr;
+
+ return length;
+}
+
+static int _netsec_get_phy_reg(struct mii_dev *bus,
+ int phy_addr, int devad, int reg_addr)
+{
+ return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
+}
+
+static int _netsec_set_phy_reg(struct mii_dev *bus,
+ int phy_addr, int devad, int reg_addr, u16 val)
+{
+ return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
+}
+
+static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = _netsec_get_phy_reg;
+ bus->write = _netsec_set_phy_reg;
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
+ bus->priv = priv;
+
+ return mdio_register(bus);
+}
+
+static int netsec_phy_init(struct netsec_priv *priv, void *dev)
+{
+ struct phy_device *phydev;
+ int ret;
+
+ phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->max_speed) {
+ ret = phy_set_supported(phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
+ u32 addr_h, u32 addr_l, u32 size)
+{
+ u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
+
+ while (size > 0) {
+ char buf[NOR_BLOCK];
+ u32 *ucode = (u32 *)buf;
+ u64 off;
+ int i;
+
+ off = base % NOR_BLOCK;
+ base -= off;
+ netsec_spi_read(buf, sizeof(buf), base);
+
+ for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
+ netsec_write_reg(priv, reg, ucode[i]);
+ base += NOR_BLOCK;
+ }
+
+ return 0;
+}
+
+static int netsec_netdev_load_microcode(struct netsec_priv *priv)
+{
+ u32 addr_h, addr_l, size;
+ char buf[NOR_BLOCK];
+ u32 *ucinfo = (u32 *)buf;
+ int err;
+
+ netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
+
+ addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
+ addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
+ size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
+
+ err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
+ addr_h, addr_l, size);
+ if (err)
+ return err;
+
+ addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
+ addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
+ size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
+
+ err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
+ addr_h, addr_l, size);
+ if (err)
+ return err;
+
+ addr_h = 0;
+ addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
+ size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
+
+ err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
+ addr_h, addr_l, size);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+void netsec_pre_init_microengine(struct netsec_priv *priv)
+{
+ u32 data;
+
+ /* Remove dormant settings */
+ data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
+ data &= ~BMCR_PDOWN;
+ data |= BMCR_ISOLATE;
+ netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+ mdelay(100);
+
+ /* Put phy in loopback mode to guarantee RXCLK input */
+ data |= BMCR_LOOPBACK;
+ netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+ mdelay(100);
+}
+
+void netsec_post_init_microengine(struct netsec_priv *priv)
+{
+ u32 data;
+
+ /* Get phy back to normal operation */
+ data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
+ data &= ~BMCR_LOOPBACK;
+ netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+ mdelay(100);
+
+ /* Apply software reset */
+ data |= BMCR_RESET;
+ netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+ mdelay(100);
+}
+
+static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
+{
+ u32 value;
+ int err;
+
+ netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
+
+ /* stop DMA engines */
+ if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
+ netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
+ NETSEC_DMA_CTRL_REG_STOP);
+ netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
+ NETSEC_DMA_CTRL_REG_STOP);
+
+ value = 100;
+ while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
+ NETSEC_DMA_CTRL_REG_STOP) {
+ udelay(1000);
+ if (--value == 0) {
+ pr_err("%s:%d timeout!\n", __func__, __LINE__);
+ break;
+ }
+ }
+
+ value = 100;
+ while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
+ NETSEC_DMA_CTRL_REG_STOP) {
+ udelay(1000);
+ if (--value == 0) {
+ pr_err("%s:%d timeout!\n", __func__, __LINE__);
+ break;
+ }
+ }
+ }
+
+ netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
+
+ netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
+ netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
+ netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
+
+ value = 100;
+ while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
+ udelay(1000);
+ if (--value == 0) {
+ pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
+ break;
+ }
+ }
+
+ /* MAC desc init */
+ netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
+ netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
+ /* set MAC_INTF_SEL */
+ netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
+
+ netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+ /* set desc_start addr */
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
+ upper_32_bits((dma_addr_t)priv->rxde));
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
+ lower_32_bits((dma_addr_t)priv->rxde));
+
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
+ upper_32_bits((dma_addr_t)priv->txde));
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
+ lower_32_bits((dma_addr_t)priv->txde));
+
+ /* set normal tx dring ring config */
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
+ 1 << NETSEC_REG_DESC_ENDIAN);
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
+ 1 << NETSEC_REG_DESC_ENDIAN);
+
+ if (load_ucode) {
+ err = netsec_netdev_load_microcode(priv);
+ if (err) {
+ pr_err("%s: failed to load microcode (%d)\n",
+ __func__, err);
+ return err;
+ }
+ }
+
+ /* set desc_start addr */
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
+ upper_32_bits((dma_addr_t)priv->rxde));
+ netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
+ lower_32_bits((dma_addr_t)priv->rxde));
+
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
+ upper_32_bits((dma_addr_t)priv->txde));
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
+ lower_32_bits((dma_addr_t)priv->txde));
+
+ netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+ /* start DMA engines */
+ netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
+
+ netsec_pre_init_microengine(priv);
+
+ netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
+
+ mdelay(100);
+
+ if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
+ NETSEC_TOP_IRQ_REG_ME_START)) {
+ pr_err("microengine start failed\n");
+ return -ENXIO;
+ }
+
+ netsec_post_init_microengine(priv);
+
+ /* clear microcode load end status */
+ netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
+ NETSEC_TOP_IRQ_REG_ME_START);
+
+ netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+ value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
+ value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
+ /* change to normal mode */
+ netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
+ netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
+
+ value = 100;
+ while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
+ NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
+ udelay(1000);
+ if (--value == 0) {
+ value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
+ pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
+ break;
+ }
+ }
+
+ /* clear any pending EMPTY/ERR irq status */
+ netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
+
+ /* Disable TX & RX intr */
+ netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
+
+ return 0;
+}
+
+static void netsec_stop(struct udevice *dev)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+
+ netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
+ netsec_stop_gmac(priv);
+ phy_shutdown(priv->phydev);
+ netsec_reset_hardware(priv, false);
+}
+
+static int netsec_start(struct udevice *dev)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+ int i;
+
+ phy_startup(priv->phydev);
+ netsec_start_gmac(priv);
+
+ priv->rxat = 0;
+ for (i = 0; i < PKTBUFSRX; i++)
+ netsec_set_rx_de(priv, i, net_rx_packets[i]);
+
+ return 0;
+}
+
+static int netsec_of_to_plat(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct netsec_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
+ const char *phy_mode;
+
+ pdata->iobase = dev_read_addr_index(dev, 0);
+ priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
+
+ pdata->phy_interface = -1;
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args))
+ priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
+ else
+ priv->phy_addr = 7;
+
+ pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+
+ priv->ioaddr = pdata->iobase;
+ priv->phy_mode = pdata->phy_interface;
+ priv->max_speed = pdata->max_speed;
+ priv->freq = 250000000UL;
+
+ return 0;
+}
+
+#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
+#define SMMU_SCR0_MTCFG (0x1 << 20)
+#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
+
+static int netsec_probe(struct udevice *dev)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
+ (phys_addr_t)0x52E00000);
+
+ netsec_reset_hardware(priv, true);
+
+ ret = netsec_mdiobus_init(priv, dev->name);
+ if (ret) {
+ pr_err("Failed to initialize mdiobus: %d\n", ret);
+ return ret;
+ }
+
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ ret = netsec_phy_init(priv, dev);
+ if (ret) {
+ pr_err("Failed to initialize phy: %d\n", ret);
+ goto out_mdiobus_release;
+ }
+
+ return 0;
+out_mdiobus_release:
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+ return ret;
+}
+
+static int netsec_remove(struct udevice *dev)
+{
+ struct netsec_priv *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ return 0;
+}
+
+static const struct eth_ops netsec_ops = {
+ .start = netsec_start,
+ .stop = netsec_stop,
+ .send = netsec_send,
+ .recv = netsec_recv,
+ .free_pkt = netsec_free_packet,
+ .read_rom_hwaddr = netsec_read_rom_hwaddr,
+};
+
+static const struct udevice_id netsec_ids[] = {
+ {
+ .compatible = "socionext,synquacer-netsec",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(ave) = {
+ .name = "synquacer_netsec",
+ .id = UCLASS_ETH,
+ .of_match = netsec_ids,
+ .probe = netsec_probe,
+ .remove = netsec_remove,
+ .of_to_plat = netsec_of_to_plat,
+ .ops = &netsec_ops,
+ .priv_auto = sizeof(struct netsec_priv),
+ .plat_auto = sizeof(struct eth_pdata),
+};
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 09/13] i2c: synquacer: SNI Synquacer I2C controller
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (7 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 08/13] net: synquacer: Add netsec driver Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox Masami Hiramatsu
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
From: Jassi Brar <jaswinder.singh@linaro.org>
Add driver for class of I2C controllers found on
Socionext Synquacer platform.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
drivers/i2c/Kconfig | 7 +
drivers/i2c/Makefile | 1
drivers/i2c/synquacer_i2c.c | 338 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 346 insertions(+)
create mode 100644 drivers/i2c/synquacer_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 57a4efb88e..ce0d796d09 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -455,6 +455,13 @@ config SYS_I2C_STM32F7
_ Optional clock stretching
_ Software reset
+config SYS_I2C_SYNQUACER
+ bool "Socionext SynQuacer I2C controller"
+ depends on ARCH_SYNQUACER && DM_I2C
+ help
+ Support for Socionext Synquacer I2C controller. This I2C controller
+ will be used for RTC and LS-connector on DeveloperBox.
+
config SYS_I2C_TEGRA
bool "NVIDIA Tegra internal I2C controller"
depends on ARCH_TEGRA
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 8c9f1fcd8b..06a1150f03 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
+obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c
new file mode 100644
index 0000000000..6672d9435e
--- /dev/null
+++ b/drivers/i2c/synquacer_i2c.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ */
+
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <clk.h>
+
+#define REG_BSR 0x0
+#define REG_BCR 0x4
+#define REG_CCR 0x8
+#define REG_ADR 0xc
+#define REG_DAR 0x10
+#define REG_CSR 0x14
+#define REG_FSR 0x18
+#define REG_BC2R 0x1c
+
+/* I2C register bit definitions */
+#define BSR_FBT BIT(0) // First Byte Transfer
+#define BSR_GCA BIT(1) // General Call Address
+#define BSR_AAS BIT(2) // Address as Slave
+#define BSR_TRX BIT(3) // Transfer/Receive
+#define BSR_LRB BIT(4) // Last Received Bit
+#define BSR_AL BIT(5) // Arbitration Lost
+#define BSR_RSC BIT(6) // Repeated Start Cond.
+#define BSR_BB BIT(7) // Bus Busy
+
+#define BCR_INT BIT(0) // Interrupt
+#define BCR_INTE BIT(1) // Interrupt Enable
+#define BCR_GCAA BIT(2) // Gen. Call Access Ack.
+#define BCR_ACK BIT(3) // Acknowledge
+#define BCR_MSS BIT(4) // Master Slave Select
+#define BCR_SCC BIT(5) // Start Condition Cont.
+#define BCR_BEIE BIT(6) // Bus Error Int Enable
+#define BCR_BER BIT(7) // Bus Error
+
+#define CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
+#define CCR_EN BIT(5) // Enable
+#define CCR_FM BIT(6) // Speed Mode Select
+
+#define CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
+
+#define BC2R_SCLL BIT(0) // SCL Low Drive
+#define BC2R_SDAL BIT(1) // SDA Low Drive
+#define BC2R_SCLS BIT(4) // SCL Status
+#define BC2R_SDAS BIT(5) // SDA Status
+
+/* PCLK frequency */
+#define BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
+
+#define I2C_CLK_DEF 62500000
+
+/* STANDARD MODE frequency */
+#define CLK_MASTER_STD(rate) \
+ DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2)
+/* FAST MODE frequency */
+#define CLK_MASTER_FAST(rate) \
+ DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3)
+
+/* (clkrate <= 18000000) */
+/* calculate the value of CS bits in CCR register on standard mode */
+#define CCR_CS_STD_MAX_18M(rate) \
+ ((CLK_MASTER_STD(rate) - 65) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on standard mode */
+#define CSR_CS_STD_MAX_18M(rate) 0x00
+
+/* calculate the value of CS bits in CCR register on fast mode */
+#define CCR_CS_FAST_MAX_18M(rate) \
+ ((CLK_MASTER_FAST(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on fast mode */
+#define CSR_CS_FAST_MAX_18M(rate) 0x00
+
+/* (clkrate > 18000000) */
+/* calculate the value of CS bits in CCR register on standard mode */
+#define CCR_CS_STD_MIN_18M(rate) \
+ ((CLK_MASTER_STD(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on standard mode */
+#define CSR_CS_STD_MIN_18M(rate) \
+ (((CLK_MASTER_STD(rate) - 1) >> 5) \
+ & CSR_CS_MASK)
+
+/* calculate the value of CS bits in CCR register on fast mode */
+#define CCR_CS_FAST_MIN_18M(rate) \
+ ((CLK_MASTER_FAST(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on fast mode */
+#define CSR_CS_FAST_MIN_18M(rate) \
+ (((CLK_MASTER_FAST(rate) - 1) >> 5) \
+ & CSR_CS_MASK)
+
+/* min I2C clock frequency 14M */
+#define MIN_CLK_RATE (14 * 1000000)
+/* max I2C clock frequency 200M */
+#define MAX_CLK_RATE (200 * 1000000)
+/* I2C clock frequency 18M */
+#define CLK_RATE_18M (18 * 1000000)
+
+#define SPEED_FM 400 // Fast Mode
+#define SPEED_SM 100 // Standard Mode
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_i2c {
+ void __iomem *base;
+ unsigned long pclkrate;
+ unsigned long speed_khz;
+};
+
+static int wait_irq(struct udevice *dev)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(dev);
+ int timeout = 500000;
+
+ do {
+ if (readb(i2c->base + REG_BCR) & BCR_INT)
+ return 0;
+ } while (timeout--);
+
+ pr_err("%s: timeout\n", __func__);
+ return -1;
+}
+
+static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c,
+ int addr, int read)
+{
+ u8 bsr, bcr;
+
+ writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR);
+
+ bsr = readb(i2c->base + REG_BSR);
+ bcr = readb(i2c->base + REG_BCR);
+
+ if ((bsr & BSR_BB) && !(bcr & BCR_MSS))
+ return -EBUSY;
+
+ if (bsr & BSR_BB) {
+ writeb(bcr | BCR_SCC, i2c->base + REG_BCR);
+ } else {
+ if (bcr & BCR_MSS)
+ return -EAGAIN;
+ /* Start Condition + Enable Interrupts */
+ writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR);
+ }
+
+ udelay(100);
+ return 0;
+}
+
+static int synquacer_i2c_xfer(struct udevice *bus,
+ struct i2c_msg *msg, int nmsgs)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+ u8 bsr, bcr;
+ int idx;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ synquacer_i2c_xfer_start(i2c, msg->addr, msg->flags & I2C_M_RD);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+
+ bsr = readb(i2c->base + REG_BSR);
+ if (bsr & BSR_LRB) {
+ debug("%s: No ack received\n", __func__);
+ return -EREMOTEIO;
+ }
+
+ idx = 0;
+ do {
+ bsr = readb(i2c->base + REG_BSR);
+ bcr = readb(i2c->base + REG_BCR);
+ if (bcr & BCR_BER) {
+ debug("%s: Bus error detected\n", __func__);
+ return -EREMOTEIO;
+ }
+ if ((bsr & BSR_AL) || !(bcr & BCR_MSS)) {
+ debug("%s: Arbitration lost\n", __func__);
+ return -EREMOTEIO;
+ }
+
+ if (msg->flags & I2C_M_RD) {
+ bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
+ if (idx < msg->len - 1)
+ bcr |= BCR_ACK;
+ writeb(bcr, i2c->base + REG_BCR);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+ bsr = readb(i2c->base + REG_BSR);
+ if (!(bsr & BSR_FBT))
+ msg->buf[idx++] = readb(i2c->base + REG_DAR);
+ } else {
+ writeb(msg->buf[idx++], i2c->base + REG_DAR);
+ bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
+ writeb(bcr, i2c->base + REG_BCR);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+ bsr = readb(i2c->base + REG_BSR);
+ if (bsr & BSR_LRB) {
+ debug("%s: no ack\n", __func__);
+ return -EREMOTEIO;
+ }
+ }
+ } while (idx < msg->len);
+ }
+
+ /* Force bus state to idle, terminating any ongoing transfer */
+ writeb(0, i2c->base + REG_BCR);
+ udelay(100);
+
+ return 0;
+}
+
+static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
+{
+ /* Disable clock */
+ writeb(0, i2c->base + REG_CCR);
+ writeb(0, i2c->base + REG_CSR);
+
+ /* Set own Address */
+ writeb(0, i2c->base + REG_ADR);
+
+ /* Set PCLK frequency */
+ writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
+
+ /* clear IRQ (INT=0, BER=0), Interrupt Disable */
+ writeb(0, i2c->base + REG_BCR);
+ writeb(0, i2c->base + REG_BC2R);
+}
+
+static int synquacer_i2c_get_bus_speed(struct udevice *bus)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+
+ return i2c->speed_khz * 1000;
+}
+
+static int synquacer_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+ u32 rt = i2c->pclkrate;
+ u8 ccr_cs, csr_cs;
+
+ /* Set PCLK frequency */
+ writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
+
+ if (speed >= SPEED_FM * 1000) {
+ i2c->speed_khz = SPEED_FM;
+ if (i2c->pclkrate <= CLK_RATE_18M) {
+ ccr_cs = CCR_CS_FAST_MAX_18M(rt);
+ csr_cs = CSR_CS_FAST_MAX_18M(rt);
+ } else {
+ ccr_cs = CCR_CS_FAST_MIN_18M(rt);
+ csr_cs = CSR_CS_FAST_MIN_18M(rt);
+ }
+
+ /* Set Clock and enable, Set fast mode */
+ writeb(ccr_cs | CCR_FM | CCR_EN, i2c->base + REG_CCR);
+ writeb(csr_cs, i2c->base + REG_CSR);
+ } else {
+ i2c->speed_khz = SPEED_SM;
+ if (i2c->pclkrate <= CLK_RATE_18M) {
+ ccr_cs = CCR_CS_STD_MAX_18M(rt);
+ csr_cs = CSR_CS_STD_MAX_18M(rt);
+ } else {
+ ccr_cs = CCR_CS_STD_MIN_18M(rt);
+ csr_cs = CSR_CS_STD_MIN_18M(rt);
+ }
+
+ /* Set Clock and enable, Set standard mode */
+ writeb(ccr_cs | CCR_EN, i2c->base + REG_CCR);
+ writeb(csr_cs, i2c->base + REG_CSR);
+ }
+
+ return 0;
+}
+
+static int synquacer_i2c_of_to_plat(struct udevice *bus)
+{
+ struct synquacer_i2c *priv = dev_get_priv(bus);
+ struct clk ck;
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &ck);
+ if (ret < 0) {
+ priv->pclkrate = I2C_CLK_DEF;
+ } else {
+ clk_enable(&ck);
+ priv->pclkrate = clk_get_rate(&ck);
+ }
+
+ return 0;
+}
+
+static int synquacer_i2c_probe(struct udevice *bus)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+
+ i2c->base = dev_read_addr_ptr(bus);
+ synquacer_i2c_hw_reset(i2c);
+ synquacer_i2c_set_bus_speed(bus, 400000); /* set default speed */
+ return 0;
+}
+
+static const struct dm_i2c_ops synquacer_i2c_ops = {
+ .xfer = synquacer_i2c_xfer,
+ .set_bus_speed = synquacer_i2c_set_bus_speed,
+ .get_bus_speed = synquacer_i2c_get_bus_speed,
+};
+
+static const struct udevice_id synquacer_i2c_ids[] = {
+ {
+ .compatible = "socionext,synquacer-i2c",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(sni_synquacer_i2c) = {
+ .name = "sni_synquacer_i2c",
+ .id = UCLASS_I2C,
+ .of_match = synquacer_i2c_ids,
+ .of_to_plat = synquacer_i2c_of_to_plat,
+ .probe = synquacer_i2c_probe,
+ .priv_auto = sizeof(struct synquacer_i2c),
+ .ops = &synquacer_i2c_ops,
+};
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (8 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 09/13] i2c: synquacer: SNI Synquacer I2C controller Masami Hiramatsu
@ 2021-06-04 9:44 ` Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 11/13] board: synquacer: Add DeveloperBox 96boards EE support Masami Hiramatsu
` (3 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:44 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
Changes in v4:
- Add i2c0 and RTC node.
Changes in v3:
- Use generic nor flash instead of specific mx25u51245g.
(chip parameters will be searched by the register value)
Changes in v2:
- Add reference commit id of original EDK2 to the comment
- Just copy the EDK2 dts files as-is (change #include path)
- Split out the u-boot specific changes in -u-boot.dtsi.
- Removed unneeded spi-nor flash partition information.
---
arch/arm/dts/Makefile | 2
arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +++
arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++
arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++++++++++++++++++++
5 files changed, 801 insertions(+)
create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..167dbbc056 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1103,6 +1103,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 0000000000..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref { \
+ i-cache-size = <0x8000>; \
+ i-cache-line-size = <64>; \
+ i-cache-sets = <256>; \
+ d-cache-size = <0x8000>; \
+ d-cache-line-size = <64>; \
+ d-cache-sets = <128>; \
+ l2-cache = <l2ref>; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+ cache-size = <0x40000>; \
+ cache-line-size = <64>; \
+ cache-sets = <256>; \
+ cache-unified; \
+ next-level-cache = <&L3>; \
+};
+
+/ {
+ __L2(0)
+ __L2(1)
+ __L2(2)
+ __L2(3)
+ __L2(4)
+ __L2(5)
+ __L2(6)
+ __L2(7)
+ __L2(8)
+ __L2(9)
+ __L2(10)
+ __L2(11)
+
+ L3: l3-cache {
+ cache-level = <3>;
+ cache-size = <0x400000>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 0000000000..2f13a42235
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ i2c0 = &i2c0;
+ };
+
+ spi_nor: spi@54800000 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x54800000 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ active_clk_edges;
+ chipselect_num = <1>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <31250000>;
+ spi-rx-bus-width = <0x1>;
+ spi-tx-bus-width = <0x1>;
+ };
+ };
+
+ i2c0: i2c@51200000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x0 0x51200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_i2c>;
+ clock-names = "pclk";
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+
+ firmware {
+ optee {
+ status = "okay";
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&sdhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
new file mode 100644
index 0000000000..42b6cbbb82
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
@@ -0,0 +1,56 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/dts-v1/;
+
+#include "synquacer-sc2a11.dtsi"
+
+#define KEY_POWER 116
+
+/ {
+ model = "Socionext Developer Box";
+ compatible = "socionext,developer-box", "socionext,synquacer";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&exiu>;
+
+ power {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+ };
+};
+
+#ifdef TPM2_ENABLE
+&tpm {
+ status = "okay";
+};
+#endif
+
+&gpio {
+ gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
+ "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
+ "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
+ "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
+ "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
+ "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
+ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
+ "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
+};
+
+&netsec {
+ phy-mode = "rgmii-id";
+};
+
+&mdio_netsec {
+ phy_netsec: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi
new file mode 100644
index 0000000000..1fe7d214b9
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11.dtsi
@@ -0,0 +1,595 @@
+/** @file
+ * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/* These are added for U-Boot to avoid compilation error */
+#define PcdNetsecEepromBase 0x08080000
+#define FixedPcdGet32(n) n
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &soc_uart0;
+ serial1 = &fuart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU4: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU5: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x201>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU6: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU7: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x301>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU8: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU9: cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x401>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU10: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU11: cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x501>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU12: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU13: cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x601>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU14: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU15: cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x701>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU16: cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU17: cpu@801 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x801>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU18: cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU19: cpu@901 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x901>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU20: cpu@a00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU21: cpu@a01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU22: cpu@b00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU23: cpu@b01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+ core1 {
+ cpu = <&CPU5>;
+ };
+ };
+ cluster3 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+ cluster4 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+ core1 {
+ cpu = <&CPU9>;
+ };
+ };
+ cluster5 {
+ core0 {
+ cpu = <&CPU10>;
+ };
+ core1 {
+ cpu = <&CPU11>;
+ };
+ };
+ cluster6 {
+ core0 {
+ cpu = <&CPU12>;
+ };
+ core1 {
+ cpu = <&CPU13>;
+ };
+ };
+ cluster7 {
+ core0 {
+ cpu = <&CPU14>;
+ };
+ core1 {
+ cpu = <&CPU15>;
+ };
+ };
+ cluster8 {
+ core0 {
+ cpu = <&CPU16>;
+ };
+ core1 {
+ cpu = <&CPU17>;
+ };
+ };
+ cluster9 {
+ core0 {
+ cpu = <&CPU18>;
+ };
+ core1 {
+ cpu = <&CPU19>;
+ };
+ };
+ cluster10 {
+ core0 {
+ cpu = <&CPU20>;
+ };
+ core1 {
+ cpu = <&CPU21>;
+ };
+ };
+ cluster11 {
+ core0 {
+ cpu = <&CPU22>;
+ };
+ core1 {
+ cpu = <&CPU23>;
+ };
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2000>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2500>;
+ local-timer-stop;
+ };
+ };
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0x0 0x10000>, // GICD
+ <0x0 0x30400000 0x0 0x300000>, // GICR
+ <0x0 0x2c000000 0x0 0x2000>, // GICC
+ <0x0 0x2c010000 0x0 0x1000>, // GICH
+ <0x0 0x2c020000 0x0 0x10000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ its: gic-its@30020000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30020000 0x0 0x20000>;
+ #msi-cells = <1>;
+ msi-controller;
+ socionext,synquacer-pre-its = <0x58000000 0x200000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
+ };
+
+ mmio-timer@2a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x2a810000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ frame@2a830000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x2a830000 0x0 0x10000>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clk_uart: refclk62500khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ clock-output-names = "uartclk";
+ };
+
+ clk_apb: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_uart0: uart@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart>, <&clk_apb>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ fuart: uart@51040000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x51040000 0x0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart>, <&clk_apb>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ };
+
+ clk_netsec: refclk250mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
+ netsec: ethernet@522d0000 {
+ compatible = "socionext,synquacer-netsec";
+ reg = <0 0x522d0000 0x0 0x10000>,
+ <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_netsec>;
+ clock-names = "phy_ref_clk";
+ max-speed = <1000>;
+ max-frame-size = <9000>;
+ phy-handle = <&phy_netsec>;
+ dma-coherent;
+
+ mdio_netsec: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ smmu: iommu@582c0000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0x0 0x582c0000 0x0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie0: pcie@60000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x60000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
+ <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-map = <0x000 &its 0x0 0x7f00>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ pcie1: pcie@70000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x70000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
+ <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-map = <0x0 &its 0x10000 0x7f00>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ gpio: gpio@51000000 {
+ compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
+ reg = <0x0 0x51000000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clk_apb>;
+ base = <0>;
+ };
+
+ exiu: interrupt-controller@510c0000 {
+ compatible = "socionext,synquacer-exiu";
+ reg = <0x0 0x510c0000 0x0 0x20>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ socionext,spi-base = <112>;
+ };
+
+ clk_alw_b_0: bclk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "sd_bclk";
+ };
+
+ clk_alw_c_0: sd4clk800 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sd_sd4clk";
+ };
+
+ sdhci: sdhci@52300000 {
+ compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x52300000 0x0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ fujitsu,cmd-dat-delay-select;
+ clocks = <&clk_alw_c_0 &clk_alw_b_0>;
+ clock-names = "core", "iface";
+ dma-coherent;
+ status = "disabled";
+ };
+
+ clk_alw_1_8: spi_ihclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "iHCLK";
+ };
+
+ spi: spi@54810000 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x0 0x54810000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ clk_i2c: i2c_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ clock-output-names = "pclk";
+ };
+
+ i2c: i2c@51210000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x0 0x51210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_i2c>;
+ clock-names = "pclk";
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ tpm: tpm_tis@10000000 {
+ compatible = "socionext,synquacer-tpm-mmio";
+ reg = <0x0 0x10000000 0x0 0x5000>;
+ status = "disabled";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
+ };
+};
+
+#include "synquacer-sc2a11-caches.dtsi"
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 11/13] board: synquacer: Add DeveloperBox 96boards EE support
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (9 preceding siblings ...)
2021-06-04 9:44 ` [PATCH v5 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox Masami Hiramatsu
@ 2021-06-04 9:45 ` Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 12/13] doc: qemu: arm64: Fix the documentation of capsule update Masami Hiramatsu
` (2 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:45 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.
For more information, see this page;
https://www.96boards.org/product/developerbox/
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
Changes in v5:
- Remove log level from config.
Changes in v4:
- Add I2C and RTC configuration.
- Enable RTC and Date command.
- Remove I2C0 node before booting linux to hide it same as EDK2 does.
- Add some configurations to make it EBBR compliant.
Changes in v3:
- Enable CONFIG_MMC_SDHCI_F_SDH30.
- Enable CONFIG_CMD_GENERIC (fstype command) for distro boot.
- Remove unneeded CONFIG_ONLY_GENERIC_GPIO.
Changes in v2:
- Do not include arch/gpio.h and remove arch-sc2a11/gpio.h.
- Remove non-UEFI boot commands.
- Use Distro boot.
- Remove NOR-connected SPI node by path instead of alias.
- Rename configs/SynQuacer_defconfig to
configs/synquacer_developerbox_defconfig.
- Rename include/configs/SynQuacer.h to include/configs/synquacer.h.
- Move README under doc/board/socionext/ and make it .rst text.
---
arch/arm/Kconfig | 14 +++
board/socionext/developerbox/Kconfig | 36 +++++++
board/socionext/developerbox/MAINTAINERS | 14 +++
board/socionext/developerbox/Makefile | 9 ++
board/socionext/developerbox/developerbox.c | 146 +++++++++++++++++++++++++++
configs/synquacer_developerbox_defconfig | 112 +++++++++++++++++++++
doc/board/index.rst | 1
doc/board/socionext/developerbox.rst | 87 ++++++++++++++++
doc/board/socionext/index.rst | 9 ++
include/configs/synquacer.h | 109 ++++++++++++++++++++
10 files changed, 537 insertions(+)
create mode 100644 board/socionext/developerbox/Kconfig
create mode 100644 board/socionext/developerbox/MAINTAINERS
create mode 100644 board/socionext/developerbox/Makefile
create mode 100644 board/socionext/developerbox/developerbox.c
create mode 100644 configs/synquacer_developerbox_defconfig
create mode 100644 doc/board/socionext/developerbox.rst
create mode 100644 doc/board/socionext/index.rst
create mode 100644 include/configs/synquacer.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 023824df77..7ff24535cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1760,6 +1760,19 @@ config ARCH_UNIPHIER
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
+config ARCH_SYNQUACER
+ bool "Socionext SynQuacer SoCs"
+ select ARM64
+ select DM
+ select GIC_V3
+ select PSCI_RESET
+ select SYSRESET
+ select SYSRESET_PSCI
+ select OF_CONTROL
+ help
+ Support for SynQuacer SoC family developed by Socionext Inc.
+ This SoC is used on 96boards EE DeveloperBox.
+
config ARCH_STM32
bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
@@ -2102,6 +2115,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
+source "board/socionext/developerbox/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig
new file mode 100644
index 0000000000..706b8dc0f1
--- /dev/null
+++ b/board/socionext/developerbox/Kconfig
@@ -0,0 +1,36 @@
+if ARCH_SYNQUACER
+
+choice
+ prompt "SC2A11 Cortex-A53 MPCore 24cores"
+ optional
+
+config TARGET_DEVELOPERBOX
+ bool "Socionext DeveloperBox"
+ select PCI
+ select DM_PCI
+ select PCIE_ECAM_SYNQUACER
+ select SYS_DISABLE_DCACHE_OPS
+ select OF_BOARD_SETUP
+ help
+ Choose this option if you build the U-Boot for the DeveloperBox
+ 96boards Enterprise Edition.
+ This board will booted from SCP firmware and it enables SMMU, thus
+ the dcache is updated automatically when DMA operation is executed.
+endchoice
+
+config SYS_SOC
+ default "sc2a11"
+
+if TARGET_DEVELOPERBOX
+
+config SYS_BOARD
+ default "developerbox"
+
+config SYS_VENDOR
+ default "socionext"
+
+config SYS_CONFIG_NAME
+ default "synquacer"
+
+endif
+endif
diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS
new file mode 100644
index 0000000000..aa672b6e05
--- /dev/null
+++ b/board/socionext/developerbox/MAINTAINERS
@@ -0,0 +1,14 @@
+DEVELOPER BOX
+M: Masami Hiramatsu <masami.hiramatsu@linaro.org>
+M: Jassi Brar <jaswinder.singh@linaro.org>
+S: Maintained
+F: arch/arm/dts/synquacer-*
+F: board/socionext/developerbox/*
+F: configs/synquacer_developerbox_defconfig
+F: drivers/i2c/synquacer_i2c.c
+F: drivers/mmc/f_sdh30.c
+F: drivers/net/sni_netsec.c
+F: drivers/pci/pcie_ecam_synquacer.c
+F: drivers/spi/spi-synquacer.c
+F: include/configs/synquacer.h
+F: doc/board/socionext/developerbox.rst
diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile
new file mode 100644
index 0000000000..4a46de995a
--- /dev/null
+++ b/board/socionext/developerbox/Makefile
@@ -0,0 +1,9 @@
+#
+# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org>
+#
+# Copyright (C) 2021 Linaro Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := developerbox.o
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
new file mode 100644
index 0000000000..34335baec3
--- /dev/null
+++ b/board/socionext/developerbox/developerbox.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * u-boot/board/socionext/developerbox/developerbox.c
+ *
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Copyright (C) 2021 Linaro Ltd.
+ */
+#include <asm/types.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env_internal.h>
+#include <fdt_support.h>
+#include <log.h>
+
+static struct mm_region sc2a11_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* 1st DDR block */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = PHYS_SDRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* 2nd DDR place holder */
+ 0,
+ }, {
+ /* 3rd DDR place holder */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = sc2a11_mem_map;
+
+#define DDR_REGION_INDEX(i) (1 + (i))
+#define MAX_DDR_REGIONS 3
+
+struct draminfo_entry {
+ u64 base;
+ u64 size;
+};
+
+struct draminfo {
+ u32 nr_regions;
+ u32 reserved;
+ struct draminfo_entry entry[3];
+};
+
+struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->env_addr = (ulong)&default_environment[0];
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
+ fdt_del_node_and_alias(blob, "spi_nor");
+ fdt_del_node_and_alias(blob, "i2c0");
+
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+
+int dram_init(void)
+{
+ struct draminfo_entry *ent = synquacer_draminfo->entry;
+ struct mm_region *mr;
+ int i, ri;
+
+ if (synquacer_draminfo->nr_regions < 1) {
+ log_err("Failed to get correct DRAM information\n");
+ return -1;
+ }
+
+ /*
+ * U-Boot RAM size must be under the first DRAM region so that it doesn't
+ * access secure memory which is at the end of the first DRAM region.
+ */
+ gd->ram_size = ent[0].size;
+
+ /* Update memory region maps */
+ for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
+ if (i >= MAX_DDR_REGIONS)
+ break;
+
+ ri = DDR_REGION_INDEX(i);
+ mem_map[ri].phys = ent[i].base;
+ mem_map[ri].size = ent[i].size;
+ if (i == 0)
+ continue;
+
+ mr = &mem_map[DDR_REGION_INDEX(0)];
+ mem_map[ri].virt = mr->virt + mr->size;
+ mem_map[ri].attrs = mr->attrs;
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ struct draminfo_entry *ent = synquacer_draminfo->entry;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+ if (i < synquacer_draminfo->nr_regions) {
+ debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
+ gd->bd->bi_dram[i].start = ent[i].base;
+ gd->bd->bi_dram[i].size = ent[i].size;
+ }
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
+ return 0;
+}
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
new file mode 100644
index 0000000000..cbc09d3225
--- /dev/null
+++ b/configs/synquacer_developerbox_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_SYS_TEXT_BASE=0x08200000
+CONFIG_ENV_SIZE=0x30000
+CONFIG_ENV_OFFSET=0x300000
+CONFIG_DEBUG_UART_BASE=0x2a400000
+CONFIG_DEBUG_UART_CLOCK=62500000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_DEVELOPERBOX=y
+CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
+CONFIG_AHCI=y
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+CONFIG_BOOTM_EFI=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_NVEDIT_INFO=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_NVME=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)"
+CONFIG_MTDIDS_DEFAULT="nor1=nor1"
+CONFIG_CMD_LOG=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_LOADER=y
+CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
+CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
+CONFIG_EFI_UNICODE_CAPITALIZATION=y
+CONFIG_EFI_HAVE_RUNTIME_RESET=y
+CONFIG_EFI_GET_TIME=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_CMD_EFI_VARIABLE_FILE_STORE=Y
+CONFIG_OF_SEPARATE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_PROT_UDP=y
+CONFIG_BAUDRATE=115200
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SATA=y
+CONFIG_NVME=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_SYNQUACER=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=31250000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_SNI_NETSEC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYNQUACER_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_STORAGE=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index a70d2de19d..242372b321 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -21,6 +21,7 @@ Board-specific doc
rockchip/index
sifive/index
sipeed/index
+ socionext/index
st/index
tbs/index
toradex/index
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
new file mode 100644
index 0000000000..2d943c23be
--- /dev/null
+++ b/doc/board/socionext/developerbox.rst
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Introduction
+============
+
+DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: -
+
+* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard
+* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
+* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
+ (1x slots are connected via PCIe bridge chip)
+* 4 USB-3.0 ports
+* 2 SATA ports
+* 1 GbE network port
+* 1 USB-UART serial port (micro USB)
+* 64MB SPI NOR Flash
+* 8GB eMMC Flash Storage
+* 96boards LS connector
+
+The DeveloperBox schematic can be found here: -
+https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
+
+And the other documents can be found here: -
+https://www.96boards.org/documentation/enterprise/developerbox/
+
+
+Currently, the U-Boot port supports: -
+
+* USB
+* eMMC
+* SPI-NOR
+* SATA
+* GbE
+
+The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
+The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
+BL33, but no need to combine with it.
+
+Compile from source
+===================
+
+You can build U-Boot without any additinal source code.::
+
+ cd u-boot
+ export ARCH=arm64
+ export CROSS_COMPILE=aarch64-linux-gnu-
+ make SynQuacer_defconfig
+ make -j `noproc`
+
+Then, expand the binary to 1MB for preparing flash.::
+
+ cp u-boot.bin SPI_NOR_UBOOT.fd
+ truncate -s 1M SPI_NOR_UBOOT.fd
+
+Installation
+============
+
+You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
+
+Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port.
+Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing.
+
+*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail*
+
+https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html
+
+When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0::
+
+
+ /*------------------------------------------*/
+ /* SC2A11 "SynQuacer" series Flash writer */
+ /* */
+ /* Version: cd254ac */
+ /* Build: 12/15/17 11:25:45 */
+ /*------------------------------------------*/
+
+ Command Input >
+
+Once the flasher tool is running we are ready flash the UEFI image::
+
+ flash rawwrite 200000 100000
+ >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) <<
+
+*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).*
+
+After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board.
+
diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst
new file mode 100644
index 0000000000..4673dcc45b
--- /dev/null
+++ b/doc/board/socionext/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Socionext
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ developerbox
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
new file mode 100644
index 0000000000..0dab4de1f1
--- /dev/null
+++ b/include/configs/synquacer.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
+
+#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
+#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
+
+#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
+
+/*
+ * Boot info
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
+#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+/*
+ * Hardware drivers support
+ */
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/* Serial (pl011) */
+#define UART_CLK (62500000)
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK UART_CLK
+#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+/* Support MTD */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
+/* #define CONFIG_SYS_PCI_64BIT 1 */
+
+/* Distro boot settings */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICE_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICE_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_NVME
+#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
+#else
+#define BOOT_TARGET_DEVICE_NVME(func)
+#endif
+
+#ifdef CONFIG_CMD_SCSI
+#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
+#else
+#define BOOT_TARGET_DEVICE_SCSI(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICE_USB(func) \
+ BOOT_TARGET_DEVICE_MMC(func) \
+ BOOT_TARGET_DEVICE_SCSI(func) \
+ BOOT_TARGET_DEVICE_NVME(func) \
+
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r=0x9fe00000\0" \
+ "kernel_addr_r=0x90000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "scriptaddr=0x88000000\0" \
+ "pxefile_addr_r=0x88100000\0" \
+ BOOTENV
+
+#endif /* __CONFIG_H */
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 12/13] doc: qemu: arm64: Fix the documentation of capsule update
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (10 preceding siblings ...)
2021-06-04 9:45 ` [PATCH v5 11/13] board: synquacer: Add DeveloperBox 96boards EE support Masami Hiramatsu
@ 2021-06-04 9:45 ` Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 13/13] configs: synquacer: Enable EFI capsule update support Masami Hiramatsu
2021-06-11 7:25 ` [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:45 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Since the EDK2 GenerateCapsule script is out of date and it
doesn't generate the supported version capsule file, the document
should refer the mkeficapsule in tools.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
doc/board/emulation/qemu_capsule_update.rst | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst
index 33ce4bcd32..0a2286d039 100644
--- a/doc/board/emulation/qemu_capsule_update.rst
+++ b/doc/board/emulation/qemu_capsule_update.rst
@@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific)::
CONFIG_TFABOOT
-The capsule file can be generated by using the GenerateCapsule.py
-script in EDKII::
-
- $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
- <capsule_file_name> --fw-version <val> --lsv <val> --guid \
- e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \
- <val> --verbose <u-boot.bin>
+The capsule file can be generated by using the tools/mkeficapsule::
-The above is a wrapper script(GenerateCapsule) which eventually calls
-the actual GenerateCapsule.py script.
+ $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
As per the UEFI specification, the capsule file needs to be placed on
the EFI System Partition, under the \EFI\UpdateCapsule directory. The
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 13/13] configs: synquacer: Enable EFI capsule update support
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (11 preceding siblings ...)
2021-06-04 9:45 ` [PATCH v5 12/13] doc: qemu: arm64: Fix the documentation of capsule update Masami Hiramatsu
@ 2021-06-04 9:45 ` Masami Hiramatsu
2021-06-11 7:25 ` [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
13 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-04 9:45 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Masami Hiramatsu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Enable EFI capsule update support. With the EFI capsule update,
you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are
usually combined as a FIP binary, but if the binary is bigger
than 480KB, you have to modify FIP header, split the OP-TEE
and stores the OP-TEE binary in the different place. This
configuration supports both cases.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
Changes in v4:
- Add some config options for EBBR.
Changes in v3:
- Fix a typo in dfu_alt_info.
---
configs/synquacer_developerbox_defconfig | 17 +++++++++++++++++
include/configs/synquacer.h | 6 ++++++
2 files changed, 23 insertions(+)
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
index cbc09d3225..d42db9a1d6 100644
--- a/configs/synquacer_developerbox_defconfig
+++ b/configs/synquacer_developerbox_defconfig
@@ -110,3 +110,20 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_STORAGE=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
+CONFIG_EFI_CAPSULE_FIRMWARE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FMP_HEADER=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DFU_SF_PART=y
+CONFIG_FIT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_ERASEENV=y
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index 0dab4de1f1..8fe10d7485 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -61,6 +61,11 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
/* #define CONFIG_SYS_PCI_64BIT 1 */
+#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
+ "mtd nor1=u-boot.bin raw 200000 100000;" \
+ "fip.bin raw 180000 78000;" \
+ "optee.bin raw 500000 100000\0"
+
/* Distro boot settings */
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_USB
@@ -104,6 +109,7 @@
"ramdisk_addr_r=0xa0000000\0" \
"scriptaddr=0x88000000\0" \
"pxefile_addr_r=0x88100000\0" \
+ DEFAULT_DFU_ALT_INFO \
BOOTENV
#endif /* __CONFIG_H */
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
` (12 preceding siblings ...)
2021-06-04 9:45 ` [PATCH v5 13/13] configs: synquacer: Enable EFI capsule update support Masami Hiramatsu
@ 2021-06-11 7:25 ` Masami Hiramatsu
2021-06-11 8:05 ` Ilias Apalodimas
13 siblings, 1 reply; 20+ messages in thread
From: Masami Hiramatsu @ 2021-06-11 7:25 UTC (permalink / raw)
To: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu
Cc: Jassi Brar, Ilias Apalodimas, Masahisa Kojima, Takahiro Akashi,
Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
Hello,
Would anyone have any comments on this series?
Thank you,
2021年6月4日(金) 18:43 Masami Hiramatsu <masami.hiramatsu@linaro.org>:
>
> Hi,
>
> Here is the 5th version of the series (including some fixes for build
> errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot.
>
> This series includes not only DeveloperBox support but also some fixes
> for the issues which I faced while porting U-Boot on the DeveloperBox.
> First 3 patches are fixes, next 1 patch is a code cleanup for generic
> gpio for arm. The next 7 patches adding DeveloperBox devices
> and board support. The last 2 patches are related to the UEFI capsule
> update.
>
> Previous version is here:
>
> https://lists.denx.de/pipermail/u-boot/2021-May/449305.html
>
>
> Changes in v5
> -------------
>
> I dripped dfu_mtd bugfix patch (previous [12/14]) from this,
> because Sughosh already fixed it.
>
> [11/13]:
> - Remove log level from config.
>
>
> DeveloperBox
> ============
>
> DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: -
> * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard
> * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
> * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
> (1x slots are connected via PCIe bridge chip)
> * 4 USB-3.0 ports
> * 2 SATA ports
> * 1 GbE network port
> * 1 USB-UART serial port (micro USB)
> * 64MB SPI NOR Flash
> * 8GB eMMC Flash Storage
> * 96boards LS connector
>
> The DeveloperBox schematic can be found here: -
> https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
>
> And the other documents can be found here: -
> https://www.96boards.org/documentation/enterprise/developerbox/
>
>
> Currently, the U-Boot port supports: -
> * USB
> * eMMC
> * SPI-NOR
> * SATA
> * GbE
>
> The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
> The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
> BL33, but no need to combine with it.
>
>
> Thank you,
>
> ---
>
> Jassi Brar (4):
> mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
> spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
> net: synquacer: Add netsec driver
> i2c: synquacer: SNI Synquacer I2C controller
>
> Masami Hiramatsu (9):
> ata: ahci-pci: Use scsi_ops to initialize ops
> dm: pci: Skip setting VGA bridge bits if parent device is the host bus
> efi: Fix to use null handle to create new handle for efi_fmp_raw
> gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
> pci: synquacer: Add SynQuacer ECAM based PCIe driver
> ARM: dts: synquacer: Add device trees for DeveloperBox
> board: synquacer: Add DeveloperBox 96boards EE support
> doc: qemu: arm64: Fix the documentation of capsule update
> configs: synquacer: Enable EFI capsule update support
>
>
> arch/arm/Kconfig | 108 ++
> arch/arm/dts/Makefile | 2
> arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 +
> .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +
> arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 +
> arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++++++++++
> arch/arm/include/asm/gpio.h | 8
> board/socionext/developerbox/Kconfig | 36 +
> board/socionext/developerbox/MAINTAINERS | 14
> board/socionext/developerbox/Makefile | 9
> board/socionext/developerbox/developerbox.c | 146 +++
> configs/synquacer_developerbox_defconfig | 129 ++
> doc/board/emulation/qemu_capsule_update.rst | 11
> doc/board/index.rst | 1
> doc/board/socionext/developerbox.rst | 87 ++
> doc/board/socionext/index.rst | 9
> drivers/ata/ahci-pci.c | 2
> drivers/i2c/Kconfig | 7
> drivers/i2c/Makefile | 1
> drivers/i2c/synquacer_i2c.c | 338 ++++++
> drivers/mmc/Kconfig | 10
> drivers/mmc/Makefile | 1
> drivers/mmc/f_sdh30.c | 81 +
> drivers/net/Kconfig | 8
> drivers/net/Makefile | 1
> drivers/net/sni_netsec.c | 1134 ++++++++++++++++++++
> drivers/pci/Kconfig | 12
> drivers/pci/Makefile | 1
> drivers/pci/pci-uclass.c | 3
> drivers/pci/pcie_ecam_synquacer.c | 600 +++++++++++
> drivers/spi/Kconfig | 8
> drivers/spi/Makefile | 1
> drivers/spi/spi-synquacer.c | 491 +++++++++
> include/configs/synquacer.h | 115 ++
> lib/efi_loader/efi_capsule.c | 2
> 35 files changed, 4158 insertions(+), 17 deletions(-)
> create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
> create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
> create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
> create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
> create mode 100644 board/socionext/developerbox/Kconfig
> create mode 100644 board/socionext/developerbox/MAINTAINERS
> create mode 100644 board/socionext/developerbox/Makefile
> create mode 100644 board/socionext/developerbox/developerbox.c
> create mode 100644 configs/synquacer_developerbox_defconfig
> create mode 100644 doc/board/socionext/developerbox.rst
> create mode 100644 doc/board/socionext/index.rst
> create mode 100644 drivers/i2c/synquacer_i2c.c
> create mode 100644 drivers/mmc/f_sdh30.c
> create mode 100644 drivers/net/sni_netsec.c
> create mode 100644 drivers/pci/pcie_ecam_synquacer.c
> create mode 100644 drivers/spi/spi-synquacer.c
> create mode 100644 include/configs/synquacer.h
>
> --
> Masami Hiramatsu <masami.hiramatsu@linaro.org>
--
Masami Hiramatsu
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support
2021-06-11 7:25 ` [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
@ 2021-06-11 8:05 ` Ilias Apalodimas
0 siblings, 0 replies; 20+ messages in thread
From: Ilias Apalodimas @ 2021-06-11 8:05 UTC (permalink / raw)
To: Masami Hiramatsu
Cc: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Ramon Fried, Sughosh Ganu, Jassi Brar, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, U-Boot Mailing List,
Jaehoon Chung
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
On Fri, 11 Jun 2021 at 10:25, Masami Hiramatsu <masami.hiramatsu@linaro.org>
wrote:
> Hello,
>
> Would anyone have any comments on this series?
>
> Thank you,
>
> 2021年6月4日(金) 18:43 Masami Hiramatsu <masami.hiramatsu@linaro.org>:
> >
> > Hi,
> >
> > Here is the 5th version of the series (including some fixes for build
> > errors) to add SynQuacer/DeveloperBox 96board EE suport on U-Boot.
> >
> > This series includes not only DeveloperBox support but also some fixes
> > for the issues which I faced while porting U-Boot on the DeveloperBox.
> > First 3 patches are fixes, next 1 patch is a code cleanup for generic
> > gpio for arm. The next 7 patches adding DeveloperBox devices
> > and board support. The last 2 patches are related to the UEFI capsule
> > update.
> >
> > Previous version is here:
> >
> > https://lists.denx.de/pipermail/u-boot/2021-May/449305.html
> >
> >
> > Changes in v5
> > -------------
> >
> > I dripped dfu_mtd bugfix patch (previous [12/14]) from this,
> > because Sughosh already fixed it.
> >
> > [11/13]:
> > - Remove log level from config.
> >
> >
> > DeveloperBox
> > ============
> >
> > DeveloperBox is a certified 96boards Enterprise Edition board. The
> board/SoC has: -
> > * Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor
> motherboard
> > * 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
> > * 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
> > (1x slots are connected via PCIe bridge chip)
> > * 4 USB-3.0 ports
> > * 2 SATA ports
> > * 1 GbE network port
> > * 1 USB-UART serial port (micro USB)
> > * 64MB SPI NOR Flash
> > * 8GB eMMC Flash Storage
> > * 96boards LS connector
> >
> > The DeveloperBox schematic can be found here: -
> >
> https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
> >
> > And the other documents can be found here: -
> > https://www.96boards.org/documentation/enterprise/developerbox/
> >
> >
> > Currently, the U-Boot port supports: -
> > * USB
> > * eMMC
> > * SPI-NOR
> > * SATA
> > * GbE
> >
> > The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
> > The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
> > BL33, but no need to combine with it.
> >
> >
> > Thank you,
> >
> > ---
> >
> > Jassi Brar (4):
> > mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
> > spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
> > net: synquacer: Add netsec driver
> > i2c: synquacer: SNI Synquacer I2C controller
> >
> > Masami Hiramatsu (9):
> > ata: ahci-pci: Use scsi_ops to initialize ops
> > dm: pci: Skip setting VGA bridge bits if parent device is the host
> bus
> > efi: Fix to use null handle to create new handle for efi_fmp_raw
> > gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
> > pci: synquacer: Add SynQuacer ECAM based PCIe driver
> > ARM: dts: synquacer: Add device trees for DeveloperBox
> > board: synquacer: Add DeveloperBox 96boards EE support
> > doc: qemu: arm64: Fix the documentation of capsule update
> > configs: synquacer: Enable EFI capsule update support
> >
> >
> > arch/arm/Kconfig | 108 ++
> > arch/arm/dts/Makefile | 2
> > arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 +
> > .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +
> > arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 +
> > arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++++++++++
> > arch/arm/include/asm/gpio.h | 8
> > board/socionext/developerbox/Kconfig | 36 +
> > board/socionext/developerbox/MAINTAINERS | 14
> > board/socionext/developerbox/Makefile | 9
> > board/socionext/developerbox/developerbox.c | 146 +++
> > configs/synquacer_developerbox_defconfig | 129 ++
> > doc/board/emulation/qemu_capsule_update.rst | 11
> > doc/board/index.rst | 1
> > doc/board/socionext/developerbox.rst | 87 ++
> > doc/board/socionext/index.rst | 9
> > drivers/ata/ahci-pci.c | 2
> > drivers/i2c/Kconfig | 7
> > drivers/i2c/Makefile | 1
> > drivers/i2c/synquacer_i2c.c | 338 ++++++
> > drivers/mmc/Kconfig | 10
> > drivers/mmc/Makefile | 1
> > drivers/mmc/f_sdh30.c | 81 +
> > drivers/net/Kconfig | 8
> > drivers/net/Makefile | 1
> > drivers/net/sni_netsec.c | 1134
> ++++++++++++++++++++
> > drivers/pci/Kconfig | 12
> > drivers/pci/Makefile | 1
> > drivers/pci/pci-uclass.c | 3
> > drivers/pci/pcie_ecam_synquacer.c | 600 +++++++++++
> > drivers/spi/Kconfig | 8
> > drivers/spi/Makefile | 1
> > drivers/spi/spi-synquacer.c | 491 +++++++++
> > include/configs/synquacer.h | 115 ++
> > lib/efi_loader/efi_capsule.c | 2
> > 35 files changed, 4158 insertions(+), 17 deletions(-)
> > create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi
> > create mode 100644
> arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
> > create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts
> > create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi
> > create mode 100644 board/socionext/developerbox/Kconfig
> > create mode 100644 board/socionext/developerbox/MAINTAINERS
> > create mode 100644 board/socionext/developerbox/Makefile
> > create mode 100644 board/socionext/developerbox/developerbox.c
> > create mode 100644 configs/synquacer_developerbox_defconfig
> > create mode 100644 doc/board/socionext/developerbox.rst
> > create mode 100644 doc/board/socionext/index.rst
> > create mode 100644 drivers/i2c/synquacer_i2c.c
> > create mode 100644 drivers/mmc/f_sdh30.c
> > create mode 100644 drivers/net/sni_netsec.c
> > create mode 100644 drivers/pci/pcie_ecam_synquacer.c
> > create mode 100644 drivers/spi/spi-synquacer.c
> > create mode 100644 include/configs/synquacer.h
> >
> > --
> > Masami Hiramatsu <masami.hiramatsu@linaro.org>
>
>
>
> --
> Masami Hiramatsu
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 08/13] net: synquacer: Add netsec driver
2021-06-04 9:44 ` [PATCH v5 08/13] net: synquacer: Add netsec driver Masami Hiramatsu
@ 2021-06-12 18:32 ` Ramon Fried
2021-06-12 18:39 ` Ramon Fried
1 sibling, 0 replies; 20+ messages in thread
From: Ramon Fried @ 2021-06-12 18:32 UTC (permalink / raw)
To: Masami Hiramatsu
Cc: Peng Fan, Simon Glass, Tom Rini, Heinrich Schuchardt,
Alexander Graf, Jagan Teki, Vignesh R, Joe Hershberger,
Sughosh Ganu, Jassi Brar, Ilias Apalodimas, Masahisa Kojima,
Takahiro Akashi, Tim Harvey, Bin Meng, U-Boot Mailing List,
Jaehoon Chung
On Fri, Jun 4, 2021 at 12:44 PM Masami Hiramatsu
<masami.hiramatsu@linaro.org> wrote:
>
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add SynQuacer's NETSEC GbE controller driver.
> Since this driver will load the firmware from SPI NOR flash,
> this depends on CONFIG_SYNQUACER_SPI=y.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> ---
> drivers/net/Kconfig | 8
> drivers/net/Makefile | 1
> drivers/net/sni_netsec.c | 1134 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1143 insertions(+)
> create mode 100644 drivers/net/sni_netsec.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 382639044b..9fc28b149d 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -673,6 +673,14 @@ config SNI_AVE
> This driver implements support for the Socionext AVE Ethernet
> controller, as found on the Socionext UniPhier family.
>
> +config SNI_NETSEC
> + bool "Socionext NETSEC Ethernet support"
> + depends on DM_ETH && SYNQUACER_SPI
> + select PHYLIB
> + help
> + This driver implements support for the Socionext SynQuacer NETSEC
> + ethernet controller, as found on the Socionext SynQuacer family.
> +
> source "drivers/net/mscc_eswitch/Kconfig"
>
> config ETHER_ON_FEC1
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a44a7d3f56..d56baa65b2 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> obj-$(CONFIG_FSL_PFE) += pfe_eth/
> obj-y += qe/
> obj-$(CONFIG_SNI_AVE) += sni_ave.o
> +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
> obj-y += ti/
> obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
> obj-y += mscc_eswitch/
> diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c
> new file mode 100644
> index 0000000000..a9ebf6af9c
> --- /dev/null
> +++ b/drivers/net/sni_netsec.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/**
> + * netsec.c - Socionext Synquacer Netsec driver
> + * Copyright 2021 Linaro Ltd.
> + */
> +
> +#include <clk.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <fdt_support.h>
> +#include <log.h>
> +#include <malloc.h>
> +#include <miiphy.h>
> +#include <net.h>
> +#include <regmap.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/cache.h>
> +#include <asm/global_data.h>
> +#include <dm/device_compat.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <spi.h>
> +#include <spi_flash.h>
> +
> +#define NETSEC_REG_SOFT_RST 0x104
> +#define NETSEC_REG_COM_INIT 0x120
> +
> +#define NETSEC_REG_TOP_STATUS 0x200
> +#define NETSEC_IRQ_RX BIT(1)
> +#define NETSEC_IRQ_TX BIT(0)
> +
> +#define NETSEC_REG_TOP_INTEN 0x204
> +#define NETSEC_REG_INTEN_SET 0x234
> +#define NETSEC_REG_INTEN_CLR 0x238
> +
> +#define NETSEC_REG_NRM_TX_STATUS 0x400
> +#define NETSEC_REG_NRM_TX_INTEN 0x404
> +#define NETSEC_REG_NRM_TX_INTEN_SET 0x428
> +#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
> +#define NRM_TX_ST_NTOWNR BIT(17)
> +#define NRM_TX_ST_TR_ERR BIT(16)
> +#define NRM_TX_ST_TXDONE BIT(15)
> +#define NRM_TX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_NRM_RX_STATUS 0x440
> +#define NETSEC_REG_NRM_RX_INTEN 0x444
> +#define NETSEC_REG_NRM_RX_INTEN_SET 0x468
> +#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
> +#define NRM_RX_ST_RC_ERR BIT(16)
> +#define NRM_RX_ST_PKTCNT BIT(15)
> +#define NRM_RX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_PKT_CMD_BUF 0xd0
> +
> +#define NETSEC_REG_CLK_EN 0x100
> +
> +#define NETSEC_REG_PKT_CTRL 0x140
> +
> +#define NETSEC_REG_DMA_TMR_CTRL 0x20c
> +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c
> +#define NETSEC_REG_F_TAIKI_VER 0x230
> +#define NETSEC_REG_DMA_HM_CTRL 0x214
> +#define NETSEC_REG_DMA_MH_CTRL 0x220
> +#define NETSEC_REG_ADDR_DIS_CORE 0x218
> +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
> +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
> +
> +#define NETSEC_REG_NRM_TX_PKTCNT 0x410
> +
> +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
> +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
> +
> +#define NETSEC_REG_NRM_TX_TMR 0x41c
> +
> +#define NETSEC_REG_NRM_RX_PKTCNT 0x454
> +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
> +#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
> +#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
> +
> +#define NETSEC_REG_NRM_RX_TMR 0x45c
> +
> +#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
> +#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
> +#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
> +#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
> +
> +#define NETSEC_REG_NRM_TX_CONFIG 0x430
> +#define NETSEC_REG_NRM_RX_CONFIG 0x470
> +
> +#define MAC_REG_STATUS 0x1024
> +#define MAC_REG_DATA 0x11c0
> +#define MAC_REG_CMD 0x11c4
> +#define MAC_REG_FLOW_TH 0x11cc
> +#define MAC_REG_INTF_SEL 0x11d4
> +#define MAC_REG_DESC_INIT 0x11fc
> +#define MAC_REG_DESC_SOFT_RST 0x1204
> +#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
> +
> +#define GMAC_REG_MCR 0x0000
> +#define GMAC_REG_MFFR 0x0004
> +#define GMAC_REG_GAR 0x0010
> +#define GMAC_REG_GDR 0x0014
> +#define GMAC_REG_FCR 0x0018
> +#define GMAC_REG_BMR 0x1000
> +#define GMAC_REG_RDLAR 0x100c
> +#define GMAC_REG_TDLAR 0x1010
> +#define GMAC_REG_OMR 0x1018
> +
> +#define MHZ(n) ((n) * 1000 * 1000)
> +
> +#define NETSEC_TX_SHIFT_OWN_FIELD 31
> +#define NETSEC_TX_SHIFT_LD_FIELD 30
> +#define NETSEC_TX_SHIFT_DRID_FIELD 24
> +#define NETSEC_TX_SHIFT_PT_FIELD 21
> +#define NETSEC_TX_SHIFT_TDRID_FIELD 16
> +#define NETSEC_TX_SHIFT_CC_FIELD 15
> +#define NETSEC_TX_SHIFT_FS_FIELD 9
> +#define NETSEC_TX_LAST 8
> +#define NETSEC_TX_SHIFT_CO 7
> +#define NETSEC_TX_SHIFT_SO 6
> +#define NETSEC_TX_SHIFT_TRS_FIELD 4
> +
> +#define NETSEC_RX_PKT_OWN_FIELD 31
> +#define NETSEC_RX_PKT_LD_FIELD 30
> +#define NETSEC_RX_PKT_SDRID_FIELD 24
> +#define NETSEC_RX_PKT_FR_FIELD 23
> +#define NETSEC_RX_PKT_ER_FIELD 21
> +#define NETSEC_RX_PKT_ERR_FIELD 16
> +#define NETSEC_RX_PKT_TDRID_FIELD 12
> +#define NETSEC_RX_PKT_FS_FIELD 9
> +#define NETSEC_RX_PKT_LS_FIELD 8
> +#define NETSEC_RX_PKT_CO_FIELD 6
> +
> +#define NETSEC_RX_PKT_ERR_MASK 3
> +
> +#define NETSEC_MAX_TX_PKT_LEN 1518
> +#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
> +
> +#define NETSEC_RING_GMAC 15
> +#define NETSEC_RING_MAX 2
> +
> +#define NETSEC_TCP_SEG_LEN_MAX 1460
> +#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
> +
> +#define NETSEC_RX_CKSUM_NOTAVAIL 0
> +#define NETSEC_RX_CKSUM_OK 1
> +#define NETSEC_RX_CKSUM_NG 2
> +
> +#define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
> +#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
> +
> +#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
> +#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
> +
> +#define NETSEC_INT_PKTCNT_MAX 2047
> +
> +#define NETSEC_FLOW_START_TH_MAX 95
> +#define NETSEC_FLOW_STOP_TH_MAX 95
> +#define NETSEC_FLOW_PAUSE_TIME_MIN 5
> +
> +#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
> +
> +#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
> +#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
> +#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
> +#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
> +
> +#define NETSEC_CLK_EN_REG_DOM_G BIT(5)
> +#define NETSEC_CLK_EN_REG_DOM_C BIT(1)
> +#define NETSEC_CLK_EN_REG_DOM_D BIT(0)
> +
> +#define NETSEC_COM_INIT_REG_DB BIT(2)
> +#define NETSEC_COM_INIT_REG_CLS BIT(1)
> +#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
> + NETSEC_COM_INIT_REG_DB)
> +
> +#define NETSEC_SOFT_RST_REG_RESET 0
> +#define NETSEC_SOFT_RST_REG_RUN BIT(31)
> +
> +#define NETSEC_DMA_CTRL_REG_STOP 1
> +#define MH_CTRL__MODE_TRANS BIT(20)
> +
> +#define NETSEC_GMAC_CMD_ST_READ 0
> +#define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
> +#define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
> +
> +#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
> +#define NETSEC_GMAC_BMR_REG_RESET 0x00020181
> +#define NETSEC_GMAC_BMR_REG_SWR 0x00000001
> +
> +#define NETSEC_GMAC_OMR_REG_ST BIT(13)
> +#define NETSEC_GMAC_OMR_REG_SR BIT(1)
> +
> +#define NETSEC_GMAC_MCR_REG_IBN BIT(30)
> +#define NETSEC_GMAC_MCR_REG_CST BIT(25)
> +#define NETSEC_GMAC_MCR_REG_JE BIT(20)
> +#define NETSEC_MCR_PS BIT(15)
> +#define NETSEC_GMAC_MCR_REG_FES BIT(14)
> +#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
> +#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
> +
> +#define NETSEC_FCR_RFE BIT(2)
> +#define NETSEC_FCR_TFE BIT(1)
> +
> +#define NETSEC_GMAC_GAR_REG_GW BIT(1)
> +#define NETSEC_GMAC_GAR_REG_GB BIT(0)
> +
> +#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
> +#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
> +#define GMAC_REG_SHIFT_CR_GAR 2
> +
> +#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
> +#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
> +#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
> +#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
> +#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
> +#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
> +
> +#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
> +#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
> +
> +#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
> +
> +#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
> +#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
> +#define NETSEC_REG_DESC_TMR_MODE 4
> +#define NETSEC_REG_DESC_ENDIAN 0
> +
> +#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
> +#define NETSEC_MAC_DESC_INIT_REG_INIT 1
> +
> +#define NETSEC_EEPROM_MAC_ADDRESS 0x00
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
> +#define NETSEC_EEPROM_HM_ME_SIZE 0x10
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
> +#define NETSEC_EEPROM_MH_ME_SIZE 0x1C
> +#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
> +#define NETSEC_EEPROM_PKT_ME_SIZE 0x24
> +
> +#define DESC_SZ sizeof(struct netsec_de)
> +
> +#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
> +
> +#define EERPROM_MAP_OFFSET 0x8000000
> +#define NOR_BLOCK 1024
> +
> +struct netsec_de { /* Netsec Descriptor layout */
> + u32 attr;
> + u32 data_buf_addr_up;
> + u32 data_buf_addr_lw;
> + u32 buf_len_info;
> +};
> +
> +struct netsec_priv {
> + struct netsec_de rxde[PKTBUFSRX];
> + struct netsec_de txde[1];
> + u16 rxat;
> +
> + phys_addr_t eeprom_base;
> + phys_addr_t ioaddr;
> +
> + struct mii_dev *bus;
> + struct phy_device *phydev;
> + u32 phy_addr, freq;
> + int phy_mode;
> + int max_speed;
> +};
> +
> +struct netsec_tx_pkt_ctrl {
> + u16 tcp_seg_len;
> + bool tcp_seg_offload_flag;
> + bool cksum_offload_flag;
> +};
> +
> +struct netsec_rx_pkt_info {
> + int rx_cksum_result;
> + int err_code;
> + bool err_flag;
> +};
> +
> +static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
> +{
> + writel(val, priv->ioaddr + reg_addr);
> +}
> +
> +static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
> +{
> + return readl(priv->ioaddr + reg_addr);
> +}
> +
> +/************* MDIO BUS OPS FOLLOW *************/
> +
> +#define TIMEOUT_SPINS_MAC 1000
> +#define TIMEOUT_SECONDARY_MS_MAC 100
> +
> +static u32 netsec_clk_type(u32 freq)
> +{
> + if (freq < MHZ(35))
> + return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
> + if (freq < MHZ(60))
> + return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
> + if (freq < MHZ(100))
> + return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
> + if (freq < MHZ(150))
> + return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
> + if (freq < MHZ(250))
> + return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
> +
> + return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
> +}
> +
> +static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> +
> + while (--timeout && netsec_read_reg(priv, addr) & mask)
> + cpu_relax();
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + while (--timeout && netsec_read_reg(priv, addr) & mask)
> + udelay(2000);
> +
> + if (timeout)
> + return 0;
> +
> + pr_err("%s: timeout\n", __func__);
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
> +{
> + netsec_write_reg(priv, MAC_REG_DATA, value);
> + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
> + return netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> +}
> +
> +static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
> +{
> + int ret;
> +
> + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
> + ret = netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> + if (ret)
> + return ret;
> +
> + *read = netsec_read_reg(priv, MAC_REG_DATA);
> +
> + return 0;
> +}
> +
> +static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
> + u32 addr, u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> + u32 data;
> + int ret;
> +
> + do {
> + ret = netsec_get_mac_reg(priv, addr, &data);
> + if (ret)
> + break;
> + udelay(1);
> + } while (--timeout && (data & mask));
> +
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + do {
> + udelay(2000);
> +
> + ret = netsec_get_mac_reg(priv, addr, &data);
> + if (ret)
> + break;
> + cpu_relax();
> + } while (--timeout && (data & mask));
> +
> + if (timeout && !ret)
> + return 0;
> +
> + return -ETIMEDOUT;
> +}
> +
> +static void netsec_cache_invalidate(uintptr_t vaddr, int len)
> +{
> + invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
> + roundup(vaddr + len, ARCH_DMA_MINALIGN));
> +}
> +
> +static void netsec_cache_flush(uintptr_t vaddr, int len)
> +{
> + flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
> + roundup(vaddr + len, ARCH_DMA_MINALIGN));
> +}
> +
> +static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
> +{
> + struct netsec_de *de = &priv->rxde[idx];
> + u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
> + (1 << NETSEC_RX_PKT_FS_FIELD) |
> + (1 << NETSEC_RX_PKT_LS_FIELD);
> +
> + if (idx == PKTBUFSRX - 1)
> + attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
> + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
> + de->buf_len_info = PKTSIZE;
> + de->attr = attr;
> + dmb();
> + netsec_cache_flush((uintptr_t)de, sizeof(*de));
> +}
> +
> +static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
> +{
> + struct netsec_de *de = &priv->txde[0];
> + u32 attr;
> +
> + attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
> + (1 << NETSEC_TX_SHIFT_PT_FIELD) |
> + (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
> + (1 << NETSEC_TX_SHIFT_FS_FIELD) |
> + (1 << NETSEC_TX_LAST) |
> + (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
> + (1 << NETSEC_TX_SHIFT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
> + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
> + de->buf_len_info = len;
> + de->attr = attr;
> + dmb();
> + netsec_cache_flush((uintptr_t)de, sizeof(*de));
> +}
> +
> +static int netsec_get_phy_reg(struct netsec_priv *priv,
> + int phy_addr, int reg_addr)
> +{
> + u32 data;
> + int ret;
> +
> + if (phy_addr != 7)
> + return -EINVAL;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> + if (ret)
> + return ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
> + if (ret)
> + return ret;
> +
> + return data;
> +}
> +
> +static int netsec_set_phy_reg(struct netsec_priv *priv,
> + int phy_addr, int reg_addr, u16 val)
> +{
> + int ret;
> +
> + if (phy_addr != 7)
> + return -EINVAL;
> + if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> +
> + /* Developerbox implements RTL8211E PHY and there is
> + * a compatibility problem with F_GMAC4.
> + * RTL8211E expects MDC clock must be kept toggling for several
> + * clock cycle with MDIO high before entering the IDLE state.
> + * To meet this requirement, netsec driver needs to issue dummy
> + * read(e.g. read PHYID1(offset 0x2) register) right after write.
> + */
> + netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
> +
> + return ret;
> +}
> +
> +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
> +{
> + struct phy_device *phydev = priv->phydev;
> + u32 value = 0;
> +
> + value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
> +
> + if (phydev->speed != SPEED_1000)
> + value |= NETSEC_MCR_PS;
> +
> + if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
> + phydev->speed == SPEED_100)
> + value |= NETSEC_GMAC_MCR_REG_FES;
> +
> + value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
> +
> + if (phy_interface_is_rgmii(phydev))
> + value |= NETSEC_GMAC_MCR_REG_IBN;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_start_gmac(struct netsec_priv *priv)
> +{
> + u32 value = 0;
> + int ret;
> +
> + if (priv->max_speed != SPEED_1000)
> + value = (NETSEC_GMAC_MCR_REG_CST |
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_RESET))
> + return -ETIMEDOUT;
> +
> + /* Wait soft reset */
> + mdelay(5);
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
> + if (ret)
> + return ret;
> +
> + if (value & NETSEC_GMAC_BMR_REG_SWR)
> + return -EAGAIN;
> +
> + netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
> + return -ETIMEDOUT;
> +
> + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
> + NETSEC_GMAC_RDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
> + NETSEC_GMAC_TDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_update_to_phy_state(priv);
> + if (ret)
> + return ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> +
> + value |= NETSEC_GMAC_OMR_REG_SR;
> + value |= NETSEC_GMAC_OMR_REG_ST;
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_stop_gmac(struct netsec_priv *priv)
> +{
> + u32 value;
> + int ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> + value &= ~NETSEC_GMAC_OMR_REG_SR;
> + value &= ~NETSEC_GMAC_OMR_REG_ST;
> +
> + /* disable all interrupts */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
> +}
> +
> +static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
> +{
> + struct udevice *new;
> + struct spi_flash *flash;
> +
> + spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
> + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
> + flash = dev_get_uclass_priv(new);
> +
> + spi_flash_read(flash, offset, len, buf);
> +}
> +
> +static int netsec_read_rom_hwaddr(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + char macp[NOR_BLOCK];
> +
> + netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
> +
> + pdata->enetaddr[0] = readb(macp + 3);
> + pdata->enetaddr[1] = readb(macp + 2);
> + pdata->enetaddr[2] = readb(macp + 1);
> + pdata->enetaddr[3] = readb(macp + 0);
> + pdata->enetaddr[4] = readb(macp + 7);
> + pdata->enetaddr[5] = readb(macp + 6);
> + return 0;
> +}
> +
> +static int netsec_send(struct udevice *dev, void *packet, int length)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + u32 val, tout;
> +
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
> + netsec_cache_flush((uintptr_t)packet, length);
> + netsec_set_tx_de(priv, packet, length);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
> +
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
> +
> + tout = 10000;
> + do {
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
> + udelay(2);
> + } while (--tout && !val);
> +
> + if (!tout) {
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
> + pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
> +
> + priv->rxat++;
> + if (priv->rxat == PKTBUFSRX)
> + priv->rxat = 0;
> +
> + return 0;
> +}
> +
> +static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int idx = priv->rxat;
> + uchar *ptr = net_rx_packets[idx];
> + struct netsec_de *de = &priv->rxde[idx];
> + int length = 0;
> +
> + netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
> +
> + if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
> + return -EAGAIN;
> +
> + length = de->buf_len_info >> 16;
> +
> + /* invalidate after DMA is done */
> + netsec_cache_invalidate((uintptr_t)ptr, length);
> + *packetp = ptr;
> +
> + return length;
> +}
> +
> +static int _netsec_get_phy_reg(struct mii_dev *bus,
> + int phy_addr, int devad, int reg_addr)
> +{
> + return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
> +}
> +
> +static int _netsec_set_phy_reg(struct mii_dev *bus,
> + int phy_addr, int devad, int reg_addr, u16 val)
> +{
> + return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
> +}
> +
> +static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
> +{
> + struct mii_dev *bus = mdio_alloc();
> +
> + if (!bus)
> + return -ENOMEM;
> +
> + bus->read = _netsec_get_phy_reg;
> + bus->write = _netsec_set_phy_reg;
> + snprintf(bus->name, sizeof(bus->name), "%s", name);
> + bus->priv = priv;
> +
> + return mdio_register(bus);
> +}
> +
> +static int netsec_phy_init(struct netsec_priv *priv, void *dev)
> +{
> + struct phy_device *phydev;
> + int ret;
> +
> + phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
> +
> + phydev->supported &= PHY_GBIT_FEATURES;
> + if (priv->max_speed) {
> + ret = phy_set_supported(phydev, priv->max_speed);
> + if (ret)
> + return ret;
> + }
> + phydev->advertising = phydev->supported;
> +
> + priv->phydev = phydev;
> + phy_config(phydev);
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
> + u32 addr_h, u32 addr_l, u32 size)
> +{
> + u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
> +
> + while (size > 0) {
> + char buf[NOR_BLOCK];
> + u32 *ucode = (u32 *)buf;
> + u64 off;
> + int i;
> +
> + off = base % NOR_BLOCK;
> + base -= off;
> + netsec_spi_read(buf, sizeof(buf), base);
> +
> + for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
> + netsec_write_reg(priv, reg, ucode[i]);
> + base += NOR_BLOCK;
> + }
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_load_microcode(struct netsec_priv *priv)
> +{
> + u32 addr_h, addr_l, size;
> + char buf[NOR_BLOCK];
> + u32 *ucinfo = (u32 *)buf;
> + int err;
> +
> + netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
> +
> + addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
> + addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
> + size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
> + addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
> + size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + addr_h = 0;
> + addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
> + size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +void netsec_pre_init_microengine(struct netsec_priv *priv)
> +{
> + u32 data;
> +
> + /* Remove dormant settings */
> + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
> + data &= ~BMCR_PDOWN;
> + data |= BMCR_ISOLATE;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +
> + /* Put phy in loopback mode to guarantee RXCLK input */
> + data |= BMCR_LOOPBACK;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +}
> +
> +void netsec_post_init_microengine(struct netsec_priv *priv)
> +{
> + u32 data;
> +
> + /* Get phy back to normal operation */
> + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
> + data &= ~BMCR_LOOPBACK;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +
> + /* Apply software reset */
> + data |= BMCR_RESET;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +}
> +
> +static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
> +{
> + u32 value;
> + int err;
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
> +
> + /* stop DMA engines */
> + if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
> + netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> + }
> +
> + netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
> +
> + netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
> + netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
> + netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> +
> + /* MAC desc init */
> + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
> + netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
> + /* set MAC_INTF_SEL */
> + netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + /* set desc_start addr */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->rxde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->rxde));
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->txde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->txde));
> +
> + /* set normal tx dring ring config */
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> +
> + if (load_ucode) {
> + err = netsec_netdev_load_microcode(priv);
> + if (err) {
> + pr_err("%s: failed to load microcode (%d)\n",
> + __func__, err);
> + return err;
> + }
> + }
> +
> + /* set desc_start addr */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->rxde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->rxde));
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->txde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->txde));
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + /* start DMA engines */
> + netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
> +
> + netsec_pre_init_microengine(priv);
> +
> + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
> +
> + mdelay(100);
> +
> + if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
> + NETSEC_TOP_IRQ_REG_ME_START)) {
> + pr_err("microengine start failed\n");
> + return -ENXIO;
> + }
> +
> + netsec_post_init_microengine(priv);
> +
> + /* clear microcode load end status */
> + netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
> + NETSEC_TOP_IRQ_REG_ME_START);
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
> + value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
> + /* change to normal mode */
> + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
> + netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
> +
> + value = 100;
> + while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
> + NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
> + udelay(1000);
> + if (--value == 0) {
> + value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
> + pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
> + break;
> + }
> + }
> +
> + /* clear any pending EMPTY/ERR irq status */
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
> +
> + /* Disable TX & RX intr */
> + netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
> +
> + return 0;
> +}
> +
> +static void netsec_stop(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
> + netsec_stop_gmac(priv);
> + phy_shutdown(priv->phydev);
> + netsec_reset_hardware(priv, false);
> +}
> +
> +static int netsec_start(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int i;
> +
> + phy_startup(priv->phydev);
> + netsec_start_gmac(priv);
> +
> + priv->rxat = 0;
> + for (i = 0; i < PKTBUFSRX; i++)
> + netsec_set_rx_de(priv, i, net_rx_packets[i]);
> +
> + return 0;
> +}
> +
> +static int netsec_of_to_plat(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct netsec_priv *priv = dev_get_priv(dev);
> + struct ofnode_phandle_args phandle_args;
> + const char *phy_mode;
> +
> + pdata->iobase = dev_read_addr_index(dev, 0);
> + priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
> +
> + pdata->phy_interface = -1;
> + phy_mode = dev_read_prop(dev, "phy-mode", NULL);
> + if (phy_mode)
> + pdata->phy_interface = phy_get_interface_by_name(phy_mode);
> + if (pdata->phy_interface == -1) {
> + pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
> + return -EINVAL;
> + }
> +
> + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> + &phandle_args))
> + priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
> + else
> + priv->phy_addr = 7;
> +
> + pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
> +
> + priv->ioaddr = pdata->iobase;
> + priv->phy_mode = pdata->phy_interface;
> + priv->max_speed = pdata->max_speed;
> + priv->freq = 250000000UL;
> +
> + return 0;
> +}
> +
> +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
> +#define SMMU_SCR0_MTCFG (0x1 << 20)
> +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
> +
> +static int netsec_probe(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
> + (phys_addr_t)0x52E00000);
> +
> + netsec_reset_hardware(priv, true);
> +
> + ret = netsec_mdiobus_init(priv, dev->name);
> + if (ret) {
> + pr_err("Failed to initialize mdiobus: %d\n", ret);
> + return ret;
> + }
> +
> + priv->bus = miiphy_get_dev_by_name(dev->name);
> +
> + ret = netsec_phy_init(priv, dev);
> + if (ret) {
> + pr_err("Failed to initialize phy: %d\n", ret);
> + goto out_mdiobus_release;
> + }
> +
> + return 0;
> +out_mdiobus_release:
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> + return ret;
> +}
> +
> +static int netsec_remove(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + free(priv->phydev);
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> +
> + return 0;
> +}
> +
> +static const struct eth_ops netsec_ops = {
> + .start = netsec_start,
> + .stop = netsec_stop,
> + .send = netsec_send,
> + .recv = netsec_recv,
> + .free_pkt = netsec_free_packet,
> + .read_rom_hwaddr = netsec_read_rom_hwaddr,
> +};
> +
> +static const struct udevice_id netsec_ids[] = {
> + {
> + .compatible = "socionext,synquacer-netsec",
> + },
> + {}
> +};
> +
> +U_BOOT_DRIVER(ave) = {
> + .name = "synquacer_netsec",
> + .id = UCLASS_ETH,
> + .of_match = netsec_ids,
> + .probe = netsec_probe,
> + .remove = netsec_remove,
> + .of_to_plat = netsec_of_to_plat,
> + .ops = &netsec_ops,
> + .priv_auto = sizeof(struct netsec_priv),
> + .plat_auto = sizeof(struct eth_pdata),
> +};
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 08/13] net: synquacer: Add netsec driver
2021-06-04 9:44 ` [PATCH v5 08/13] net: synquacer: Add netsec driver Masami Hiramatsu
2021-06-12 18:32 ` Ramon Fried
@ 2021-06-12 18:39 ` Ramon Fried
1 sibling, 0 replies; 20+ messages in thread
From: Ramon Fried @ 2021-06-12 18:39 UTC (permalink / raw)
To: Masami Hiramatsu, Peng Fan, Simon Glass, Tom Rini,
Heinrich Schuchardt, Alexander Graf, Jagan Teki, Vignesh R,
Joe Hershberger, Sughosh Ganu
Cc: Jassi Brar, Ilias Apalodimas, Masahisa Kojima, Takahiro Akashi,
Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
On Fri Jun 4, 2021 at 12:44 PM IDT, Masami Hiramatsu wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add SynQuacer's NETSEC GbE controller driver.
> Since this driver will load the firmware from SPI NOR flash,
> this depends on CONFIG_SYNQUACER_SPI=y.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> ---
> drivers/net/Kconfig | 8
> drivers/net/Makefile | 1
> drivers/net/sni_netsec.c | 1134
> ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1143 insertions(+)
> create mode 100644 drivers/net/sni_netsec.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 382639044b..9fc28b149d 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -673,6 +673,14 @@ config SNI_AVE
> This driver implements support for the Socionext AVE Ethernet
> controller, as found on the Socionext UniPhier family.
>
> +config SNI_NETSEC
> + bool "Socionext NETSEC Ethernet support"
> + depends on DM_ETH && SYNQUACER_SPI
> + select PHYLIB
> + help
> + This driver implements support for the Socionext SynQuacer NETSEC
> + ethernet controller, as found on the Socionext SynQuacer family.
> +
> source "drivers/net/mscc_eswitch/Kconfig"
>
> config ETHER_ON_FEC1
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a44a7d3f56..d56baa65b2 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> obj-$(CONFIG_FSL_PFE) += pfe_eth/
> obj-y += qe/
> obj-$(CONFIG_SNI_AVE) += sni_ave.o
> +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
> obj-y += ti/
> obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
> obj-y += mscc_eswitch/
> diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c
> new file mode 100644
> index 0000000000..a9ebf6af9c
> --- /dev/null
> +++ b/drivers/net/sni_netsec.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/**
> + * netsec.c - Socionext Synquacer Netsec driver
> + * Copyright 2021 Linaro Ltd.
> + */
> +
> +#include <clk.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <fdt_support.h>
> +#include <log.h>
> +#include <malloc.h>
> +#include <miiphy.h>
> +#include <net.h>
> +#include <regmap.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/cache.h>
> +#include <asm/global_data.h>
> +#include <dm/device_compat.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <spi.h>
> +#include <spi_flash.h>
> +
> +#define NETSEC_REG_SOFT_RST 0x104
> +#define NETSEC_REG_COM_INIT 0x120
> +
> +#define NETSEC_REG_TOP_STATUS 0x200
> +#define NETSEC_IRQ_RX BIT(1)
> +#define NETSEC_IRQ_TX BIT(0)
> +
> +#define NETSEC_REG_TOP_INTEN 0x204
> +#define NETSEC_REG_INTEN_SET 0x234
> +#define NETSEC_REG_INTEN_CLR 0x238
> +
> +#define NETSEC_REG_NRM_TX_STATUS 0x400
> +#define NETSEC_REG_NRM_TX_INTEN 0x404
> +#define NETSEC_REG_NRM_TX_INTEN_SET 0x428
> +#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
> +#define NRM_TX_ST_NTOWNR BIT(17)
> +#define NRM_TX_ST_TR_ERR BIT(16)
> +#define NRM_TX_ST_TXDONE BIT(15)
> +#define NRM_TX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_NRM_RX_STATUS 0x440
> +#define NETSEC_REG_NRM_RX_INTEN 0x444
> +#define NETSEC_REG_NRM_RX_INTEN_SET 0x468
> +#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
> +#define NRM_RX_ST_RC_ERR BIT(16)
> +#define NRM_RX_ST_PKTCNT BIT(15)
> +#define NRM_RX_ST_TMREXP BIT(14)
> +
> +#define NETSEC_REG_PKT_CMD_BUF 0xd0
> +
> +#define NETSEC_REG_CLK_EN 0x100
> +
> +#define NETSEC_REG_PKT_CTRL 0x140
> +
> +#define NETSEC_REG_DMA_TMR_CTRL 0x20c
> +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c
> +#define NETSEC_REG_F_TAIKI_VER 0x230
> +#define NETSEC_REG_DMA_HM_CTRL 0x214
> +#define NETSEC_REG_DMA_MH_CTRL 0x220
> +#define NETSEC_REG_ADDR_DIS_CORE 0x218
> +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
> +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
> +
> +#define NETSEC_REG_NRM_TX_PKTCNT 0x410
> +
> +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
> +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
> +
> +#define NETSEC_REG_NRM_TX_TMR 0x41c
> +
> +#define NETSEC_REG_NRM_RX_PKTCNT 0x454
> +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
> +#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
> +#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
> +
> +#define NETSEC_REG_NRM_RX_TMR 0x45c
> +
> +#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
> +#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
> +#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
> +#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
> +
> +#define NETSEC_REG_NRM_TX_CONFIG 0x430
> +#define NETSEC_REG_NRM_RX_CONFIG 0x470
> +
> +#define MAC_REG_STATUS 0x1024
> +#define MAC_REG_DATA 0x11c0
> +#define MAC_REG_CMD 0x11c4
> +#define MAC_REG_FLOW_TH 0x11cc
> +#define MAC_REG_INTF_SEL 0x11d4
> +#define MAC_REG_DESC_INIT 0x11fc
> +#define MAC_REG_DESC_SOFT_RST 0x1204
> +#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
> +
> +#define GMAC_REG_MCR 0x0000
> +#define GMAC_REG_MFFR 0x0004
> +#define GMAC_REG_GAR 0x0010
> +#define GMAC_REG_GDR 0x0014
> +#define GMAC_REG_FCR 0x0018
> +#define GMAC_REG_BMR 0x1000
> +#define GMAC_REG_RDLAR 0x100c
> +#define GMAC_REG_TDLAR 0x1010
> +#define GMAC_REG_OMR 0x1018
> +
> +#define MHZ(n) ((n) * 1000 * 1000)
> +
> +#define NETSEC_TX_SHIFT_OWN_FIELD 31
> +#define NETSEC_TX_SHIFT_LD_FIELD 30
> +#define NETSEC_TX_SHIFT_DRID_FIELD 24
> +#define NETSEC_TX_SHIFT_PT_FIELD 21
> +#define NETSEC_TX_SHIFT_TDRID_FIELD 16
> +#define NETSEC_TX_SHIFT_CC_FIELD 15
> +#define NETSEC_TX_SHIFT_FS_FIELD 9
> +#define NETSEC_TX_LAST 8
> +#define NETSEC_TX_SHIFT_CO 7
> +#define NETSEC_TX_SHIFT_SO 6
> +#define NETSEC_TX_SHIFT_TRS_FIELD 4
> +
> +#define NETSEC_RX_PKT_OWN_FIELD 31
> +#define NETSEC_RX_PKT_LD_FIELD 30
> +#define NETSEC_RX_PKT_SDRID_FIELD 24
> +#define NETSEC_RX_PKT_FR_FIELD 23
> +#define NETSEC_RX_PKT_ER_FIELD 21
> +#define NETSEC_RX_PKT_ERR_FIELD 16
> +#define NETSEC_RX_PKT_TDRID_FIELD 12
> +#define NETSEC_RX_PKT_FS_FIELD 9
> +#define NETSEC_RX_PKT_LS_FIELD 8
> +#define NETSEC_RX_PKT_CO_FIELD 6
> +
> +#define NETSEC_RX_PKT_ERR_MASK 3
> +
> +#define NETSEC_MAX_TX_PKT_LEN 1518
> +#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
> +
> +#define NETSEC_RING_GMAC 15
> +#define NETSEC_RING_MAX 2
> +
> +#define NETSEC_TCP_SEG_LEN_MAX 1460
> +#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
> +
> +#define NETSEC_RX_CKSUM_NOTAVAIL 0
> +#define NETSEC_RX_CKSUM_OK 1
> +#define NETSEC_RX_CKSUM_NG 2
> +
> +#define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
> +#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
> +
> +#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
> +#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
> +
> +#define NETSEC_INT_PKTCNT_MAX 2047
> +
> +#define NETSEC_FLOW_START_TH_MAX 95
> +#define NETSEC_FLOW_STOP_TH_MAX 95
> +#define NETSEC_FLOW_PAUSE_TIME_MIN 5
> +
> +#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
> +
> +#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
> +#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
> +#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
> +#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
> +#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
> +
> +#define NETSEC_CLK_EN_REG_DOM_G BIT(5)
> +#define NETSEC_CLK_EN_REG_DOM_C BIT(1)
> +#define NETSEC_CLK_EN_REG_DOM_D BIT(0)
> +
> +#define NETSEC_COM_INIT_REG_DB BIT(2)
> +#define NETSEC_COM_INIT_REG_CLS BIT(1)
> +#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
> + NETSEC_COM_INIT_REG_DB)
> +
> +#define NETSEC_SOFT_RST_REG_RESET 0
> +#define NETSEC_SOFT_RST_REG_RUN BIT(31)
> +
> +#define NETSEC_DMA_CTRL_REG_STOP 1
> +#define MH_CTRL__MODE_TRANS BIT(20)
> +
> +#define NETSEC_GMAC_CMD_ST_READ 0
> +#define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
> +#define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
> +
> +#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
> +#define NETSEC_GMAC_BMR_REG_RESET 0x00020181
> +#define NETSEC_GMAC_BMR_REG_SWR 0x00000001
> +
> +#define NETSEC_GMAC_OMR_REG_ST BIT(13)
> +#define NETSEC_GMAC_OMR_REG_SR BIT(1)
> +
> +#define NETSEC_GMAC_MCR_REG_IBN BIT(30)
> +#define NETSEC_GMAC_MCR_REG_CST BIT(25)
> +#define NETSEC_GMAC_MCR_REG_JE BIT(20)
> +#define NETSEC_MCR_PS BIT(15)
> +#define NETSEC_GMAC_MCR_REG_FES BIT(14)
> +#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
> +#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
> +
> +#define NETSEC_FCR_RFE BIT(2)
> +#define NETSEC_FCR_TFE BIT(1)
> +
> +#define NETSEC_GMAC_GAR_REG_GW BIT(1)
> +#define NETSEC_GMAC_GAR_REG_GB BIT(0)
> +
> +#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
> +#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
> +#define GMAC_REG_SHIFT_CR_GAR 2
> +
> +#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
> +#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
> +#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
> +#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
> +#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
> +#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
> +
> +#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
> +#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
> +
> +#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
> +
> +#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
> +#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
> +#define NETSEC_REG_DESC_TMR_MODE 4
> +#define NETSEC_REG_DESC_ENDIAN 0
> +
> +#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
> +#define NETSEC_MAC_DESC_INIT_REG_INIT 1
> +
> +#define NETSEC_EEPROM_MAC_ADDRESS 0x00
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
> +#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
> +#define NETSEC_EEPROM_HM_ME_SIZE 0x10
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
> +#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
> +#define NETSEC_EEPROM_MH_ME_SIZE 0x1C
> +#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
> +#define NETSEC_EEPROM_PKT_ME_SIZE 0x24
> +
> +#define DESC_SZ sizeof(struct netsec_de)
> +
> +#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
> +
> +#define EERPROM_MAP_OFFSET 0x8000000
> +#define NOR_BLOCK 1024
> +
> +struct netsec_de { /* Netsec Descriptor layout */
> + u32 attr;
> + u32 data_buf_addr_up;
> + u32 data_buf_addr_lw;
> + u32 buf_len_info;
> +};
> +
> +struct netsec_priv {
> + struct netsec_de rxde[PKTBUFSRX];
> + struct netsec_de txde[1];
> + u16 rxat;
> +
> + phys_addr_t eeprom_base;
> + phys_addr_t ioaddr;
> +
> + struct mii_dev *bus;
> + struct phy_device *phydev;
> + u32 phy_addr, freq;
> + int phy_mode;
> + int max_speed;
> +};
> +
> +struct netsec_tx_pkt_ctrl {
> + u16 tcp_seg_len;
> + bool tcp_seg_offload_flag;
> + bool cksum_offload_flag;
> +};
> +
> +struct netsec_rx_pkt_info {
> + int rx_cksum_result;
> + int err_code;
> + bool err_flag;
> +};
> +
> +static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr,
> u32 val)
> +{
> + writel(val, priv->ioaddr + reg_addr);
> +}
> +
> +static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
> +{
> + return readl(priv->ioaddr + reg_addr);
> +}
> +
> +/************* MDIO BUS OPS FOLLOW *************/
> +
> +#define TIMEOUT_SPINS_MAC 1000
> +#define TIMEOUT_SECONDARY_MS_MAC 100
> +
> +static u32 netsec_clk_type(u32 freq)
> +{
> + if (freq < MHZ(35))
> + return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
> + if (freq < MHZ(60))
> + return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
> + if (freq < MHZ(100))
> + return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
> + if (freq < MHZ(150))
> + return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
> + if (freq < MHZ(250))
> + return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
> +
> + return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
> +}
> +
> +static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr,
> u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> +
> + while (--timeout && netsec_read_reg(priv, addr) & mask)
> + cpu_relax();
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + while (--timeout && netsec_read_reg(priv, addr) & mask)
> + udelay(2000);
> +
> + if (timeout)
> + return 0;
> +
> + pr_err("%s: timeout\n", __func__);
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32
> value)
> +{
> + netsec_write_reg(priv, MAC_REG_DATA, value);
> + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
> + return netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> +}
> +
> +static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32
> *read)
> +{
> + int ret;
> +
> + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
> + ret = netsec_wait_while_busy(priv,
> + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
> + if (ret)
> + return ret;
> +
> + *read = netsec_read_reg(priv, MAC_REG_DATA);
> +
> + return 0;
> +}
> +
> +static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
> + u32 addr, u32 mask)
> +{
> + u32 timeout = TIMEOUT_SPINS_MAC;
> + u32 data;
> + int ret;
> +
> + do {
> + ret = netsec_get_mac_reg(priv, addr, &data);
> + if (ret)
> + break;
> + udelay(1);
> + } while (--timeout && (data & mask));
> +
> + if (timeout)
> + return 0;
> +
> + timeout = TIMEOUT_SECONDARY_MS_MAC;
> + do {
> + udelay(2000);
> +
> + ret = netsec_get_mac_reg(priv, addr, &data);
> + if (ret)
> + break;
> + cpu_relax();
> + } while (--timeout && (data & mask));
> +
> + if (timeout && !ret)
> + return 0;
> +
> + return -ETIMEDOUT;
> +}
> +
> +static void netsec_cache_invalidate(uintptr_t vaddr, int len)
> +{
> + invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
> + roundup(vaddr + len, ARCH_DMA_MINALIGN));
> +}
> +
> +static void netsec_cache_flush(uintptr_t vaddr, int len)
> +{
> + flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
> + roundup(vaddr + len, ARCH_DMA_MINALIGN));
> +}
> +
> +static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void
> *addr)
> +{
> + struct netsec_de *de = &priv->rxde[idx];
> + u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
> + (1 << NETSEC_RX_PKT_FS_FIELD) |
> + (1 << NETSEC_RX_PKT_LS_FIELD);
> +
> + if (idx == PKTBUFSRX - 1)
> + attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
> + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
> + de->buf_len_info = PKTSIZE;
> + de->attr = attr;
> + dmb();
> + netsec_cache_flush((uintptr_t)de, sizeof(*de));
> +}
> +
> +static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int
> len)
> +{
> + struct netsec_de *de = &priv->txde[0];
> + u32 attr;
> +
> + attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
> + (1 << NETSEC_TX_SHIFT_PT_FIELD) |
> + (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
> + (1 << NETSEC_TX_SHIFT_FS_FIELD) |
> + (1 << NETSEC_TX_LAST) |
> + (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
> + (1 << NETSEC_TX_SHIFT_LD_FIELD);
> +
> + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
> + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
> + de->buf_len_info = len;
> + de->attr = attr;
> + dmb();
> + netsec_cache_flush((uintptr_t)de, sizeof(*de));
> +}
> +
> +static int netsec_get_phy_reg(struct netsec_priv *priv,
> + int phy_addr, int reg_addr)
> +{
> + u32 data;
> + int ret;
> +
> + if (phy_addr != 7)
> + return -EINVAL;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> + if (ret)
> + return ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
> + if (ret)
> + return ret;
> +
> + return data;
> +}
> +
> +static int netsec_set_phy_reg(struct netsec_priv *priv,
> + int phy_addr, int reg_addr, u16 val)
> +{
> + int ret;
> +
> + if (phy_addr != 7)
> + return -EINVAL;
> + if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
> + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
> + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
> + NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
> + (netsec_clk_type(priv->freq) <<
> + GMAC_REG_SHIFT_CR_GAR)))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
> + NETSEC_GMAC_GAR_REG_GB);
> +
> + /* Developerbox implements RTL8211E PHY and there is
> + * a compatibility problem with F_GMAC4.
> + * RTL8211E expects MDC clock must be kept toggling for several
> + * clock cycle with MDIO high before entering the IDLE state.
> + * To meet this requirement, netsec driver needs to issue dummy
> + * read(e.g. read PHYID1(offset 0x2) register) right after write.
> + */
> + netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
> +
> + return ret;
> +}
> +
> +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
> +{
> + struct phy_device *phydev = priv->phydev;
> + u32 value = 0;
> +
> + value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
> +
> + if (phydev->speed != SPEED_1000)
> + value |= NETSEC_MCR_PS;
> +
> + if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
> + phydev->speed == SPEED_100)
> + value |= NETSEC_GMAC_MCR_REG_FES;
> +
> + value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
> +
> + if (phy_interface_is_rgmii(phydev))
> + value |= NETSEC_GMAC_MCR_REG_IBN;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_start_gmac(struct netsec_priv *priv)
> +{
> + u32 value = 0;
> + int ret;
> +
> + if (priv->max_speed != SPEED_1000)
> + value = (NETSEC_GMAC_MCR_REG_CST |
> + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_RESET))
> + return -ETIMEDOUT;
> +
> + /* Wait soft reset */
> + mdelay(5);
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
> + if (ret)
> + return ret;
> +
> + if (value & NETSEC_GMAC_BMR_REG_SWR)
> + return -EAGAIN;
> +
> + netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
> + return -ETIMEDOUT;
> +
> + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
> + if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
> + NETSEC_GMAC_BMR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
> + NETSEC_GMAC_RDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
> + NETSEC_GMAC_TDLAR_REG_COMMON))
> + return -ETIMEDOUT;
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
> + return -ETIMEDOUT;
> +
> + ret = netsec_mac_update_to_phy_state(priv);
> + if (ret)
> + return ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> +
> + value |= NETSEC_GMAC_OMR_REG_SR;
> + value |= NETSEC_GMAC_OMR_REG_ST;
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int netsec_stop_gmac(struct netsec_priv *priv)
> +{
> + u32 value;
> + int ret;
> +
> + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
> + if (ret)
> + return ret;
> + value &= ~NETSEC_GMAC_OMR_REG_SR;
> + value &= ~NETSEC_GMAC_OMR_REG_ST;
> +
> + /* disable all interrupts */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
> +
> + return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
> +}
> +
> +static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
> +{
> + struct udevice *new;
> + struct spi_flash *flash;
> +
> + spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
> + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
> + flash = dev_get_uclass_priv(new);
> +
> + spi_flash_read(flash, offset, len, buf);
> +}
> +
> +static int netsec_read_rom_hwaddr(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + char macp[NOR_BLOCK];
> +
> + netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
> +
> + pdata->enetaddr[0] = readb(macp + 3);
> + pdata->enetaddr[1] = readb(macp + 2);
> + pdata->enetaddr[2] = readb(macp + 1);
> + pdata->enetaddr[3] = readb(macp + 0);
> + pdata->enetaddr[4] = readb(macp + 7);
> + pdata->enetaddr[5] = readb(macp + 6);
> + return 0;
> +}
> +
> +static int netsec_send(struct udevice *dev, void *packet, int length)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + u32 val, tout;
> +
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
> + netsec_cache_flush((uintptr_t)packet, length);
> + netsec_set_tx_de(priv, packet, length);
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another
> tx */
> +
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
> +
> + tout = 10000;
> + do {
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
> + udelay(2);
> + } while (--tout && !val);
> +
> + if (!tout) {
> + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
> + pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int netsec_free_packet(struct udevice *dev, uchar *packet, int
> length)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
> +
> + priv->rxat++;
> + if (priv->rxat == PKTBUFSRX)
> + priv->rxat = 0;
> +
> + return 0;
> +}
> +
> +static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int idx = priv->rxat;
> + uchar *ptr = net_rx_packets[idx];
> + struct netsec_de *de = &priv->rxde[idx];
> + int length = 0;
> +
> + netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
> +
> + if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
> + return -EAGAIN;
> +
> + length = de->buf_len_info >> 16;
> +
> + /* invalidate after DMA is done */
> + netsec_cache_invalidate((uintptr_t)ptr, length);
> + *packetp = ptr;
> +
> + return length;
> +}
> +
> +static int _netsec_get_phy_reg(struct mii_dev *bus,
> + int phy_addr, int devad, int reg_addr)
> +{
> + return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
> +}
> +
> +static int _netsec_set_phy_reg(struct mii_dev *bus,
> + int phy_addr, int devad, int reg_addr, u16 val)
> +{
> + return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
> +}
> +
> +static int netsec_mdiobus_init(struct netsec_priv *priv, const char
> *name)
> +{
> + struct mii_dev *bus = mdio_alloc();
> +
> + if (!bus)
> + return -ENOMEM;
> +
> + bus->read = _netsec_get_phy_reg;
> + bus->write = _netsec_set_phy_reg;
> + snprintf(bus->name, sizeof(bus->name), "%s", name);
> + bus->priv = priv;
> +
> + return mdio_register(bus);
> +}
> +
> +static int netsec_phy_init(struct netsec_priv *priv, void *dev)
> +{
> + struct phy_device *phydev;
> + int ret;
> +
> + phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
> +
> + phydev->supported &= PHY_GBIT_FEATURES;
> + if (priv->max_speed) {
> + ret = phy_set_supported(phydev, priv->max_speed);
> + if (ret)
> + return ret;
> + }
> + phydev->advertising = phydev->supported;
> +
> + priv->phydev = phydev;
> + phy_config(phydev);
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_load_ucode_region(struct netsec_priv *priv,
> u32 reg,
> + u32 addr_h, u32 addr_l, u32 size)
> +{
> + u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
> +
> + while (size > 0) {
> + char buf[NOR_BLOCK];
> + u32 *ucode = (u32 *)buf;
> + u64 off;
> + int i;
> +
> + off = base % NOR_BLOCK;
> + base -= off;
> + netsec_spi_read(buf, sizeof(buf), base);
> +
> + for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
> + netsec_write_reg(priv, reg, ucode[i]);
> + base += NOR_BLOCK;
> + }
> +
> + return 0;
> +}
> +
> +static int netsec_netdev_load_microcode(struct netsec_priv *priv)
> +{
> + u32 addr_h, addr_l, size;
> + char buf[NOR_BLOCK];
> + u32 *ucinfo = (u32 *)buf;
> + int err;
> +
> + netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
> +
> + addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
> + addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
> + size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv,
> NETSEC_REG_DMAC_HM_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
> + addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
> + size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv,
> NETSEC_REG_DMAC_MH_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + addr_h = 0;
> + addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
> + size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
> +
> + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
> + addr_h, addr_l, size);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +void netsec_pre_init_microengine(struct netsec_priv *priv)
> +{
> + u32 data;
> +
> + /* Remove dormant settings */
> + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
> + data &= ~BMCR_PDOWN;
> + data |= BMCR_ISOLATE;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +
> + /* Put phy in loopback mode to guarantee RXCLK input */
> + data |= BMCR_LOOPBACK;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +}
> +
> +void netsec_post_init_microengine(struct netsec_priv *priv)
> +{
> + u32 data;
> +
> + /* Get phy back to normal operation */
> + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
> + data &= ~BMCR_LOOPBACK;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +
> + /* Apply software reset */
> + data |= BMCR_RESET;
> + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
> + mdelay(100);
> +}
> +
> +static int netsec_reset_hardware(struct netsec_priv *priv, bool
> load_ucode)
> +{
> + u32 value;
> + int err;
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
> +
> + /* stop DMA engines */
> + if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
> + netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
> + NETSEC_DMA_CTRL_REG_STOP);
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
> + NETSEC_DMA_CTRL_REG_STOP) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> + }
> +
> + netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
> +
> + netsec_write_reg(priv, NETSEC_REG_SOFT_RST,
> NETSEC_SOFT_RST_REG_RESET);
> + netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
> + netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
> +
> + value = 100;
> + while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
> + udelay(1000);
> + if (--value == 0) {
> + pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
> + break;
> + }
> + }
> +
> + /* MAC desc init */
> + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
> + netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
> + /* set MAC_INTF_SEL */
> + netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + /* set desc_start addr */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->rxde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->rxde));
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->txde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->txde));
> +
> + /* set normal tx dring ring config */
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
> + 1 << NETSEC_REG_DESC_ENDIAN);
> +
> + if (load_ucode) {
> + err = netsec_netdev_load_microcode(priv);
> + if (err) {
> + pr_err("%s: failed to load microcode (%d)\n",
> + __func__, err);
> + return err;
> + }
> + }
> +
> + /* set desc_start addr */
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->rxde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->rxde));
> +
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
> + upper_32_bits((dma_addr_t)priv->txde));
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
> + lower_32_bits((dma_addr_t)priv->txde));
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + /* start DMA engines */
> + netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 -
> 1);
> +
> + netsec_pre_init_microengine(priv);
> +
> + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
> +
> + mdelay(100);
> +
> + if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
> + NETSEC_TOP_IRQ_REG_ME_START)) {
> + pr_err("microengine start failed\n");
> + return -ENXIO;
> + }
> +
> + netsec_post_init_microengine(priv);
> +
> + /* clear microcode load end status */
> + netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
> + NETSEC_TOP_IRQ_REG_ME_START);
> +
> + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
> +
> + value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
> + value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
> + /* change to normal mode */
> + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
> + netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
> +
> + value = 100;
> + while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
> + NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
> + udelay(1000);
> + if (--value == 0) {
> + value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
> + pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
> + break;
> + }
> + }
> +
> + /* clear any pending EMPTY/ERR irq status */
> + netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
> +
> + /* Disable TX & RX intr */
> + netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
> +
> + return 0;
> +}
> +
> +static void netsec_stop(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
> + netsec_stop_gmac(priv);
> + phy_shutdown(priv->phydev);
> + netsec_reset_hardware(priv, false);
> +}
> +
> +static int netsec_start(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int i;
> +
> + phy_startup(priv->phydev);
> + netsec_start_gmac(priv);
> +
> + priv->rxat = 0;
> + for (i = 0; i < PKTBUFSRX; i++)
> + netsec_set_rx_de(priv, i, net_rx_packets[i]);
> +
> + return 0;
> +}
> +
> +static int netsec_of_to_plat(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct netsec_priv *priv = dev_get_priv(dev);
> + struct ofnode_phandle_args phandle_args;
> + const char *phy_mode;
> +
> + pdata->iobase = dev_read_addr_index(dev, 0);
> + priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
> +
> + pdata->phy_interface = -1;
> + phy_mode = dev_read_prop(dev, "phy-mode", NULL);
> + if (phy_mode)
> + pdata->phy_interface = phy_get_interface_by_name(phy_mode);
> + if (pdata->phy_interface == -1) {
> + pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
> + return -EINVAL;
> + }
> +
> + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> + &phandle_args))
> + priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
> + else
> + priv->phy_addr = 7;
> +
> + pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
> +
> + priv->ioaddr = pdata->iobase;
> + priv->phy_mode = pdata->phy_interface;
> + priv->max_speed = pdata->max_speed;
> + priv->freq = 250000000UL;
> +
> + return 0;
> +}
> +
> +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
> +#define SMMU_SCR0_MTCFG (0x1 << 20)
> +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
> +
> +static int netsec_probe(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG |
> SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
> + (phys_addr_t)0x52E00000);
> +
> + netsec_reset_hardware(priv, true);
> +
> + ret = netsec_mdiobus_init(priv, dev->name);
> + if (ret) {
> + pr_err("Failed to initialize mdiobus: %d\n", ret);
> + return ret;
> + }
> +
> + priv->bus = miiphy_get_dev_by_name(dev->name);
> +
> + ret = netsec_phy_init(priv, dev);
> + if (ret) {
> + pr_err("Failed to initialize phy: %d\n", ret);
> + goto out_mdiobus_release;
> + }
> +
> + return 0;
> +out_mdiobus_release:
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> + return ret;
> +}
> +
> +static int netsec_remove(struct udevice *dev)
> +{
> + struct netsec_priv *priv = dev_get_priv(dev);
> +
> + free(priv->phydev);
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> +
> + return 0;
> +}
> +
> +static const struct eth_ops netsec_ops = {
> + .start = netsec_start,
> + .stop = netsec_stop,
> + .send = netsec_send,
> + .recv = netsec_recv,
> + .free_pkt = netsec_free_packet,
> + .read_rom_hwaddr = netsec_read_rom_hwaddr,
> +};
> +
> +static const struct udevice_id netsec_ids[] = {
> + {
> + .compatible = "socionext,synquacer-netsec",
> + },
> + {}
> +};
> +
> +U_BOOT_DRIVER(ave) = {
> + .name = "synquacer_netsec",
> + .id = UCLASS_ETH,
> + .of_match = netsec_ids,
> + .probe = netsec_probe,
> + .remove = netsec_remove,
> + .of_to_plat = netsec_of_to_plat,
> + .ops = &netsec_ops,
> + .priv_auto = sizeof(struct netsec_priv),
> + .plat_auto = sizeof(struct eth_pdata),
> +};
Applied to u-boot-net/master, thanks!
Best regards,
Ramon Fried
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops
2021-06-04 9:43 ` [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops Masami Hiramatsu
@ 2021-07-06 22:50 ` Tom Rini
2021-07-07 22:47 ` Masami Hiramatsu
0 siblings, 1 reply; 20+ messages in thread
From: Tom Rini @ 2021-07-06 22:50 UTC (permalink / raw)
To: Masami Hiramatsu
Cc: Peng Fan, Simon Glass, Heinrich Schuchardt, Alexander Graf,
Jagan Teki, Vignesh R, Joe Hershberger, Ramon Fried, Sughosh Ganu,
Jassi Brar, Ilias Apalodimas, Masahisa Kojima, Takahiro Akashi,
Tim Harvey, Bin Meng, u-boot, Jaehoon Chung
[-- Attachment #1: Type: text/plain, Size: 348 bytes --]
On Fri, Jun 04, 2021 at 06:43:23PM +0900, Masami Hiramatsu wrote:
> Without this fix, scsi-scan will cause a synchronous abort
> when accessing ops->scan.
>
> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
> Reviewed-by: Simon Glass <sjg@chromium.org>
For the entire series, applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops
2021-07-06 22:50 ` Tom Rini
@ 2021-07-07 22:47 ` Masami Hiramatsu
0 siblings, 0 replies; 20+ messages in thread
From: Masami Hiramatsu @ 2021-07-07 22:47 UTC (permalink / raw)
To: Tom Rini
Cc: Peng Fan, Simon Glass, Heinrich Schuchardt, Alexander Graf,
Jagan Teki, Vignesh R, Joe Hershberger, Ramon Fried, Sughosh Ganu,
Jassi Brar, Ilias Apalodimas, Masahisa Kojima, Takahiro Akashi,
Tim Harvey, Bin Meng, U-Boot Mailing List, Jaehoon Chung
Hi Tom,
2021年7月7日(水) 7:50 Tom Rini <trini@konsulko.com>:
>
> On Fri, Jun 04, 2021 at 06:43:23PM +0900, Masami Hiramatsu wrote:
>
> > Without this fix, scsi-scan will cause a synchronous abort
> > when accessing ops->scan.
> >
> > Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
> > Reviewed-by: Simon Glass <sjg@chromium.org>
>
> For the entire series, applied to u-boot/master, thanks!
Thank you so much!
I have some updates, so I'll send it.
Regards,
--
Masami Hiramatsu
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-07-07 22:47 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
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2021-06-04 9:43 [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 01/13] ata: ahci-pci: Use scsi_ops to initialize ops Masami Hiramatsu
2021-07-06 22:50 ` Tom Rini
2021-07-07 22:47 ` Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 02/13] dm: pci: Skip setting VGA bridge bits if parent device is the host bus Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 03/13] efi: Fix to use null handle to create new handle for efi_fmp_raw Masami Hiramatsu
2021-06-04 9:43 ` [PATCH v5 04/13] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 05/13] pci: synquacer: Add SynQuacer ECAM based PCIe driver Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 06/13] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 07/13] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 08/13] net: synquacer: Add netsec driver Masami Hiramatsu
2021-06-12 18:32 ` Ramon Fried
2021-06-12 18:39 ` Ramon Fried
2021-06-04 9:44 ` [PATCH v5 09/13] i2c: synquacer: SNI Synquacer I2C controller Masami Hiramatsu
2021-06-04 9:44 ` [PATCH v5 10/13] ARM: dts: synquacer: Add device trees for DeveloperBox Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 11/13] board: synquacer: Add DeveloperBox 96boards EE support Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 12/13] doc: qemu: arm64: Fix the documentation of capsule update Masami Hiramatsu
2021-06-04 9:45 ` [PATCH v5 13/13] configs: synquacer: Enable EFI capsule update support Masami Hiramatsu
2021-06-11 7:25 ` [PATCH v5 00/13] arm64: synquacer: Add SynQuacer/DeveloperBox support Masami Hiramatsu
2021-06-11 8:05 ` Ilias Apalodimas
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