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Wed, 9 Jun 2021 09:06:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rickchen36@gmail.com Received: by mail-il1-x12c.google.com with SMTP id d1so20831899ils.5 for ; Wed, 09 Jun 2021 00:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=zRtzQrW6OJ0FJ3aCJPPhuc+DvJByroZ3b1xB76ViD7Q=; b=mmCQcUSOcdz6lgK6LRLFpOlJeSrWObdjFITM+Olacp3uXUghh3cOiXgTp8x+nLw+lY RfxYVH24c+X5F0Y+V8Ohxo8BQNGEEN5UMC1BfTKChRf5YuxUPsNqyUdTlVqXc5WzoR2R KevBSrbHlBX4cF3G1iLdE0V9S1UAffP6n1as8oEEQW5ztIWl6WWobyKIR/dQGpug3+tY Fpx+/VEVk2XDPBDmwQYFvw//CREx46BQ9+lrEefQJmn6u8+Ers1DP+IYKPCj0Ba8RCYG xSlso0OM6+KJBId0adWRpTzrC7KGhRm6gjZ4h2NuBvsHJ8tn9G1X3+ZgLQVxg/1iwaee yhxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=zRtzQrW6OJ0FJ3aCJPPhuc+DvJByroZ3b1xB76ViD7Q=; b=uKTTsP4beUZiI7bpzFbw686f2HGsKhPARLp9XQftu5MVXbaKLL5sqLJ2VBs+3akKcm YtxBTwkbLJEKgvIBs3sGX0rQvJG4owJIGeXORe1uPbm9ULX3AhJLaBWbv2ANxlwLRS67 fBXwi3O91ONLjTaNL/wWqmhwcRolDAC3F9TFH9uoSUITlX3uWogC18toK4hHbZnCLGPA 1Gp606uNCgzbIX3B+TRYORjKXrQvGxAsleXeJKMrkWTzysT/TWzKuSr1i9Sbt5VwXLdw FQ+0Ad5pj8qwhBUnP8niw3rjihh6dMb5QLzNVvB+Y5EU5vLckDFSUegeJi7fdRS5vtLH cqHg== X-Gm-Message-State: AOAM532F39y3WwZkmDHvSpL0cmW6uQZD2dpVMh8XpjDlqJ/flkxodK5n ThjqTo7HGpFtMCw8CtNNBzQ8MBp4YVSMZE75rkU= X-Google-Smtp-Source: ABdhPJxelgrM+tkOZhkYHRbh5HHNV9a1HbJMGc5jowDqi9q4PwHyorF4wtguK4bXkZhEeW7L8sJHd75Yg0o+E1j0d2c= X-Received: by 2002:a5e:9e4a:: with SMTP id j10mr22534563ioq.52.1623222416812; Wed, 09 Jun 2021 00:06:56 -0700 (PDT) MIME-Version: 1.0 References: <20210604055113.3630286-1-bmeng.cn@gmail.com> <20210604055113.3630286-5-bmeng.cn@gmail.com> <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8783@ATCPCS12.andestech.com> In-Reply-To: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8783@ATCPCS12.andestech.com> From: Rick Chen Date: Wed, 9 Jun 2021 15:06:45 +0800 Message-ID: Subject: Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config To: Bin Meng Cc: U-Boot Mailing List , rick , Leo Liang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Hi Bin, > From: Bin Meng > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(=E9=99=B3=E5=BB=BA=E5=BF=97) ;= Leo Yu-Chi Liang(=E6=A2=81=E8=82=B2=E9=BD=8A) ; U-B= oot Mailing List > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for S= PL config > > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention= was to use gdb to load device tree before running U-Boot SPL/proper from R= AM. When we switch to OF_SEPARATE we will have to use our own DT but withou= t "u-boot,dm-spl" in several essential nodes, SPL does not boot. Can you describe how do you verify and provide the steps about that SPL boot fail that I can duplicate it. :) Thanks, Rick. > > Let's add all the required "u-boot,dm-spl" for SPL config. > > Signed-off-by: Bin Meng > --- > > arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++ > arch/riscv/dts/ae350_32.dts | 1 + > arch/riscv/dts/ae350_64.dts | 1 + > 3 files changed, 54 insertions(+) > create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi > > diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-bo= ot.dtsi > new file mode 100644 > index 0000000000..0d4201cfae > --- /dev/null > +++ b/arch/riscv/dts/ae350-u-boot.dtsi > @@ -0,0 +1,52 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +/ { > + cpus { > + u-boot,dm-spl; > + CPU0: cpu@0 { > + u-boot,dm-spl; > + CPU0_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU1: cpu@1 { > + u-boot,dm-spl; > + CPU1_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU2: cpu@2 { > + u-boot,dm-spl; > + CPU2_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU3: cpu@3 { > + u-boot,dm-spl; > + CPU3_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + }; > + > + memory@0 { > + u-boot,dm-spl; > + }; > + > + soc { > + u-boot,dm-spl; > + > + plic1: interrupt-controller@e6400000 { > + u-boot,dm-spl; > + }; > + > + plmt0@e6000000 { > + u-boot,dm-spl; > + }; > + }; > + > + serial0: serial@f0300000 { > + u-boot,dm-spl; > + }; > + > +}; > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts in= dex 70576846f2..083f676333 100644 > --- a/arch/riscv/dts/ae350_32.dts > +++ b/arch/riscv/dts/ae350_32.dts > @@ -3,6 +3,7 @@ > /dts-v1/; > > #include "binman.dtsi" > +#include "ae350-u-boot.dtsi" > > / { > #address-cells =3D <1>; > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts in= dex 564e94a1db..74cff9122d 100644 > --- a/arch/riscv/dts/ae350_64.dts > +++ b/arch/riscv/dts/ae350_64.dts > @@ -3,6 +3,7 @@ > /dts-v1/; > > #include "binman.dtsi" > +#include "ae350-u-boot.dtsi" > > / { > #address-cells =3D <2>; > -- > 2.25.1 > > CONFIDENTIALITY NOTICE: > > This e-mail (and its attachments) may contain confidential and legally pr= ivileged information or information protected from disclosure. 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