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[209.85.128.172]) by smtp.gmail.com with ESMTPSA id v3-20020a81b703000000b00615bd0701c7sm5298501ywh.118.2024.04.29.01.29.35 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Apr 2024 01:29:35 -0700 (PDT) Received: by mail-yw1-f172.google.com with SMTP id 00721157ae682-61acfd3fd3fso45002977b3.1 for ; Mon, 29 Apr 2024 01:29:35 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWC4Ytc6hnW/wSJcv8u1qSZlZ32zz5TDcExd4s1Ou8nWFoyvawnXq4+yiBYXSMI7UZ6RkydbQPPx0bj+b3W2kSi3o4DAKZPdEE= X-Received: by 2002:a05:690c:3391:b0:61a:d3ac:5b51 with SMTP id fl17-20020a05690c339100b0061ad3ac5b51mr9413022ywb.38.1714379374988; Mon, 29 Apr 2024 01:29:34 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-sh@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <23e9b3fd0d78e46c9fc1835852ba226aba92c3ca.1713959531.git.geert+renesas@glider.be> <23a3abf08f358588ef448c1a2f2ef53013ce6b69.camel@physik.fu-berlin.de> <09d677ad889a0bc2d7ae4324e0ca3e90d741b23b.camel@physik.fu-berlin.de> In-Reply-To: <09d677ad889a0bc2d7ae4324e0ca3e90d741b23b.camel@physik.fu-berlin.de> From: Geert Uytterhoeven Date: Mon, 29 Apr 2024 10:29:22 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] sh: boot: Remove sh5 cache handling To: John Paul Adrian Glaubitz Cc: Yoshinori Sato , Rich Felker , Arnd Bergmann , linux-sh@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Adrian, On Mon, Apr 29, 2024 at 10:22=E2=80=AFAM John Paul Adrian Glaubitz wrote: > On Mon, 2024-04-29 at 10:06 +0200, Geert Uytterhoeven wrote: > > On Mon, Apr 29, 2024 at 9:52=E2=80=AFAM John Paul Adrian Glaubitz > > wrote: > > > > > > Don't have the 32-bit SH CPUs any caches? The code itself is uncondit= ionally executed, > > > it seems. > > > > They do. E.g. SH7751 has 8+8 KiB of L1 cache. > > But e.g. sh7724 has 32+32KiB L1 cache, and 256 KiB of unified L2 cache. > > SH772[34] have l2_cache_init() to enable the L2 cache, so probably they > > boot with L2 disabled, and we are fine. > > Understood. But what exactly was the job of cache_control() when all it > does was flushing the cache area? The cache is not enabled or disabled I assume flushing the cache was needed to push all code written to RAM. > here, is it? No, it is not enabled or disabled. Probably that was planned for later, cfr. the command parameter. > Also, I was wondering whether this could be related to the boot lockups > that I am seeing on my SH-7786LCR which stops after printing "Uncompressi= ng > Linux...". I doubt it, unless reading from 0x80000000 causes a lock-up... > I will test later this week whether your patch actually fixes this issue. ... in which case my patch will help ;-) Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds