From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79215CD1288 for ; Sat, 30 Mar 2024 10:19:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZTIGfz5hhS2W72pSSurpsxx0Jj31Y6K95rK7o9oZE8o=; b=0eWGgydN7Pea9G g5L3SIUWnuAX4eepazcsO8xMDUk9p/ggpUG4dFkWJRlc0h5ABfupfBWPMy+8irCShRt2n6PInDbi5 7xYo0A4FEhJGTuFMoI3NCMkCsNCsxxUPMJ6LW+Za96KVU8K/oG/iUHa+jKvDQcYaOO559hUqXPBjM QlSprUxFgh8n+ovO2DfY5q/q7A0+IqbkH3v7f/+knVxoVlud0pIfKIJNBf2NedzmRqV6nAxFOTyVn WBBsxQzWjYKqPtclTL043GZ/klEAZQbLarObuijM11qMB2f8EzyLc9GwlOfwcixsZsR1AWAzzhAI3 Tp6R9paHKLYCu0SZXWVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqVoO-00000003FZY-2a4P; Sat, 30 Mar 2024 10:19:44 +0000 Received: from [45.249.212.51] (helo=dggsgout11.his.huawei.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqVoK-00000003FYj-21HO for linux-riscv@lists.infradead.org; Sat, 30 Mar 2024 10:19:42 +0000 Received: from mail.maildlp.com (unknown [172.19.163.235]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTP id 4V6Ctj1f98z4f3kp4 for ; Sat, 30 Mar 2024 18:19:25 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 594351A0232 for ; Sat, 30 Mar 2024 18:19:29 +0800 (CST) Received: from [10.67.109.184] (unknown [10.67.109.184]) by APP2 (Coremail) with SMTP id Syh0CgCXug0s5wdmXWTTIg--.19989S2; Sat, 30 Mar 2024 18:19:25 +0800 (CST) Message-ID: <95e1978f-341c-4de5-a665-e057fe97a060@huaweicloud.com> Date: Sat, 30 Mar 2024 18:19:24 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions Content-Language: en-US To: Conor Dooley Cc: Stefan O'Rear , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Pu Lehui In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> X-CM-TRANSID: Syh0CgCXug0s5wdmXWTTIg--.19989S2 X-Coremail-Antispam: 1UD129KBjvJXoWxur4UGFW5XF4UXrWDGFW5GFg_yoWrtF4DpF WfKF1xKFn7Jw1fZ393Xw18Wr1093Z7Kw43GrykG34Fy343ur1xGw1qy3ZrXFyDZrn3Gr1a v390gF1q93WUCFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcVAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxAIw28IcxkI 7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6x AIw20EY4v20xvaj40_Wr1j6rW3Jr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IUbG2NtUUUUU== X-CM-SenderInfo: psxovxtxl6x35dzhxuhorxvhhfrp/ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240330_031940_910899_B0C1564E X-CRM114-Status: GOOD ( 33.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Thanks for the clarification, looks good. On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dggsgout11.his.huawei.com (unknown [45.249.212.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AE2C11712; Sat, 30 Mar 2024 10:19:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711793981; cv=none; b=XjBCD05gp0RzPexcO+ruoj3Fvp0FHXH+g1yfSbBCSauFIO1tUJvCAj18ickaY2KtMh11GdCoGwv3yLyQZoDDBinyTfTzxZ5XaxHx7XGBoBo5iGdcqn7ARJxFLji2YUWRwxjWGn6aW3Oinox5cToQXAPElCFyZ7MFApmpor1VULY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711793981; c=relaxed/simple; bh=Kj8wuHAHZVd+Kvn7QFiN9E4M/87APJxMIBq/ikHQ35Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ilzO63a9w9glrMWlidF2JyKlGjQXsTBHUwYWqKLjURwPleSvCK0pu0qEQdVpkPgBj5Tx3dxnOZS852pfce8pAD873pPxN2FP6XW++Ruqeqw5s1oHFlXc5dC6RReHxltRJkkBQ+ajCbNKwPRUITLQoWw6vma09F/1Pl3fF0oK81s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.235]) by dggsgout11.his.huawei.com (SkyGuard) with ESMTP id 4V6Ctd17Lrz4f3lgL; Sat, 30 Mar 2024 18:19:21 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.75]) by mail.maildlp.com (Postfix) with ESMTP id 64B191A0568; Sat, 30 Mar 2024 18:19:29 +0800 (CST) Received: from [10.67.109.184] (unknown [10.67.109.184]) by APP2 (Coremail) with SMTP id Syh0CgCXug0s5wdmXWTTIg--.19989S2; Sat, 30 Mar 2024 18:19:25 +0800 (CST) Message-ID: <95e1978f-341c-4de5-a665-e057fe97a060@huaweicloud.com> Date: Sat, 30 Mar 2024 18:19:24 +0800 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions Content-Language: en-US To: Conor Dooley Cc: Stefan O'Rear , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Pu Lehui In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID:Syh0CgCXug0s5wdmXWTTIg--.19989S2 X-Coremail-Antispam: 1UD129KBjvJXoWxur4UGFW5XF4UXrWDGFW5GFg_yoWrtF4DpF WfKF1xKFn7Jw1fZ393Xw18Wr1093Z7Kw43GrykG34Fy343ur1xGw1qy3ZrXFyDZrn3Gr1a v390gF1q93WUCFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcVAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxAIw28IcxkI 7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6x AIw20EY4v20xvaj40_Wr1j6rW3Jr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IUbG2NtUUUUU== X-CM-SenderInfo: psxovxtxl6x35dzhxuhorxvhhfrp/ Thanks for the clarification, looks good. On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF7FECD1284 for ; Sun, 31 Mar 2024 16:43:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Message-ID: <95e1978f-341c-4de5-a665-e057fe97a060@huaweicloud.com> Date: Sat, 30 Mar 2024 18:19:24 +0800 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions Content-Language: en-US To: Conor Dooley CC: Stefan O'Rear , , , , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Eduard Zingerman" , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Pu Lehui In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> X-CM-TRANSID: Syh0CgCXug0s5wdmXWTTIg--.19989S2 X-Coremail-Antispam: 1UD129KBjvJXoWxur4UGFW5XF4UXrWDGFW5GFg_yoWrtF4DpF WfKF1xKFn7Jw1fZ393Xw18Wr1093Z7Kw43GrykG34Fy343ur1xGw1qy3ZrXFyDZrn3Gr1a v390gF1q93WUCFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcVAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxAIw28IcxkI 7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6x AIw20EY4v20xvaj40_Wr1j6rW3Jr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IUbG2NtUUUUU== X-CM-SenderInfo: psxovxtxl6x35dzhxuhorxvhhfrp/ X-EXCLAIMER-MD-CONFIG: 2c86f778-e09b-4440-8b15-867914633a10 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240331_174307_278982_08DF7545 X-CRM114-Status: GOOD ( 37.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Message-ID: <20240330101924.M5oHnEvflJyLGs8-qOcLVMSTSMjKombrHskxoNiDUzU@z> Thanks for the clarification, looks good. On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > X-sender: X-Receiver: ORCPT=rfc822;steffen.klassert@secunet.com NOTIFY=NEVER; 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On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: > >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. > > Something like this: > > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 > > RISC-V: clarify what some RISCV_ISA* config options do > > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on what > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text to > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or not an > extension is detected dynamically as that's done regardless of Kconfig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.holland@sifive.com/ > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > > If you don't know what to do here, say Y. > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from a.mx.secunet.com (a.mx.secunet.com [62.96.220.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD59615D5A6; Sun, 31 Mar 2024 16:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=62.96.220.36 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711903437; cv=fail; b=ZdlSB4PRwBuyml+Rz2KnhFJhz0ghOwGQ2rvlsdzEpzpwFphzMShrK3mosMaepvjzbd8UCLRXQr8VELcNTMqGVr8ZZqQGA5E+JEGZtRa2CUPz84aeXFHfm5WdlAuC/zcMu+4J1FyIu/gbzVo3qLNaA8kzz0uDvMjeo3CN3iS9IIU= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; 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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Message-ID: <95e1978f-341c-4de5-a665-e057fe97a060@huaweicloud.com> Date: Sat, 30 Mar 2024 18:19:24 +0800 Precedence: bulk Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions Content-Language: en-US To: Conor Dooley CC: Stefan O'Rear , , , , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , "Eduard Zingerman" , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Pu Lehui In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: Syh0CgCXug0s5wdmXWTTIg--.19989S2 X-Coremail-Antispam: 1UD129KBjvJXoWxur4UGFW5XF4UXrWDGFW5GFg_yoWrtF4DpF WfKF1xKFn7Jw1fZ393Xw18Wr1093Z7Kw43GrykG34Fy343ur1xGw1qy3ZrXFyDZrn3Gr1a v390gF1q93WUCFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcVAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxAIw28IcxkI 7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6x AIw20EY4v20xvaj40_Wr1j6rW3Jr1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IUbG2NtUUUUU== X-CM-SenderInfo: psxovxtxl6x35dzhxuhorxvhhfrp/ X-EXCLAIMER-MD-CONFIG: 2c86f778-e09b-4440-8b15-867914633a10 Message-ID: <20240330101924.d40d0fEx7AWzmxzipL-m3C0FMSDDIiVWJ0kubkH097U@z> Thanks for the clarification, looks good. On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: >=20 >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. >=20 > Something like this: >=20 > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 >=20 > RISC-V: clarify what some RISCV_ISA* config options do > =20 > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on wh= at > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text t= o > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or no= t an > extension is detected dynamically as that's done regardless of Kconf= ig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > =20 > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c= 554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.= holland@sifive.com/ >=20 > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > =20 > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > =20 > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > =20 > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > =20 > If you don't know what to do here, say Y. > =20 > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > =20 > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > =20 > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedu= re > - in the kernel. > + in the kernel. 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<20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> <20240329-linguini-uncured-380cb4cff61c@wendy> From: Pu Lehui In-Reply-To: <20240329-linguini-uncured-380cb4cff61c@wendy> Content-Type: text/plain; charset=3D"UTF-8"; format=3Dflowed Content-Transfer-Encoding: 7bit X-CM-TRANSID: Syh0CgCXug0s5wdmXWTTIg--.19989S2 X-Coremail-Antispam: 1UD129KBjvJXoWxur4UGFW5XF4UXrWDGFW5GFg_yoWrtF4DpF WfKF1xKFn7Jw1fZ393Xw18Wr1093Z7Kw43GrykG34Fy343ur1xGw1qy3ZrXFyDZrn3Gr1a v390gF1q93WUCFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 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X-MS-Exchange-Forest-IndexAgent: 1 4678 X-MS-Exchange-Forest-EmailMessageHash: 06F33EE3 X-MS-Exchange-Forest-Language: en X-MS-Exchange-Organization-Processed-By-Journaling: Journal Agent Thanks for the clarification, looks good. On 2024/3/29 19:23, Conor Dooley wrote: > On Thu, Mar 28, 2024 at 10:07:23PM +0000, Conor Dooley wrote: >=20 >> As I said on IRC to you earlier, I think the Kconfig options here are in >> need of a bit of a spring cleaning - they should be modified to explain >> their individual purposes, be that enabling optimisations in the kernel >> or being required for userspace. I'll try to send a patch for that if >> I remember tomorrow. >=20 > Something like this: >=20 > -- >8 -- > commit 5125504beaedd669b082bf74b02003a77360670f > Author: Conor Dooley > Date: Fri Mar 29 11:13:22 2024 +0000 >=20 > RISC-V: clarify what some RISCV_ISA* config options do > =20 > During some discussion on IRC yesterday and on Pu's bpf patch [1] > I noticed that these RISCV_ISA* Kconfig options are not really clear > about their implications. Many of these options have no impact on wh= at > userspace is allowed to do, for example an application can use Zbb > regardless of whether or not the kernel does. Change the help text t= o > try and clarify whether or not an option affects just the kernel, or > also userspace. None of these options actually control whether or no= t an > extension is detected dynamically as that's done regardless of Kconf= ig > options, so drop any text that implies the option is required for > dynamic detection, rewording them as "do x when y is detected". > =20 > Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c= 554f75a676c@spud/ [1] > Signed-off-by: Conor Dooley > --- > I did this based on top of Samuel's changes dropping the MMU > requurements just in case, but I don't think there's a conflict: > https://lore.kernel.org/linux-riscv/20240227003630.3634533-4-samuel.= holland@sifive.com/ >=20 > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8a777f59402..f327a8ac648f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -501,8 +501,8 @@ config RISCV_ISA_SVNAPOT > depends on RISCV_ALTERNATIVE > default y > help > - Allow kernel to detect the Svnapot ISA-extension dynamically at boot > - time and enable its usage. > + Add support for the Svnapot ISA-extension when it is detected by > + the kernel at boot. > =20 > The Svnapot extension is used to mark contiguous PTEs as a range > of contiguous virtual-to-physical translations for a naturally > @@ -520,9 +520,9 @@ config RISCV_ISA_SVPBMT > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the Svpbmt > - ISA-extension (Supervisor-mode: page-based memory types) and > - enable its usage. > + Add support for the Svpbmt ISA-extension (Supervisor-mode: > + page-based memory types) when it is detected by the kernel at > + boot. > =20 > The memory type for a page contains a combination of attributes > that indicate the cacheability, idempotency, and ordering > @@ -541,14 +541,15 @@ config TOOLCHAIN_HAS_V > depends on AS_HAS_OPTION_ARCH > =20 > config RISCV_ISA_V > - bool "VECTOR extension support" > + bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > select DYNAMIC_SIGFRAME > default y > help > Say N here if you want to disable all vector related procedure > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > =20 > If you don't know what to do here, say Y. > =20 > @@ -606,8 +607,8 @@ config RISCV_ISA_ZBB > depends on RISCV_ALTERNATIVE > default y > help > - Adds support to dynamically detect the presence of the ZBB > - extension (basic bit manipulation) and enable its usage. > + Add support for enabling optimisations in the kernel when the > + Zbb extension is detected at boot. > =20 > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > @@ -623,9 +624,9 @@ config RISCV_ISA_ZICBOM > select RISCV_DMA_NONCOHERENT > select DMA_DIRECT_REMAP > help > - Adds support to dynamically detect the presence of the ZICBOM > - extension (Cache Block Management Operations) and enable its > - usage. > + Add support for the Zicbom extension (Cache Block Management > + Operations) and enable its use in the kernel when it is detected > + at boot. > =20 > The Zicbom extension can be used to handle for example > non-coherent DMA support on devices that need it. > @@ -684,7 +685,8 @@ config FPU > default y > help > Say N here if you want to disable all floating-point related procedu= re > - in the kernel. > + in the kernel. Without this option enabled, neither the kernel nor > + userspace may use vector. > =20 > If you don't know what to do here, say Y. > =20 >=20