* [PATCH v3 0/5] Add JH7110 AON PMU support
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
This patchset adds aon power domain driver for the StarFive JH7110 SoC.
It is used to turn on/off dphy rx/tx power switch. It also can use syscon
operation. The series has been tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
changes since v2:
- Updated commit message.
- Changed "starfive,jh7110-aon-pmu" to "starfive,jh7110-aon-syscon".
- Dropped patch 3: Modify ioremap to regmap.
- Changed "pmu_parse_dt" to "pmu_parse_irq".
- Dropped "pmu_parse_dt" function in aon pmu.
- Changed copyright to "2022-2023" in "starfive,jh7110-pmu.h".
- Replaced regread/regwrite operation with io_read/io_write operation.
v2: https://lore.kernel.org/all/20230419035646.43702-1-changhuang.liang@starfivetech.com/
changes since v1:
- Updated commit message.
- Changed "starfive,jh7110-pmu-dphy" to "starfive,jh7110-aon-pmu".
- Put if condition under allOf in .yaml file.
- Updated spelling error.
- Dropped patch 4: Add pmu type operation.
- Changed "jh71xx_pmu_general_set_state" to "jh7110_pmu_set_state" and moved it in call back.
- Changed "jh7110_pmu_general_parse_dt" to "jh7110_pmu_parse_dt" and moved it in call back.
- Used pmu_status save the pmu status offset.
- Changed "JH71XX_PMU_DPHY_SWITCH" to "JH71XX_AON_PMU_SWITCH"
- Changed copyright to "2022-2023"
v1: https://lore.kernel.org/all/20230411064743.273388-1-changhuang.liang@starfivetech.com/
Changhuang Liang (5):
dt-bindings: power: Add JH7110 AON PMU support
soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
soc: starfive: Extract JH7110 pmu private operations
soc: starfive: Add JH7110 AON PMU support
riscv: dts: starfive: jh7110: Add AON PMU node
.../bindings/power/starfive,jh7110-pmu.yaml | 28 +++-
MAINTAINERS | 1 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 +
drivers/soc/starfive/Kconfig | 4 +-
drivers/soc/starfive/jh71xx_pmu.c | 138 ++++++++++++++----
.../dt-bindings/power/starfive,jh7110-pmu.h | 5 +-
6 files changed, 148 insertions(+), 34 deletions(-)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 0/5] Add JH7110 AON PMU support
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
This patchset adds aon power domain driver for the StarFive JH7110 SoC.
It is used to turn on/off dphy rx/tx power switch. It also can use syscon
operation. The series has been tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
changes since v2:
- Updated commit message.
- Changed "starfive,jh7110-aon-pmu" to "starfive,jh7110-aon-syscon".
- Dropped patch 3: Modify ioremap to regmap.
- Changed "pmu_parse_dt" to "pmu_parse_irq".
- Dropped "pmu_parse_dt" function in aon pmu.
- Changed copyright to "2022-2023" in "starfive,jh7110-pmu.h".
- Replaced regread/regwrite operation with io_read/io_write operation.
v2: https://lore.kernel.org/all/20230419035646.43702-1-changhuang.liang@starfivetech.com/
changes since v1:
- Updated commit message.
- Changed "starfive,jh7110-pmu-dphy" to "starfive,jh7110-aon-pmu".
- Put if condition under allOf in .yaml file.
- Updated spelling error.
- Dropped patch 4: Add pmu type operation.
- Changed "jh71xx_pmu_general_set_state" to "jh7110_pmu_set_state" and moved it in call back.
- Changed "jh7110_pmu_general_parse_dt" to "jh7110_pmu_parse_dt" and moved it in call back.
- Used pmu_status save the pmu status offset.
- Changed "JH71XX_PMU_DPHY_SWITCH" to "JH71XX_AON_PMU_SWITCH"
- Changed copyright to "2022-2023"
v1: https://lore.kernel.org/all/20230411064743.273388-1-changhuang.liang@starfivetech.com/
Changhuang Liang (5):
dt-bindings: power: Add JH7110 AON PMU support
soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
soc: starfive: Extract JH7110 pmu private operations
soc: starfive: Add JH7110 AON PMU support
riscv: dts: starfive: jh7110: Add AON PMU node
.../bindings/power/starfive,jh7110-pmu.yaml | 28 +++-
MAINTAINERS | 1 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 +
drivers/soc/starfive/Kconfig | 4 +-
drivers/soc/starfive/jh71xx_pmu.c | 138 ++++++++++++++----
.../dt-bindings/power/starfive,jh7110-pmu.h | 5 +-
6 files changed, 148 insertions(+), 34 deletions(-)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 1:53 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
rx/tx power switch, and it don't need the property of interrupts. It
also can use syscon operation.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/power/starfive,jh7110-pmu.yaml | 28 +++++++++++++++++--
.../dt-bindings/power/starfive,jh7110-pmu.h | 5 +++-
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
index 98eb8b4110e7..0591a4e9db6c 100644
--- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
+++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
@@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit
maintainers:
- Walker Chen <walker.chen@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
description: |
StarFive JH7110 SoC includes support for multiple power domains which can be
@@ -15,8 +16,13 @@ description: |
properties:
compatible:
- enum:
- - starfive,jh7110-pmu
+ oneOf:
+ - enum:
+ - starfive,jh7110-pmu
+ - items:
+ - enum:
+ - starfive,jh7110-aon-syscon
+ - const: syscon
reg:
maxItems: 1
@@ -30,9 +36,18 @@ properties:
required:
- compatible
- reg
- - interrupts
- "#power-domain-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-pmu
+ then:
+ required:
+ - interrupts
+
additionalProperties: false
examples:
@@ -43,3 +58,10 @@ examples:
interrupts = <111>;
#power-domain-cells = <1>;
};
+
+ - |
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x17010000 0x1000>;
+ #power-domain-cells = <1>;
+ };
diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h
index 132bfe401fc8..341e2a0676ba 100644
--- a/include/dt-bindings/power/starfive,jh7110-pmu.h
+++ b/include/dt-bindings/power/starfive,jh7110-pmu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
* Author: Walker Chen <walker.chen@starfivetech.com>
*/
#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__
@@ -14,4 +14,7 @@
#define JH7110_PD_ISP 5
#define JH7110_PD_VENC 6
+#define JH7110_PD_DPHY_TX 0
+#define JH7110_PD_DPHY_RX 1
+
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
rx/tx power switch, and it don't need the property of interrupts. It
also can use syscon operation.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/power/starfive,jh7110-pmu.yaml | 28 +++++++++++++++++--
.../dt-bindings/power/starfive,jh7110-pmu.h | 5 +++-
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
index 98eb8b4110e7..0591a4e9db6c 100644
--- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
+++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
@@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit
maintainers:
- Walker Chen <walker.chen@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
description: |
StarFive JH7110 SoC includes support for multiple power domains which can be
@@ -15,8 +16,13 @@ description: |
properties:
compatible:
- enum:
- - starfive,jh7110-pmu
+ oneOf:
+ - enum:
+ - starfive,jh7110-pmu
+ - items:
+ - enum:
+ - starfive,jh7110-aon-syscon
+ - const: syscon
reg:
maxItems: 1
@@ -30,9 +36,18 @@ properties:
required:
- compatible
- reg
- - interrupts
- "#power-domain-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-pmu
+ then:
+ required:
+ - interrupts
+
additionalProperties: false
examples:
@@ -43,3 +58,10 @@ examples:
interrupts = <111>;
#power-domain-cells = <1>;
};
+
+ - |
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x17010000 0x1000>;
+ #power-domain-cells = <1>;
+ };
diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h
index 132bfe401fc8..341e2a0676ba 100644
--- a/include/dt-bindings/power/starfive,jh7110-pmu.h
+++ b/include/dt-bindings/power/starfive,jh7110-pmu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
* Author: Walker Chen <walker.chen@starfivetech.com>
*/
#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__
@@ -14,4 +14,7 @@
#define JH7110_PD_ISP 5
#define JH7110_PD_VENC 6
+#define JH7110_PD_DPHY_TX 0
+#define JH7110_PD_DPHY_RX 1
+
#endif
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 2/5] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 1:53 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Using ARCH_FOO symbol is preferred than SOC_FOO.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/soc/starfive/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
index bdb96dc4c989..1e9b0c414fec 100644
--- a/drivers/soc/starfive/Kconfig
+++ b/drivers/soc/starfive/Kconfig
@@ -3,8 +3,8 @@
config JH71XX_PMU
bool "Support PMU for StarFive JH71XX Soc"
depends on PM
- depends on SOC_STARFIVE || COMPILE_TEST
- default SOC_STARFIVE
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
select PM_GENERIC_DOMAINS
help
Say 'y' here to enable support power domain support.
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 2/5] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Using ARCH_FOO symbol is preferred than SOC_FOO.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/soc/starfive/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
index bdb96dc4c989..1e9b0c414fec 100644
--- a/drivers/soc/starfive/Kconfig
+++ b/drivers/soc/starfive/Kconfig
@@ -3,8 +3,8 @@
config JH71XX_PMU
bool "Support PMU for StarFive JH71XX Soc"
depends on PM
- depends on SOC_STARFIVE || COMPILE_TEST
- default SOC_STARFIVE
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
select PM_GENERIC_DOMAINS
help
Say 'y' here to enable support power domain support.
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 1:53 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Move JH7110 private operation into private data of compatible. Convenient
to add AON PMU which would not have interrupts property.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++----------
1 file changed, 62 insertions(+), 27 deletions(-)
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 7d5f50d71c0d..0dbdcc0d2c91 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -51,9 +51,17 @@ struct jh71xx_domain_info {
u8 bit;
};
+struct jh71xx_pmu;
+struct jh71xx_pmu_dev;
+
struct jh71xx_pmu_match_data {
const struct jh71xx_domain_info *domain_info;
int num_domains;
+ unsigned int pmu_status;
+ int (*pmu_parse_irq)(struct platform_device *pdev,
+ struct jh71xx_pmu *pmu);
+ int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd,
+ u32 mask, bool on);
};
struct jh71xx_pmu {
@@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o
if (!mask)
return -EINVAL;
- *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
+ *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask;
return 0;
}
-static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
unsigned long flags;
@@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
u32 mode;
u32 encourage_lo;
u32 encourage_hi;
- bool is_on;
int ret;
- ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
- if (ret) {
- dev_dbg(pmu->dev, "unable to get current state for %s\n",
- pmd->genpd.name);
- return ret;
- }
-
- if (is_on == on) {
- dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
- pmd->genpd.name, on ? "en" : "dis");
- return 0;
- }
-
spin_lock_irqsave(&pmu->lock, flags);
/*
@@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ const struct jh71xx_pmu_match_data *match_data = pmu->match_data;
+ bool is_on;
+ int ret;
+
+ ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
+ if (ret) {
+ dev_dbg(pmu->dev, "unable to get current state for %s\n",
+ pmd->genpd.name);
+ return ret;
+ }
+
+ if (is_on == on) {
+ dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
+ pmd->genpd.name, on ? "en" : "dis");
+ return 0;
+ }
+
+ return match_data->pmu_set_state(pmd, mask, on);
+}
+
static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
{
struct jh71xx_pmu_dev *pmd = container_of(genpd,
@@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
+static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pmu->irq = platform_get_irq(pdev, 0);
+ if (pmu->irq < 0)
+ return pmu->irq;
+
+ ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
+ 0, pdev->name, pmu);
+ if (ret)
+ dev_err(dev, "failed to request irq\n");
+
+ jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
+
+ return 0;
+}
+
static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
{
struct jh71xx_pmu_dev *pmd;
@@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (IS_ERR(pmu->base))
return PTR_ERR(pmu->base);
- pmu->irq = platform_get_irq(pdev, 0);
- if (pmu->irq < 0)
- return pmu->irq;
-
- ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
- 0, pdev->name, pmu);
- if (ret)
- dev_err(dev, "failed to request irq\n");
+ spin_lock_init(&pmu->lock);
match_data = of_device_get_match_data(dev);
if (!match_data)
return -EINVAL;
+ ret = match_data->pmu_parse_irq(pdev, pmu);
+ if (ret) {
+ dev_err(dev, "failed to parse irq\n");
+ return ret;
+ }
+
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
sizeof(struct generic_pm_domain *),
GFP_KERNEL);
@@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
}
}
- spin_lock_init(&pmu->lock);
- jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
-
ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
if (ret) {
dev_err(dev, "failed to register genpd driver: %d\n", ret);
@@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
static const struct jh71xx_pmu_match_data jh7110_pmu = {
.num_domains = ARRAY_SIZE(jh7110_power_domains),
.domain_info = jh7110_power_domains,
+ .pmu_status = JH71XX_PMU_CURR_POWER_MODE,
+ .pmu_parse_irq = jh7110_pmu_parse_irq,
+ .pmu_set_state = jh7110_pmu_set_state,
};
static const struct of_device_id jh71xx_pmu_of_match[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Move JH7110 private operation into private data of compatible. Convenient
to add AON PMU which would not have interrupts property.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++----------
1 file changed, 62 insertions(+), 27 deletions(-)
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 7d5f50d71c0d..0dbdcc0d2c91 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -51,9 +51,17 @@ struct jh71xx_domain_info {
u8 bit;
};
+struct jh71xx_pmu;
+struct jh71xx_pmu_dev;
+
struct jh71xx_pmu_match_data {
const struct jh71xx_domain_info *domain_info;
int num_domains;
+ unsigned int pmu_status;
+ int (*pmu_parse_irq)(struct platform_device *pdev,
+ struct jh71xx_pmu *pmu);
+ int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd,
+ u32 mask, bool on);
};
struct jh71xx_pmu {
@@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o
if (!mask)
return -EINVAL;
- *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
+ *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask;
return 0;
}
-static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
unsigned long flags;
@@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
u32 mode;
u32 encourage_lo;
u32 encourage_hi;
- bool is_on;
int ret;
- ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
- if (ret) {
- dev_dbg(pmu->dev, "unable to get current state for %s\n",
- pmd->genpd.name);
- return ret;
- }
-
- if (is_on == on) {
- dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
- pmd->genpd.name, on ? "en" : "dis");
- return 0;
- }
-
spin_lock_irqsave(&pmu->lock, flags);
/*
@@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ const struct jh71xx_pmu_match_data *match_data = pmu->match_data;
+ bool is_on;
+ int ret;
+
+ ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
+ if (ret) {
+ dev_dbg(pmu->dev, "unable to get current state for %s\n",
+ pmd->genpd.name);
+ return ret;
+ }
+
+ if (is_on == on) {
+ dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
+ pmd->genpd.name, on ? "en" : "dis");
+ return 0;
+ }
+
+ return match_data->pmu_set_state(pmd, mask, on);
+}
+
static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
{
struct jh71xx_pmu_dev *pmd = container_of(genpd,
@@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
+static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pmu->irq = platform_get_irq(pdev, 0);
+ if (pmu->irq < 0)
+ return pmu->irq;
+
+ ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
+ 0, pdev->name, pmu);
+ if (ret)
+ dev_err(dev, "failed to request irq\n");
+
+ jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
+
+ return 0;
+}
+
static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
{
struct jh71xx_pmu_dev *pmd;
@@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (IS_ERR(pmu->base))
return PTR_ERR(pmu->base);
- pmu->irq = platform_get_irq(pdev, 0);
- if (pmu->irq < 0)
- return pmu->irq;
-
- ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
- 0, pdev->name, pmu);
- if (ret)
- dev_err(dev, "failed to request irq\n");
+ spin_lock_init(&pmu->lock);
match_data = of_device_get_match_data(dev);
if (!match_data)
return -EINVAL;
+ ret = match_data->pmu_parse_irq(pdev, pmu);
+ if (ret) {
+ dev_err(dev, "failed to parse irq\n");
+ return ret;
+ }
+
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
sizeof(struct generic_pm_domain *),
GFP_KERNEL);
@@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
}
}
- spin_lock_init(&pmu->lock);
- jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
-
ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
if (ret) {
dev_err(dev, "failed to register genpd driver: %d\n", ret);
@@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
static const struct jh71xx_pmu_match_data jh7110_pmu = {
.num_domains = ARRAY_SIZE(jh7110_power_domains),
.domain_info = jh7110_power_domains,
+ .pmu_status = JH71XX_PMU_CURR_POWER_MODE,
+ .pmu_parse_irq = jh7110_pmu_parse_irq,
+ .pmu_set_state = jh7110_pmu_set_state,
};
static const struct of_device_id jh71xx_pmu_of_match[] = {
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 4/5] soc: starfive: Add JH7110 AON PMU support
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 1:53 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
dphy rx/tx power switch.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 1 +
drivers/soc/starfive/jh71xx_pmu.c | 57 ++++++++++++++++++++++++++++---
2 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4c0b39c44957..ce0befe39394 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19939,6 +19939,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h
STARFIVE JH71XX PMU CONTROLLER DRIVER
M: Walker Chen <walker.chen@starfivetech.com>
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/power/starfive*
F: drivers/soc/starfive/jh71xx_pmu.c
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 0dbdcc0d2c91..c7b474409cf7 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -2,7 +2,7 @@
/*
* StarFive JH71XX PMU (Power Management Unit) Controller Driver
*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/interrupt.h>
@@ -24,6 +24,9 @@
#define JH71XX_PMU_EVENT_STATUS 0x88
#define JH71XX_PMU_INT_STATUS 0x8C
+/* aon pmu register offset */
+#define JH71XX_AON_PMU_SWITCH 0x00
+
/* sw encourage cfg */
#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
@@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pmu->lock, flags);
+ val = readl(pmu->base + JH71XX_AON_PMU_SWITCH);
+
+ if (on)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, pmu->base + JH71XX_AON_PMU_SWITCH);
+ spin_unlock_irqrestore(&pmu->lock, flags);
+
+ return 0;
+}
+
static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
@@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (!match_data)
return -EINVAL;
- ret = match_data->pmu_parse_irq(pdev, pmu);
- if (ret) {
- dev_err(dev, "failed to parse irq\n");
- return ret;
+ if (match_data->pmu_parse_irq) {
+ ret = match_data->pmu_parse_irq(pdev, pmu);
+ if (ret) {
+ dev_err(dev, "failed to parse irq\n");
+ return ret;
+ }
}
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
@@ -394,10 +419,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = {
.pmu_set_state = jh7110_pmu_set_state,
};
+static const struct jh71xx_domain_info jh7110_aon_power_domains[] = {
+ [JH7110_PD_DPHY_TX] = {
+ .name = "DPHY-TX",
+ .bit = 30,
+ },
+ [JH7110_PD_DPHY_RX] = {
+ .name = "DPHY-RX",
+ .bit = 31,
+ },
+};
+
+static const struct jh71xx_pmu_match_data jh7110_aon_pmu = {
+ .num_domains = ARRAY_SIZE(jh7110_aon_power_domains),
+ .domain_info = jh7110_aon_power_domains,
+ .pmu_status = JH71XX_AON_PMU_SWITCH,
+ .pmu_set_state = jh7110_aon_pmu_set_state,
+};
+
static const struct of_device_id jh71xx_pmu_of_match[] = {
{
.compatible = "starfive,jh7110-pmu",
.data = (void *)&jh7110_pmu,
+ }, {
+ .compatible = "starfive,jh7110-aon-syscon",
+ .data = (void *)&jh7110_aon_pmu,
}, {
/* sentinel */
}
@@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu_driver = {
builtin_platform_driver(jh71xx_pmu_driver);
MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 4/5] soc: starfive: Add JH7110 AON PMU support
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
dphy rx/tx power switch.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 1 +
drivers/soc/starfive/jh71xx_pmu.c | 57 ++++++++++++++++++++++++++++---
2 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4c0b39c44957..ce0befe39394 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19939,6 +19939,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h
STARFIVE JH71XX PMU CONTROLLER DRIVER
M: Walker Chen <walker.chen@starfivetech.com>
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/power/starfive*
F: drivers/soc/starfive/jh71xx_pmu.c
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 0dbdcc0d2c91..c7b474409cf7 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -2,7 +2,7 @@
/*
* StarFive JH71XX PMU (Power Management Unit) Controller Driver
*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/interrupt.h>
@@ -24,6 +24,9 @@
#define JH71XX_PMU_EVENT_STATUS 0x88
#define JH71XX_PMU_INT_STATUS 0x8C
+/* aon pmu register offset */
+#define JH71XX_AON_PMU_SWITCH 0x00
+
/* sw encourage cfg */
#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
@@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pmu->lock, flags);
+ val = readl(pmu->base + JH71XX_AON_PMU_SWITCH);
+
+ if (on)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, pmu->base + JH71XX_AON_PMU_SWITCH);
+ spin_unlock_irqrestore(&pmu->lock, flags);
+
+ return 0;
+}
+
static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
@@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (!match_data)
return -EINVAL;
- ret = match_data->pmu_parse_irq(pdev, pmu);
- if (ret) {
- dev_err(dev, "failed to parse irq\n");
- return ret;
+ if (match_data->pmu_parse_irq) {
+ ret = match_data->pmu_parse_irq(pdev, pmu);
+ if (ret) {
+ dev_err(dev, "failed to parse irq\n");
+ return ret;
+ }
}
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
@@ -394,10 +419,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = {
.pmu_set_state = jh7110_pmu_set_state,
};
+static const struct jh71xx_domain_info jh7110_aon_power_domains[] = {
+ [JH7110_PD_DPHY_TX] = {
+ .name = "DPHY-TX",
+ .bit = 30,
+ },
+ [JH7110_PD_DPHY_RX] = {
+ .name = "DPHY-RX",
+ .bit = 31,
+ },
+};
+
+static const struct jh71xx_pmu_match_data jh7110_aon_pmu = {
+ .num_domains = ARRAY_SIZE(jh7110_aon_power_domains),
+ .domain_info = jh7110_aon_power_domains,
+ .pmu_status = JH71XX_AON_PMU_SWITCH,
+ .pmu_set_state = jh7110_aon_pmu_set_state,
+};
+
static const struct of_device_id jh71xx_pmu_of_match[] = {
{
.compatible = "starfive,jh7110-pmu",
.data = (void *)&jh7110_pmu,
+ }, {
+ .compatible = "starfive,jh7110-aon-syscon",
+ .data = (void *)&jh7110_aon_pmu,
}, {
/* sentinel */
}
@@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu_driver = {
builtin_platform_driver(jh71xx_pmu_driver);
MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 5/5] riscv: dts: starfive: jh7110: Add AON PMU node
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 1:53 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU node to configure power. It can be used to turn on/off dphy
rx/tx power switch. It also can use syscon operation.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..d31257d4dcfc 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -486,6 +486,12 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 5/5] riscv: dts: starfive: jh7110: Add AON PMU node
@ 2023-05-10 1:53 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 1:53 UTC (permalink / raw
To: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Walker Chen, Changhuang Liang, Hal Feng, devicetree, linux-kernel,
linux-riscv
Add AON PMU node to configure power. It can be used to turn on/off dphy
rx/tx power switch. It also can use syscon operation.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..d31257d4dcfc 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -486,6 +486,12 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 6:51 ` Walker Chen
-1 siblings, 0 replies; 22+ messages in thread
From: Walker Chen @ 2023-05-10 6:51 UTC (permalink / raw
To: Changhuang Liang, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/10 9:53, Changhuang Liang wrote:
> Move JH7110 private operation into private data of compatible. Convenient
> to add AON PMU which would not have interrupts property.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Thanks!
> ---
> drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++----------
> 1 file changed, 62 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
> index 7d5f50d71c0d..0dbdcc0d2c91 100644
> --- a/drivers/soc/starfive/jh71xx_pmu.c
> +++ b/drivers/soc/starfive/jh71xx_pmu.c
> @@ -51,9 +51,17 @@ struct jh71xx_domain_info {
> u8 bit;
> };
>
> +struct jh71xx_pmu;
> +struct jh71xx_pmu_dev;
> +
> struct jh71xx_pmu_match_data {
> const struct jh71xx_domain_info *domain_info;
> int num_domains;
> + unsigned int pmu_status;
> + int (*pmu_parse_irq)(struct platform_device *pdev,
> + struct jh71xx_pmu *pmu);
> + int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd,
> + u32 mask, bool on);
> };
>
> struct jh71xx_pmu {
> @@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o
> if (!mask)
> return -EINVAL;
>
> - *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
> + *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask;
>
> return 0;
> }
>
> -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> +static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> {
> struct jh71xx_pmu *pmu = pmd->pmu;
> unsigned long flags;
> @@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> u32 mode;
> u32 encourage_lo;
> u32 encourage_hi;
> - bool is_on;
> int ret;
>
> - ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
> - if (ret) {
> - dev_dbg(pmu->dev, "unable to get current state for %s\n",
> - pmd->genpd.name);
> - return ret;
> - }
> -
> - if (is_on == on) {
> - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
> - pmd->genpd.name, on ? "en" : "dis");
> - return 0;
> - }
> -
> spin_lock_irqsave(&pmu->lock, flags);
>
> /*
> @@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> return 0;
> }
>
> +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> +{
> + struct jh71xx_pmu *pmu = pmd->pmu;
> + const struct jh71xx_pmu_match_data *match_data = pmu->match_data;
> + bool is_on;
> + int ret;
> +
> + ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
> + if (ret) {
> + dev_dbg(pmu->dev, "unable to get current state for %s\n",
> + pmd->genpd.name);
> + return ret;
> + }
> +
> + if (is_on == on) {
> + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
> + pmd->genpd.name, on ? "en" : "dis");
> + return 0;
> + }
> +
> + return match_data->pmu_set_state(pmd, mask, on);
> +}
> +
> static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
> {
> struct jh71xx_pmu_dev *pmd = container_of(genpd,
> @@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
> return IRQ_HANDLED;
> }
>
> +static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + pmu->irq = platform_get_irq(pdev, 0);
> + if (pmu->irq < 0)
> + return pmu->irq;
> +
> + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
> + 0, pdev->name, pmu);
> + if (ret)
> + dev_err(dev, "failed to request irq\n");
> +
> + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
> +
> + return 0;
> +}
> +
> static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
> {
> struct jh71xx_pmu_dev *pmd;
> @@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
> if (IS_ERR(pmu->base))
> return PTR_ERR(pmu->base);
>
> - pmu->irq = platform_get_irq(pdev, 0);
> - if (pmu->irq < 0)
> - return pmu->irq;
> -
> - ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
> - 0, pdev->name, pmu);
> - if (ret)
> - dev_err(dev, "failed to request irq\n");
> + spin_lock_init(&pmu->lock);
>
> match_data = of_device_get_match_data(dev);
> if (!match_data)
> return -EINVAL;
>
> + ret = match_data->pmu_parse_irq(pdev, pmu);
> + if (ret) {
> + dev_err(dev, "failed to parse irq\n");
> + return ret;
> + }
> +
> pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
> sizeof(struct generic_pm_domain *),
> GFP_KERNEL);
> @@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
> }
> }
>
> - spin_lock_init(&pmu->lock);
> - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
> -
> ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
> if (ret) {
> dev_err(dev, "failed to register genpd driver: %d\n", ret);
> @@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
> static const struct jh71xx_pmu_match_data jh7110_pmu = {
> .num_domains = ARRAY_SIZE(jh7110_power_domains),
> .domain_info = jh7110_power_domains,
> + .pmu_status = JH71XX_PMU_CURR_POWER_MODE,
> + .pmu_parse_irq = jh7110_pmu_parse_irq,
> + .pmu_set_state = jh7110_pmu_set_state,
> };
>
> static const struct of_device_id jh71xx_pmu_of_match[] = {
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations
@ 2023-05-10 6:51 ` Walker Chen
0 siblings, 0 replies; 22+ messages in thread
From: Walker Chen @ 2023-05-10 6:51 UTC (permalink / raw
To: Changhuang Liang, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/10 9:53, Changhuang Liang wrote:
> Move JH7110 private operation into private data of compatible. Convenient
> to add AON PMU which would not have interrupts property.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Thanks!
> ---
> drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++----------
> 1 file changed, 62 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
> index 7d5f50d71c0d..0dbdcc0d2c91 100644
> --- a/drivers/soc/starfive/jh71xx_pmu.c
> +++ b/drivers/soc/starfive/jh71xx_pmu.c
> @@ -51,9 +51,17 @@ struct jh71xx_domain_info {
> u8 bit;
> };
>
> +struct jh71xx_pmu;
> +struct jh71xx_pmu_dev;
> +
> struct jh71xx_pmu_match_data {
> const struct jh71xx_domain_info *domain_info;
> int num_domains;
> + unsigned int pmu_status;
> + int (*pmu_parse_irq)(struct platform_device *pdev,
> + struct jh71xx_pmu *pmu);
> + int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd,
> + u32 mask, bool on);
> };
>
> struct jh71xx_pmu {
> @@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o
> if (!mask)
> return -EINVAL;
>
> - *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
> + *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask;
>
> return 0;
> }
>
> -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> +static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> {
> struct jh71xx_pmu *pmu = pmd->pmu;
> unsigned long flags;
> @@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> u32 mode;
> u32 encourage_lo;
> u32 encourage_hi;
> - bool is_on;
> int ret;
>
> - ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
> - if (ret) {
> - dev_dbg(pmu->dev, "unable to get current state for %s\n",
> - pmd->genpd.name);
> - return ret;
> - }
> -
> - if (is_on == on) {
> - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
> - pmd->genpd.name, on ? "en" : "dis");
> - return 0;
> - }
> -
> spin_lock_irqsave(&pmu->lock, flags);
>
> /*
> @@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> return 0;
> }
>
> +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
> +{
> + struct jh71xx_pmu *pmu = pmd->pmu;
> + const struct jh71xx_pmu_match_data *match_data = pmu->match_data;
> + bool is_on;
> + int ret;
> +
> + ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
> + if (ret) {
> + dev_dbg(pmu->dev, "unable to get current state for %s\n",
> + pmd->genpd.name);
> + return ret;
> + }
> +
> + if (is_on == on) {
> + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
> + pmd->genpd.name, on ? "en" : "dis");
> + return 0;
> + }
> +
> + return match_data->pmu_set_state(pmd, mask, on);
> +}
> +
> static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
> {
> struct jh71xx_pmu_dev *pmd = container_of(genpd,
> @@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
> return IRQ_HANDLED;
> }
>
> +static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + pmu->irq = platform_get_irq(pdev, 0);
> + if (pmu->irq < 0)
> + return pmu->irq;
> +
> + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
> + 0, pdev->name, pmu);
> + if (ret)
> + dev_err(dev, "failed to request irq\n");
> +
> + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
> +
> + return 0;
> +}
> +
> static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
> {
> struct jh71xx_pmu_dev *pmd;
> @@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
> if (IS_ERR(pmu->base))
> return PTR_ERR(pmu->base);
>
> - pmu->irq = platform_get_irq(pdev, 0);
> - if (pmu->irq < 0)
> - return pmu->irq;
> -
> - ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
> - 0, pdev->name, pmu);
> - if (ret)
> - dev_err(dev, "failed to request irq\n");
> + spin_lock_init(&pmu->lock);
>
> match_data = of_device_get_match_data(dev);
> if (!match_data)
> return -EINVAL;
>
> + ret = match_data->pmu_parse_irq(pdev, pmu);
> + if (ret) {
> + dev_err(dev, "failed to parse irq\n");
> + return ret;
> + }
> +
> pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
> sizeof(struct generic_pm_domain *),
> GFP_KERNEL);
> @@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
> }
> }
>
> - spin_lock_init(&pmu->lock);
> - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
> -
> ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
> if (ret) {
> dev_err(dev, "failed to register genpd driver: %d\n", ret);
> @@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
> static const struct jh71xx_pmu_match_data jh7110_pmu = {
> .num_domains = ARRAY_SIZE(jh7110_power_domains),
> .domain_info = jh7110_power_domains,
> + .pmu_status = JH71XX_PMU_CURR_POWER_MODE,
> + .pmu_parse_irq = jh7110_pmu_parse_irq,
> + .pmu_set_state = jh7110_pmu_set_state,
> };
>
> static const struct of_device_id jh71xx_pmu_of_match[] = {
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
2023-05-10 1:53 ` Changhuang Liang
@ 2023-05-10 7:06 ` Conor Dooley
-1 siblings, 0 replies; 22+ messages in thread
From: Conor Dooley @ 2023-05-10 7:06 UTC (permalink / raw
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1816 bytes --]
On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
> Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
> rx/tx power switch, and it don't need the property of interrupts. It
> also can use syscon operation.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../bindings/power/starfive,jh7110-pmu.yaml | 28 +++++++++++++++++--
> .../dt-bindings/power/starfive,jh7110-pmu.h | 5 +++-
> 2 files changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> index 98eb8b4110e7..0591a4e9db6c 100644
> --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit
>
> maintainers:
> - Walker Chen <walker.chen@starfivetech.com>
> + - Changhuang Liang <changhuang.liang@starfivetech.com>
>
> description: |
> StarFive JH7110 SoC includes support for multiple power domains which can be
> @@ -15,8 +16,13 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - starfive,jh7110-pmu
> + oneOf:
> + - enum:
> + - starfive,jh7110-pmu
> + - items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - const: syscon
Unfortunately, this is not what was wanted.
This syscon, of which power domain control is just one of the things that
it can do, should be documented in
Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
alongside it's brethern "starfive,jh7110-sys-syscon" &
"starfive,jh7110-stg-syscon".
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
@ 2023-05-10 7:06 ` Conor Dooley
0 siblings, 0 replies; 22+ messages in thread
From: Conor Dooley @ 2023-05-10 7:06 UTC (permalink / raw
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 1816 bytes --]
On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
> Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
> rx/tx power switch, and it don't need the property of interrupts. It
> also can use syscon operation.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../bindings/power/starfive,jh7110-pmu.yaml | 28 +++++++++++++++++--
> .../dt-bindings/power/starfive,jh7110-pmu.h | 5 +++-
> 2 files changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> index 98eb8b4110e7..0591a4e9db6c 100644
> --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
> @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit
>
> maintainers:
> - Walker Chen <walker.chen@starfivetech.com>
> + - Changhuang Liang <changhuang.liang@starfivetech.com>
>
> description: |
> StarFive JH7110 SoC includes support for multiple power domains which can be
> @@ -15,8 +16,13 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - starfive,jh7110-pmu
> + oneOf:
> + - enum:
> + - starfive,jh7110-pmu
> + - items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - const: syscon
Unfortunately, this is not what was wanted.
This syscon, of which power domain control is just one of the things that
it can do, should be documented in
Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
alongside it's brethern "starfive,jh7110-sys-syscon" &
"starfive,jh7110-stg-syscon".
Thanks,
Conor.
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linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
2023-05-10 7:06 ` Conor Dooley
@ 2023-05-10 7:20 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 7:20 UTC (permalink / raw
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/10 15:06, Conor Dooley wrote:
> On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
>> + - starfive,jh7110-pmu
>> + - items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - const: syscon
>
> Unfortunately, this is not what was wanted.
> This syscon, of which power domain control is just one of the things that
> it can do, should be documented in
> Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> alongside it's brethern "starfive,jh7110-sys-syscon" &
> "starfive,jh7110-stg-syscon".
>
That means that I don't need to modify this original yaml file?
I just need to move current changes in this patch into
"Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
Thanks,
Changhuang
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
@ 2023-05-10 7:20 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-10 7:20 UTC (permalink / raw
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Emil Renner Berthing,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/10 15:06, Conor Dooley wrote:
> On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
>> + - starfive,jh7110-pmu
>> + - items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - const: syscon
>
> Unfortunately, this is not what was wanted.
> This syscon, of which power domain control is just one of the things that
> it can do, should be documented in
> Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> alongside it's brethern "starfive,jh7110-sys-syscon" &
> "starfive,jh7110-stg-syscon".
>
That means that I don't need to modify this original yaml file?
I just need to move current changes in this patch into
"Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
Thanks,
Changhuang
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
2023-05-10 7:20 ` Changhuang Liang
@ 2023-05-10 19:51 ` Conor Dooley
-1 siblings, 0 replies; 22+ messages in thread
From: Conor Dooley @ 2023-05-10 19:51 UTC (permalink / raw
To: Changhuang Liang
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 1240 bytes --]
On Wed, May 10, 2023 at 03:20:14PM +0800, Changhuang Liang wrote:
> On 2023/5/10 15:06, Conor Dooley wrote:
> > On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
> >> + - starfive,jh7110-pmu
> >> + - items:
> >> + - enum:
> >> + - starfive,jh7110-aon-syscon
> >> + - const: syscon
> >
> > Unfortunately, this is not what was wanted.
> > This syscon, of which power domain control is just one of the things that
> > it can do, should be documented in
> > Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > alongside it's brethern "starfive,jh7110-sys-syscon" &
> > "starfive,jh7110-stg-syscon".
> >
>
> That means that I don't need to modify this original yaml file?
Does "this original" mean starfive,jh7100-pmu.yaml?
If so then...
> I just need to move current changes in this patch into
> "Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
Correct.
It makes most sense for that binding, as it depends on the pll binding
(because it has a ref: to it), to go through the clock tree in Xingyu's
series.
I'll apply the driver changes once the binding has been applied.
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
@ 2023-05-10 19:51 ` Conor Dooley
0 siblings, 0 replies; 22+ messages in thread
From: Conor Dooley @ 2023-05-10 19:51 UTC (permalink / raw
To: Changhuang Liang
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]
On Wed, May 10, 2023 at 03:20:14PM +0800, Changhuang Liang wrote:
> On 2023/5/10 15:06, Conor Dooley wrote:
> > On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
> >> + - starfive,jh7110-pmu
> >> + - items:
> >> + - enum:
> >> + - starfive,jh7110-aon-syscon
> >> + - const: syscon
> >
> > Unfortunately, this is not what was wanted.
> > This syscon, of which power domain control is just one of the things that
> > it can do, should be documented in
> > Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > alongside it's brethern "starfive,jh7110-sys-syscon" &
> > "starfive,jh7110-stg-syscon".
> >
>
> That means that I don't need to modify this original yaml file?
Does "this original" mean starfive,jh7100-pmu.yaml?
If so then...
> I just need to move current changes in this patch into
> "Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
Correct.
It makes most sense for that binding, as it depends on the pll binding
(because it has a ref: to it), to go through the clock tree in Xingyu's
series.
I'll apply the driver changes once the binding has been applied.
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
2023-05-10 19:51 ` Conor Dooley
@ 2023-05-11 2:06 ` Changhuang Liang
-1 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-11 2:06 UTC (permalink / raw
To: Conor Dooley
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/11 3:51, Conor Dooley wrote:
> On Wed, May 10, 2023 at 03:20:14PM +0800, Changhuang Liang wrote:
>> On 2023/5/10 15:06, Conor Dooley wrote:
>>> On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
>>>> + - starfive,jh7110-pmu
>>>> + - items:
>>>> + - enum:
>>>> + - starfive,jh7110-aon-syscon
>>>> + - const: syscon
>>>
>>> Unfortunately, this is not what was wanted.
>>> This syscon, of which power domain control is just one of the things that
>>> it can do, should be documented in
>>> Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> alongside it's brethern "starfive,jh7110-sys-syscon" &
>>> "starfive,jh7110-stg-syscon".
>>>
>>
>> That means that I don't need to modify this original yaml file?
>
> Does "this original" mean starfive,jh7100-pmu.yaml?
> If so then...
>
Yes.
>> I just need to move current changes in this patch into
>> "Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
>
> Correct.
> It makes most sense for that binding, as it depends on the pll binding
> (because it has a ref: to it), to go through the clock tree in Xingyu's
> series.
> I'll apply the driver changes once the binding has been applied.
>
I think that I have to send v4 after Xingyu's series resend new version.
If drivers have no other comments. I will make the following changes:
patch 1/5: Only keep the content in starfive,jh7110-pmu.h, move other content into Xingyu's PLL series.
patch 5/5: Drop this patch, move the content into Xingyu's PLL series.
other patch: no change.
Thanks,
Changhuang
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support
@ 2023-05-11 2:06 ` Changhuang Liang
0 siblings, 0 replies; 22+ messages in thread
From: Changhuang Liang @ 2023-05-11 2:06 UTC (permalink / raw
To: Conor Dooley
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Emil Renner Berthing, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Walker Chen, Hal Feng, devicetree, linux-kernel, linux-riscv
On 2023/5/11 3:51, Conor Dooley wrote:
> On Wed, May 10, 2023 at 03:20:14PM +0800, Changhuang Liang wrote:
>> On 2023/5/10 15:06, Conor Dooley wrote:
>>> On Tue, May 09, 2023 at 06:53:07PM -0700, Changhuang Liang wrote:
>>>> + - starfive,jh7110-pmu
>>>> + - items:
>>>> + - enum:
>>>> + - starfive,jh7110-aon-syscon
>>>> + - const: syscon
>>>
>>> Unfortunately, this is not what was wanted.
>>> This syscon, of which power domain control is just one of the things that
>>> it can do, should be documented in
>>> Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> alongside it's brethern "starfive,jh7110-sys-syscon" &
>>> "starfive,jh7110-stg-syscon".
>>>
>>
>> That means that I don't need to modify this original yaml file?
>
> Does "this original" mean starfive,jh7100-pmu.yaml?
> If so then...
>
Yes.
>> I just need to move current changes in this patch into
>> "Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml"?
>
> Correct.
> It makes most sense for that binding, as it depends on the pll binding
> (because it has a ref: to it), to go through the clock tree in Xingyu's
> series.
> I'll apply the driver changes once the binding has been applied.
>
I think that I have to send v4 after Xingyu's series resend new version.
If drivers have no other comments. I will make the following changes:
patch 1/5: Only keep the content in starfive,jh7110-pmu.h, move other content into Xingyu's PLL series.
patch 5/5: Drop this patch, move the content into Xingyu's PLL series.
other patch: no change.
Thanks,
Changhuang
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-05-11 2:07 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-10 1:53 [PATCH v3 0/5] Add JH7110 AON PMU support Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
2023-05-10 1:53 ` [PATCH v3 1/5] dt-bindings: power: " Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
2023-05-10 7:06 ` Conor Dooley
2023-05-10 7:06 ` Conor Dooley
2023-05-10 7:20 ` Changhuang Liang
2023-05-10 7:20 ` Changhuang Liang
2023-05-10 19:51 ` Conor Dooley
2023-05-10 19:51 ` Conor Dooley
2023-05-11 2:06 ` Changhuang Liang
2023-05-11 2:06 ` Changhuang Liang
2023-05-10 1:53 ` [PATCH v3 2/5] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
2023-05-10 1:53 ` [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
2023-05-10 6:51 ` Walker Chen
2023-05-10 6:51 ` Walker Chen
2023-05-10 1:53 ` [PATCH v3 4/5] soc: starfive: Add JH7110 AON PMU support Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
2023-05-10 1:53 ` [PATCH v3 5/5] riscv: dts: starfive: jh7110: Add AON PMU node Changhuang Liang
2023-05-10 1:53 ` Changhuang Liang
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