* [PATCH 00/18] drm/i915: PLL refactoring
@ 2024-04-12 18:26 Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
` (22 more replies)
0 siblings, 23 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A bunch of refactoring around PLLs. Main feature is
the unionization of dpll_hw_state. The eventual goal
is to unify the approach for PLLs across all platforms
instead of the current "shared PLLs are somehow
different than other PLLs" approach.
Ville Syrjälä (18):
drm/i915: Replace hand rolled PLL state dump with
intel_dpll_dump_hw_state()
drm/i915: Use printer for the rest of PLL debugfs dump
drm/i915: Rename PLL hw_state variables/arguments
drm/i915: Introduce some local PLL state variables
drm/i915: Extract ilk_fb_cb_factor()
drm/i915: Extract ilk_dpll_compute_fp()
drm/i915: Extract i9xx_dpll_get_hw_state()
drm/i915: Pass the PLL hw_state to pll->enable()
drm/i915: Extract i965_dpll_md()
drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
drm/i915: Modernize i9xx_pll_refclk()
drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
drm/i915: Add local DPLL 'hw_state' variables
drm/i915: Carve up struct intel_dpll_hw_state
drm/i915: Unionize dpll_hw_state
drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 30 +-
.../drm/i915/display/intel_display_debugfs.c | 39 +-
.../drm/i915/display/intel_display_types.h | 43 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 338 +++++++-----
drivers/gpu/drm/i915/display/intel_dpll.h | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 489 ++++++++++--------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 80 ++-
.../gpu/drm/i915/display/intel_pch_display.c | 4 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 +-
11 files changed, 581 insertions(+), 488 deletions(-)
--
2.43.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
` (21 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just use intel_dpll_dump_hw_state() instead of hand rolling it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 31 ++-----------------
1 file changed, 2 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0feffe8d4e45..73be72bf3f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -638,6 +638,7 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct drm_printer p = drm_seq_file_printer(m);
struct intel_shared_dpll *pll;
int i;
@@ -654,35 +655,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
pll->state.pipe_mask, pll->active_mask,
str_yes_no(pll->on));
seq_printf(m, " tracked hardware state:\n");
- seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
- seq_printf(m, " dpll_md: 0x%08x\n",
- pll->state.hw_state.dpll_md);
- seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
- seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
- seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
- seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
- seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
- seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0);
- seq_printf(m, " mg_refclkin_ctl: 0x%08x\n",
- pll->state.hw_state.mg_refclkin_ctl);
- seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_coreclkctl1);
- seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_hsclkctl);
- seq_printf(m, " mg_pll_div0: 0x%08x\n",
- pll->state.hw_state.mg_pll_div0);
- seq_printf(m, " mg_pll_div1: 0x%08x\n",
- pll->state.hw_state.mg_pll_div1);
- seq_printf(m, " mg_pll_lf: 0x%08x\n",
- pll->state.hw_state.mg_pll_lf);
- seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
- pll->state.hw_state.mg_pll_frac_lock);
- seq_printf(m, " mg_pll_ssc: 0x%08x\n",
- pll->state.hw_state.mg_pll_ssc);
- seq_printf(m, " mg_pll_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_bias);
- seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_tdc_coldst_bias);
+ intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
}
drm_modeset_unlock_all(&dev_priv->drm);
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
` (20 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Since we now have the printer around for intel_dpll_dump_hw_state()
use it for all the other PLL prints as well. Just to make the thing
looks less crazy.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 73be72bf3f5c..35f9f86ef70f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -644,17 +644,17 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
drm_modeset_lock_all(&dev_priv->drm);
- seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
+ drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
dev_priv->display.dpll.ref_clks.nssc,
dev_priv->display.dpll.ref_clks.ssc);
for_each_shared_dpll(dev_priv, pll, i) {
- seq_printf(m, "DPLL%i: %s, id: %i\n", pll->index,
+ drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
pll->info->name, pll->info->id);
- seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
+ drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
pll->state.pipe_mask, pll->active_mask,
str_yes_no(pll->on));
- seq_printf(m, " tracked hardware state:\n");
+ drm_printf(&p, " tracked hardware state:\n");
intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
}
drm_modeset_unlock_all(&dev_priv->drm);
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
` (19 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have zero consistency in out PLL state naming scheme. Try
to unify things a bit by using 'dpll_hw_state' for high level
stuff and just 'hw_state' for low level stuff. Currently both
are the same, but I want to unionize intel_dpll_hw_state at
which point using different names can make it more clear whether
we're talking about the whole union or just the embedded platform
specific struct.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 223 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +-
2 files changed, 115 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9ff6c4cc2e4b..5203c538672c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -81,7 +81,7 @@ struct intel_shared_dpll_funcs {
*/
bool (*get_hw_state)(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state);
/*
* Hook for calculating the pll's output frequency based on its passed
@@ -89,7 +89,7 @@ struct intel_shared_dpll_funcs {
*/
int (*get_freq)(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state);
+ const struct intel_dpll_hw_state *dpll_hw_state);
};
struct intel_dpll_mgr {
@@ -108,7 +108,7 @@ struct intel_dpll_mgr {
struct intel_encoder *encoder);
void (*update_ref_clks)(struct drm_i915_private *i915);
void (*dump_hw_state)(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state);
+ const struct intel_dpll_hw_state *dpll_hw_state);
bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b);
};
@@ -352,7 +352,7 @@ intel_dpll_mask_all(struct drm_i915_private *i915)
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_dpll_hw_state *pll_state,
+ const struct intel_dpll_hw_state *dpll_hw_state,
unsigned long dpll_mask)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -379,9 +379,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
continue;
}
- if (memcmp(pll_state,
+ if (memcmp(dpll_hw_state,
&shared_dpll[pll->index].hw_state,
- sizeof(*pll_state)) == 0) {
+ sizeof(*dpll_hw_state)) == 0) {
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
@@ -430,14 +430,14 @@ static void
intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_shared_dpll_state *shared_dpll;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
if (shared_dpll[pll->index].pipe_mask == 0)
- shared_dpll[pll->index].hw_state = *pll_state;
+ shared_dpll[pll->index].hw_state = *dpll_hw_state;
intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
}
@@ -974,11 +974,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int refclk;
int n, p, r;
- u32 wrpll = pll_state->wrpll;
+ u32 wrpll = hw_state->wrpll;
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
@@ -1098,7 +1098,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int link_clock = 0;
@@ -1149,11 +1149,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int link_clock = 0;
- switch (pll_state->spll & SPLL_FREQ_MASK) {
+ switch (hw_state->spll & SPLL_FREQ_MASK) {
case SPLL_FREQ_810MHz:
link_clock = 81000;
break;
@@ -1694,16 +1694,16 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int ref_clock = i915->display.dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
- p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
- p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
+ p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
+ p2 = hw_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
- if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
- p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
+ if (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
+ p1 = (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
else
p1 = 1;
@@ -1751,10 +1751,10 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
return 0;
}
- dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
+ dco_freq = (hw_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
ref_clock;
- dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
+ dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
ref_clock / 0x8000;
if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
@@ -1842,11 +1842,11 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int link_clock = 0;
- switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
+ switch ((hw_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
case DPLL_CTRL1_LINK_RATE_810:
link_clock = 81000;
@@ -1920,16 +1920,16 @@ static int skl_get_dpll(struct intel_atomic_state *state,
static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
- if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(i915, pll, pll_state);
+ if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
+ return skl_ddi_wrpll_get_freq(i915, pll, hw_state);
else
- return skl_ddi_lcpll_get_freq(i915, pll, pll_state);
+ return skl_ddi_lcpll_get_freq(i915, pll, hw_state);
}
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2241,7 +2241,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
const struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
int clock = crtc_state->port_clock;
int vco = clk_div->vco;
u32 prop_coef, int_coef, gain_ctl, targ_cnt;
@@ -2279,45 +2279,46 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
else
lanestagger = 0x02;
- dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
- dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
- dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
- dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
+ hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
+ hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
+ hw_state->pll1 = PORT_PLL_N(clk_div->n);
+ hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
if (clk_div->m2 & 0x3fffff)
- dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
+ hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
- dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
+ hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
PORT_PLL_INT_COEFF(int_coef) |
PORT_PLL_GAIN_CTL(gain_ctl);
- dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
+ hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
- dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
+ hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
- dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
+ hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
PORT_PLL_DCO_AMP_OVR_EN_H;
- dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
+ hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
- dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
+ hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
return 0;
}
static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
struct dpll clock;
clock.m1 = 2;
- clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22;
- if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
- clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
- clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1);
- clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
- clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
+ clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22;
+ if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
+ clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
+ hw_state->pll2);
+ clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1);
+ clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
+ clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
}
@@ -2695,7 +2696,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
/*
* The PLL outputs multiple frequencies at the same time, selection is
@@ -2766,17 +2767,17 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
int ref_clock = icl_wrpll_ref_clock(i915);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
- p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
- p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+ p0 = hw_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+ p2 = hw_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
- if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
- p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+ if (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+ p1 = (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
DPLL_CFGCR1_QDIV_RATIO_SHIFT;
else
p1 = 1;
@@ -2808,10 +2809,10 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
break;
}
- dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
+ dco_freq = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
ref_clock;
- dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
if (ehl_combo_pll_div_frac_wa_needed(i915))
@@ -2827,33 +2828,33 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
static void icl_calc_dpll_state(struct drm_i915_private *i915,
const struct skl_wrpll_params *pll_params,
- struct intel_dpll_hw_state *pll_state)
+ struct intel_dpll_hw_state *hw_state)
{
u32 dco_fraction = pll_params->dco_fraction;
if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
- pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
+ hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
pll_params->dco_integer;
- pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
+ hw_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params->kdiv) |
DPLL_CFGCR1_PDIV(pll_params->pdiv);
if (DISPLAY_VER(i915) >= 12)
- pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
else
- pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
+ hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
if (i915->display.vbt.override_afc_startup)
- pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
+ hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
}
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
- struct intel_dpll_hw_state *state,
+ struct intel_dpll_hw_state *hw_state,
bool is_dkl)
{
static const u8 div1_vals[] = { 7, 5, 3, 2 };
@@ -2909,12 +2910,12 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
*target_dco_khz = dco;
- state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
+ hw_state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
- state->mg_clktop2_coreclkctl1 =
+ hw_state->mg_clktop2_coreclkctl1 =
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
- state->mg_clktop2_hsclkctl =
+ hw_state->mg_clktop2_hsclkctl =
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
hsdiv |
@@ -2932,7 +2933,7 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* adapted to integer-only calculation, that's why it looks so different.
*/
static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *pll_state)
+ struct intel_dpll_hw_state *hw_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
int refclk_khz = i915->display.dpll.ref_clks.nssc;
@@ -2949,7 +2950,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
int ret;
ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
- pll_state, is_dkl);
+ hw_state, is_dkl);
if (ret)
return ret;
@@ -3039,61 +3040,61 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
/* write pll_state calculations */
if (is_dkl) {
- pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
+ hw_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
DKL_PLL_DIV0_FBPREDIV(m1div) |
DKL_PLL_DIV0_FBDIV_INT(m2div_int);
if (i915->display.vbt.override_afc_startup) {
u8 val = i915->display.vbt.override_afc_startup_val;
- pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
+ hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
}
- pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
+ hw_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
- pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
+ hw_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
(use_ssc ? DKL_PLL_SSC_EN : 0);
- pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
+ hw_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
- pll_state->mg_pll_tdc_coldst_bias =
+ hw_state->mg_pll_tdc_coldst_bias =
DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
} else {
- pll_state->mg_pll_div0 =
+ hw_state->mg_pll_div0 =
(m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
MG_PLL_DIV0_FBDIV_INT(m2div_int);
- pll_state->mg_pll_div1 =
+ hw_state->mg_pll_div1 =
MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
MG_PLL_DIV1_DITHER_DIV_2 |
MG_PLL_DIV1_NDIVRATIO(1) |
MG_PLL_DIV1_FBPREDIV(m1div);
- pll_state->mg_pll_lf =
+ hw_state->mg_pll_lf =
MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
MG_PLL_LF_AFCCNTSEL_512 |
MG_PLL_LF_GAINCTRL(1) |
MG_PLL_LF_INT_COEFF(int_coeff) |
MG_PLL_LF_PROP_COEFF(prop_coeff);
- pll_state->mg_pll_frac_lock =
+ hw_state->mg_pll_frac_lock =
MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
MG_PLL_FRAC_LOCK_DCODITHEREN |
MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
if (use_ssc || m2div_rem > 0)
- pll_state->mg_pll_frac_lock |=
+ hw_state->mg_pll_frac_lock |=
MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
- pll_state->mg_pll_ssc =
+ hw_state->mg_pll_ssc =
(use_ssc ? MG_PLL_SSC_EN : 0) |
MG_PLL_SSC_TYPE(2) |
MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
@@ -3101,14 +3102,14 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
MG_PLL_SSC_FLLEN |
MG_PLL_SSC_STEPSIZE(ssc_stepsize);
- pll_state->mg_pll_tdc_coldst_bias =
+ hw_state->mg_pll_tdc_coldst_bias =
MG_PLL_TDC_COLDST_COLDSTART |
MG_PLL_TDC_COLDST_IREFINT_EN |
MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
MG_PLL_TDC_TDCOVCCORR_EN |
MG_PLL_TDC_TDCSEL(3);
- pll_state->mg_pll_bias =
+ hw_state->mg_pll_bias =
MG_PLL_BIAS_BIAS_GB_SEL(3) |
MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
MG_PLL_BIAS_BIAS_BONUS(10) |
@@ -3118,17 +3119,17 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
MG_PLL_BIAS_IREFTRIM(iref_trim);
if (refclk_khz == 38400) {
- pll_state->mg_pll_tdc_coldst_bias_mask =
+ hw_state->mg_pll_tdc_coldst_bias_mask =
MG_PLL_TDC_COLDST_COLDSTART;
- pll_state->mg_pll_bias_mask = 0;
+ hw_state->mg_pll_bias_mask = 0;
} else {
- pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
- pll_state->mg_pll_bias_mask = -1U;
+ hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
+ hw_state->mg_pll_bias_mask = -1U;
}
- pll_state->mg_pll_tdc_coldst_bias &=
- pll_state->mg_pll_tdc_coldst_bias_mask;
- pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ hw_state->mg_pll_tdc_coldst_bias &=
+ hw_state->mg_pll_tdc_coldst_bias_mask;
+ hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
}
return 0;
@@ -3136,7 +3137,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *hw_state)
{
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3144,23 +3145,23 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
ref_clock = i915->display.dpll.ref_clks.nssc;
if (DISPLAY_VER(i915) >= 12) {
- m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
+ m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
- m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
+ m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
- if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
- m2_frac = pll_state->mg_pll_bias &
+ if (hw_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
+ m2_frac = hw_state->mg_pll_bias &
DKL_PLL_BIAS_FBDIV_FRAC_MASK;
m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
} else {
m2_frac = 0;
}
} else {
- m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
- m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
+ m1 = hw_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
+ m2_int = hw_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
- if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
- m2_frac = pll_state->mg_pll_div0 &
+ if (hw_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
+ m2_frac = hw_state->mg_pll_div0 &
MG_PLL_DIV0_FBDIV_FRAC_MASK;
m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
} else {
@@ -3168,7 +3169,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
}
}
- switch (pll_state->mg_clktop2_hsclkctl &
+ switch (hw_state->mg_clktop2_hsclkctl &
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
div1 = 2;
@@ -3183,11 +3184,11 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
div1 = 7;
break;
default:
- MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
+ MISSING_CASE(hw_state->mg_clktop2_hsclkctl);
return 0;
}
- div2 = (pll_state->mg_clktop2_hsclkctl &
+ div2 = (hw_state->mg_clktop2_hsclkctl &
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
@@ -4396,33 +4397,33 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
* intel_dpll_get_freq - calculate the DPLL's output frequency
* @i915: i915 device
* @pll: DPLL for which to calculate the output frequency
- * @pll_state: DPLL state from which to calculate the output frequency
+ * @dpll_hw_state: DPLL state from which to calculate the output frequency
*
- * Return the output frequency corresponding to @pll's passed in @pll_state.
+ * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
int intel_dpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(i915, pll, pll_state);
+ return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
}
/**
* intel_dpll_get_hw_state - readout the DPLL's hardware state
* @i915: i915 device
* @pll: DPLL for which to calculate the output frequency
- * @hw_state: DPLL's hardware state
+ * @dpll_hw_state: DPLL's hardware state
*
- * Read out @pll's hardware state into @hw_state.
+ * Read out @pll's hardware state into @dpll_hw_state.
*/
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(i915, pll, hw_state);
+ return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
}
static void readout_dpll_hw_state(struct drm_i915_private *i915,
@@ -4496,21 +4497,21 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
* intel_dpll_dump_hw_state - dump hw_state
* @i915: i915 drm device
* @p: where to print the state to
- * @hw_state: hw state to be dumped
+ * @dpll_hw_state: hw state to be dumped
*
- * Dumo out the relevant values in @hw_state.
+ * Dumo out the relevant values in @dpll_hw_state.
*/
void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
if (i915->display.dpll.mgr) {
- i915->display.dpll.mgr->dump_hw_state(p, hw_state);
+ i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
*/
- ibx_dump_hw_state(p, hw_state);
+ ibx_dump_hw_state(p, dpll_hw_state);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d4d97e40440a..d63d0651b6a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -365,10 +365,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *pll_state);
+ const struct intel_dpll_hw_state *dpll_hw_state);
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
@@ -379,7 +379,7 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915);
void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state);
+ const struct intel_dpll_hw_state *dpll_hw_state);
bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b);
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 04/18] drm/i915: Introduce some local PLL state variables
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (2 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
` (18 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Spinkle local PLL hw_state variables into various low
level PLL functions. Will make subsequent changes cleaner
when we don't have to touch so many places when renaming
struct members and whatnot.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 94 ++++++++++---------
1 file changed, 52 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5203c538672c..51a7d8df0ca3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -555,15 +555,16 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
ibx_assert_pch_refclk_enabled(i915);
- intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0);
- intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1);
+ intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
+ intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
- intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll);
+ intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
/* Wait for the clocks to stabilize. */
intel_de_posting_read(i915, PCH_DPLL(id));
@@ -574,7 +575,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
*
* So write it again.
*/
- intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll);
+ intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
intel_de_posting_read(i915, PCH_DPLL(id));
udelay(200);
}
@@ -678,9 +679,10 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
- intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll);
+ intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
intel_de_posting_read(i915, WRPLL_CTL(id));
udelay(20);
}
@@ -688,7 +690,9 @@ static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
- intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll);
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+
+ intel_de_write(i915, SPLL_CTL, hw_state->spll);
intel_de_posting_read(i915, SPLL_CTL);
udelay(20);
}
@@ -1019,11 +1023,12 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
unsigned int p, n2, r2;
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
- crtc_state->dpll_hw_state.wrpll =
+ hw_state->wrpll =
WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
@@ -1126,11 +1131,12 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
return -EINVAL;
- crtc_state->dpll_hw_state.spll =
+ hw_state->spll =
SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
return 0;
@@ -1333,24 +1339,28 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
intel_de_rmw(i915, DPLL_CTRL1,
- DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id),
- pll->state.hw_state.ctrl1 << (id * 6));
+ DPLL_CTRL1_HDMI_MODE(id) |
+ DPLL_CTRL1_SSC(id) |
+ DPLL_CTRL1_LINK_RATE_MASK(id),
+ hw_state->ctrl1 << (id * 6));
intel_de_posting_read(i915, DPLL_CTRL1);
}
static void skl_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
skl_ddi_pll_write_ctrl1(i915, pll);
- intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
- intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
+ intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
+ intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
intel_de_posting_read(i915, regs[id].cfgcr1);
intel_de_posting_read(i915, regs[id].cfgcr2);
@@ -1766,37 +1776,35 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
struct skl_wrpll_params wrpll_params = {};
- u32 ctrl1, cfgcr1, cfgcr2;
int ret;
- /*
- * See comment in intel_dpll_hw_state to understand why we always use 0
- * as the DPLL id in this function.
- */
- ctrl1 = DPLL_CTRL1_OVERRIDE(0);
-
- ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
-
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
i915->display.dpll.ref_clks.nssc, &wrpll_params);
if (ret)
return ret;
- cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
+ /*
+ * See comment in intel_dpll_hw_state to understand why we always use 0
+ * as the DPLL id in this function.
+ */
+ hw_state->ctrl1 =
+ DPLL_CTRL1_OVERRIDE(0) |
+ DPLL_CTRL1_HDMI_MODE(0);
+
+ hw_state->cfgcr1 =
+ DPLL_CFGCR1_FREQ_ENABLE |
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
wrpll_params.dco_integer;
- cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
+ hw_state->cfgcr2 =
+ DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- crtc_state->dpll_hw_state.ctrl1 = ctrl1;
- crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
- crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
-
crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
&crtc_state->dpll_hw_state);
@@ -1806,6 +1814,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
static int
skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
u32 ctrl1;
/*
@@ -1835,7 +1844,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
break;
}
- crtc_state->dpll_hw_state.ctrl1 = ctrl1;
+ hw_state->ctrl1 = ctrl1;
return 0;
}
@@ -1989,10 +1998,11 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
{
+ const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+ enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
+ enum dpio_phy phy;
+ enum dpio_channel ch;
u32 temp;
- enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
- enum dpio_phy phy;
- enum dpio_channel ch;
bxt_port_to_phy_channel(i915, port, &phy, &ch);
@@ -2015,43 +2025,43 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
/* Write P1 & P2 */
intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
- PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0);
+ PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
/* Write M2 integer */
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
- PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0);
+ PORT_PLL_M2_INT_MASK, hw_state->pll0);
/* Write N */
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
- PORT_PLL_N_MASK, pll->state.hw_state.pll1);
+ PORT_PLL_N_MASK, hw_state->pll1);
/* Write M2 fraction */
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
- PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2);
+ PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
/* Write M2 fraction enable */
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
- PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3);
+ PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
/* Write coeff */
temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
temp &= ~PORT_PLL_PROP_COEFF_MASK;
temp &= ~PORT_PLL_INT_COEFF_MASK;
temp &= ~PORT_PLL_GAIN_CTL_MASK;
- temp |= pll->state.hw_state.pll6;
+ temp |= hw_state->pll6;
intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
/* Write calibration val */
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
- PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8);
+ PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
- PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9);
+ PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
temp &= ~PORT_PLL_DCO_AMP_MASK;
- temp |= pll->state.hw_state.pll10;
+ temp |= hw_state->pll10;
intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
/* Recalibrate with new settings */
@@ -2059,7 +2069,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
temp |= PORT_PLL_RECALIBRATE;
intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
- temp |= pll->state.hw_state.ebb4;
+ temp |= hw_state->ebb4;
intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
/* Enable PLL */
@@ -2083,7 +2093,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
temp &= ~LANE_STAGGER_MASK;
temp &= ~LANESTAGGER_STRAP_OVRD;
- temp |= pll->state.hw_state.pcsdw12;
+ temp |= hw_state->pcsdw12;
intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
}
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (3 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
` (17 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the code to calculate PCH DPLL tuning factor
into its own function. Helps declutter ilk_update_pll_dividers().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 32 ++++++++++++-----------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 3038655377ea..3278ca7a3be0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1192,6 +1192,22 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
+ ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) ||
+ (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(i915))))
+ return 25;
+
+ if (crtc_state->sdvo_tv_clock)
+ return 20;
+
+ return 21;
+}
+
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{
return dpll->m < factor * dpll->n;
@@ -1201,22 +1217,8 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int factor = ilk_fb_cb_factor(crtc_state);
u32 fp, fp2;
- int factor;
-
- /* Enable autotuning of the PLL clock (if permissible) */
- factor = 21;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
- if ((intel_panel_use_ssc(dev_priv) &&
- dev_priv->display.vbt.lvds_ssc_freq == 100000) ||
- (HAS_PCH_IBX(dev_priv) &&
- intel_is_dual_link_lvds(dev_priv)))
- factor = 25;
- } else if (crtc_state->sdvo_tv_clock) {
- factor = 20;
- }
fp = i9xx_dpll_compute_fp(clock);
if (ilk_needs_fb_cb_tune(clock, factor))
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (4 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
` (16 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's not repeat ourselves so much and pull the entire
PCH DPLL FP register value calculation into its own
function.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 24 ++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 3278ca7a3be0..aa46e9e80786 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1213,23 +1213,25 @@ static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
return dpll->m < factor * dpll->n;
}
+static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
+{
+ u32 fp;
+
+ fp = i9xx_dpll_compute_fp(clock);
+ if (ilk_needs_fb_cb_tune(clock, factor))
+ fp |= FP_CB_TUNE;
+
+ return fp;
+}
+
static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
int factor = ilk_fb_cb_factor(crtc_state);
- u32 fp, fp2;
- fp = i9xx_dpll_compute_fp(clock);
- if (ilk_needs_fb_cb_tune(clock, factor))
- fp |= FP_CB_TUNE;
-
- fp2 = i9xx_dpll_compute_fp(reduced_clock);
- if (ilk_needs_fb_cb_tune(reduced_clock, factor))
- fp2 |= FP_CB_TUNE;
-
- crtc_state->dpll_hw_state.fp0 = fp;
- crtc_state->dpll_hw_state.fp1 = fp2;
+ crtc_state->dpll_hw_state.fp0 = ilk_dpll_compute_fp(clock, factor);
+ crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
}
static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (5 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
` (15 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Start making the GMCH DPLL code a bit more like the more modern
platforms by separating out the DPLL hw state readout from the
rest of the pipe readout.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++-------------
drivers/gpu/drm/i915/display/intel_dpll.c | 30 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dpll.h | 3 ++
3 files changed, 37 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92b67adee9c..70ba8a9c671e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3071,19 +3071,16 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pfit_config(pipe_config);
+ i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
+
if (DISPLAY_VER(dev_priv) >= 4) {
- /* No way to read it out on pipes B and C */
- if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
- tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
- else
- tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+ tmp = pipe_config->dpll_hw_state.dpll_md;
pipe_config->pixel_multiplier =
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
- pipe_config->dpll_hw_state.dpll_md = tmp;
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
- tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
+ tmp = pipe_config->dpll_hw_state.dpll;
pipe_config->pixel_multiplier =
((tmp & SDVO_MULTIPLIER_MASK)
>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
@@ -3093,19 +3090,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
* function. */
pipe_config->pixel_multiplier = 1;
}
- pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
- DPLL(crtc->pipe));
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
- pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
- FP0(crtc->pipe));
- pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
- FP1(crtc->pipe));
- } else {
- /* Mask out read-only status bits. */
- pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
- DPLL_PORTC_READY_MASK |
- DPLL_PORTB_READY_MASK);
- }
if (IS_CHERRYVIEW(dev_priv))
chv_crtc_clock_get(crtc, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index aa46e9e80786..693e22f06aee 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -385,6 +385,36 @@ static int i9xx_pll_refclk(struct drm_device *dev,
return 48000;
}
+void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
+ struct intel_dpll_hw_state *hw_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (DISPLAY_VER(dev_priv) >= 4) {
+ u32 tmp;
+
+ /* No way to read it out on pipes B and C */
+ if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
+ tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
+ else
+ tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+
+ hw_state->dpll_md = tmp;
+ }
+
+ hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
+
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
+ hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
+ hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe));
+ } else {
+ /* Mask out read-only status bits. */
+ hw_state->dpll &= ~(DPLL_LOCK_VLV |
+ DPLL_PORTC_READY_MASK |
+ DPLL_PORTB_READY_MASK);
+ }
+}
+
/* Returns the clock of the currently programmed mode of the given pipe. */
void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index ac01bb19cc6c..c11c18277266 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_dpll_hw_state;
enum pipe;
void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
@@ -22,6 +23,8 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
+void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
+ struct intel_dpll_hw_state *hw_state);
void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
void chv_compute_dpll(struct intel_crtc_state *crtc_state);
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (6 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
` (14 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop rummaging around inside pll->state directly in the low
level pll->enable() functions, and instead let the higher level
code figure out where the correct state is stored and pass it in.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 ++++++++++---------
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 51a7d8df0ca3..1a78093e41f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -64,7 +64,8 @@ struct intel_shared_dpll_funcs {
* the pll is not already enabled.
*/
void (*enable)(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll);
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *dpll_hw_state);
/*
* Hook for disabling the pll, called from intel_disable_shared_dpll()
@@ -227,7 +228,7 @@ static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
- pll->info->funcs->enable(i915, pll);
+ pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
pll->on = true;
}
@@ -553,9 +554,9 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
}
static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
@@ -677,9 +678,9 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
};
static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
@@ -688,10 +689,9 @@ static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
}
static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
-
intel_de_write(i915, SPLL_CTL, hw_state->spll);
intel_de_posting_read(i915, SPLL_CTL);
udelay(20);
@@ -1259,7 +1259,8 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
};
static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
}
@@ -1337,9 +1338,9 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
};
static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
intel_de_rmw(i915, DPLL_CTRL1,
@@ -1351,13 +1352,13 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
}
static void skl_ddi_pll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
- skl_ddi_pll_write_ctrl1(i915, pll);
+ skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
@@ -1372,9 +1373,10 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
}
static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- skl_ddi_pll_write_ctrl1(i915, pll);
+ skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
}
static void skl_ddi_pll_disable(struct drm_i915_private *i915,
@@ -1996,9 +1998,9 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
};
static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- const struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;
@@ -3697,9 +3699,9 @@ static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
}
static void icl_dpll_write(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
@@ -3739,9 +3741,9 @@ static void icl_dpll_write(struct drm_i915_private *i915,
}
static void icl_mg_pll_write(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
/*
@@ -3782,9 +3784,9 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
}
static void dkl_pll_write(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
- struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
u32 val;
@@ -3897,13 +3899,14 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
}
static void combo_pll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
icl_pll_power_enable(i915, pll, enable_reg);
- icl_dpll_write(i915, pll);
+ icl_dpll_write(i915, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3919,11 +3922,12 @@ static void combo_pll_enable(struct drm_i915_private *i915,
}
static void tbt_pll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
- icl_dpll_write(i915, pll);
+ icl_dpll_write(i915, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3937,16 +3941,17 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
}
static void mg_pll_enable(struct drm_i915_private *i915,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *hw_state)
{
i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
icl_pll_power_enable(i915, pll, enable_reg);
if (DISPLAY_VER(i915) >= 12)
- dkl_pll_write(i915, pll);
+ dkl_pll_write(i915, pll, hw_state);
else
- icl_mg_pll_write(i915, pll);
+ icl_mg_pll_write(i915, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 09/18] drm/i915: Extract i965_dpll_md()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (7 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
` (13 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have three copies of the DPLL_MD value computation.
Share it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 693e22f06aee..9e1f94a2ce92 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1008,6 +1008,11 @@ static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
crtc_state->dpll_hw_state.fp1 = fp2;
}
+static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
+{
+ return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+}
+
static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
@@ -1080,11 +1085,8 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
dpll |= DPLL_VCO_ENABLE;
crtc_state->dpll_hw_state.dpll = dpll;
- if (DISPLAY_VER(dev_priv) >= 4) {
- u32 dpll_md = (crtc_state->pixel_multiplier - 1)
- << DPLL_MD_UDI_MULTIPLIER_SHIFT;
- crtc_state->dpll_hw_state.dpll_md = dpll_md;
- }
+ if (DISPLAY_VER(dev_priv) >= 4)
+ crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
}
static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
@@ -1425,8 +1427,7 @@ void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
DPLL_EXT_BUFFER_ENABLE_VLV;
- crtc_state->dpll_hw_state.dpll_md =
- (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+ crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
}
void chv_compute_dpll(struct intel_crtc_state *crtc_state)
@@ -1442,8 +1443,7 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
- crtc_state->dpll_hw_state.dpll_md =
- (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+ crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
}
static int chv_crtc_compute_clock(struct intel_atomic_state *state,
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (8 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-15 14:06 ` Jani Nikula
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
` (12 subsequent siblings)
22 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The *_compute_dpll() functions generally contain
two things:
- huge pile of inline code to calculate the DPLL
register value
- a few calls to helpers to calculate the
DPLL_MD and FP register values
Pull the DPLL register value calculations into a helpers
as well, so that *_compute_dpll() can focus on higher
level tasks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 115 ++++++++++++++--------
1 file changed, 75 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9e1f94a2ce92..0625b9c436c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1013,17 +1013,15 @@ static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
-static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
- const struct dpll *clock,
- const struct dpll *reduced_clock)
+static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll;
- i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
-
- dpll = DPLL_VGA_MODE_DIS;
+ dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
dpll |= DPLLB_MODE_LVDS;
@@ -1082,24 +1080,33 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
else
dpll |= PLL_REF_INPUT_DREFCLK;
- dpll |= DPLL_VCO_ENABLE;
- crtc_state->dpll_hw_state.dpll = dpll;
+ return dpll;
+}
+
+static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
+
+ crtc_state->dpll_hw_state.dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
if (DISPLAY_VER(dev_priv) >= 4)
crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
}
-static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
- const struct dpll *clock,
- const struct dpll *reduced_clock)
+static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll;
- i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
-
- dpll = DPLL_VGA_MODE_DIS;
+ dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
@@ -1136,8 +1143,16 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
else
dpll |= PLL_REF_INPUT_DREFCLK;
- dpll |= DPLL_VCO_ENABLE;
- crtc_state->dpll_hw_state.dpll = dpll;
+ return dpll;
+}
+
+static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
+{
+ i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
+
+ crtc_state->dpll_hw_state.dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
}
static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1266,17 +1281,15 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
}
-static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
- const struct dpll *clock,
- const struct dpll *reduced_clock)
+static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll;
- ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
-
- dpll = 0;
+ dpll = DPLL_VCO_ENABLE;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
dpll |= DPLLB_MODE_LVDS;
@@ -1338,9 +1351,16 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
else
dpll |= PLL_REF_INPUT_DREFCLK;
- dpll |= DPLL_VCO_ENABLE;
+ return dpll;
+}
- crtc_state->dpll_hw_state.dpll = dpll;
+static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
+ const struct dpll *clock,
+ const struct dpll *reduced_clock)
+{
+ ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
+
+ crtc_state->dpll_hw_state.dpll = ilk_dpll(crtc_state, clock, reduced_clock);
}
static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1413,36 +1433,51 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
return intel_reserve_shared_dplls(state, crtc, NULL);
}
+static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ u32 dpll;
+
+ dpll = DPLL_INTEGRATED_REF_CLK_VLV |
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+
+ if (crtc->pipe != PIPE_A)
+ dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+ /* DPLL not used with DSI, but still need the rest set up */
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+ dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
+
+ return dpll;
+}
+
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->dpll_hw_state.dpll = vlv_dpll(crtc_state);
+ crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
+}
+
+static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ u32 dpll;
- crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
+ dpll = DPLL_SSC_REF_CLK_CHV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+
if (crtc->pipe != PIPE_A)
- crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+ dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
/* DPLL not used with DSI, but still need the rest set up */
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
- crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
- DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_VCO_ENABLE;
- crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
+ return dpll;
}
void chv_compute_dpll(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
- DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
- if (crtc->pipe != PIPE_A)
- crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
- /* DPLL not used with DSI, but still need the rest set up */
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
- crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
-
+ crtc_state->dpll_hw_state.dpll = chv_dpll(crtc_state);
crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
}
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (9 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
` (11 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that *_compute_dpll() are no longer a mess
{i9xx,ilk}_update_pll_dividers() don't serve any real
purpose anymore. Just inline them into the callers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 46 +++++++----------------
1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0625b9c436c2..43d36ea56798 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -988,26 +988,6 @@ static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
return (1 << dpll->n) << 16 | dpll->m2;
}
-static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
- const struct dpll *clock,
- const struct dpll *reduced_clock)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 fp, fp2;
-
- if (IS_PINEVIEW(dev_priv)) {
- fp = pnv_dpll_compute_fp(clock);
- fp2 = pnv_dpll_compute_fp(reduced_clock);
- } else {
- fp = i9xx_dpll_compute_fp(clock);
- fp2 = i9xx_dpll_compute_fp(reduced_clock);
- }
-
- crtc_state->dpll_hw_state.fp0 = fp;
- crtc_state->dpll_hw_state.fp1 = fp2;
-}
-
static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
{
return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
@@ -1090,7 +1070,13 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
+ if (IS_PINEVIEW(dev_priv)) {
+ crtc_state->dpll_hw_state.fp0 = pnv_dpll_compute_fp(clock);
+ crtc_state->dpll_hw_state.fp1 = pnv_dpll_compute_fp(reduced_clock);
+ } else {
+ crtc_state->dpll_hw_state.fp0 = i9xx_dpll_compute_fp(clock);
+ crtc_state->dpll_hw_state.fp1 = i9xx_dpll_compute_fp(reduced_clock);
+ }
crtc_state->dpll_hw_state.dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
@@ -1150,7 +1136,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
+ crtc_state->dpll_hw_state.fp0 = i9xx_dpll_compute_fp(clock);
+ crtc_state->dpll_hw_state.fp1 = i9xx_dpll_compute_fp(reduced_clock);
crtc_state->dpll_hw_state.dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
}
@@ -1271,16 +1258,6 @@ static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
return fp;
}
-static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
- const struct dpll *clock,
- const struct dpll *reduced_clock)
-{
- int factor = ilk_fb_cb_factor(crtc_state);
-
- crtc_state->dpll_hw_state.fp0 = ilk_dpll_compute_fp(clock, factor);
- crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
-}
-
static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
@@ -1358,7 +1335,10 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
+ int factor = ilk_fb_cb_factor(crtc_state);
+
+ crtc_state->dpll_hw_state.fp0 = ilk_dpll_compute_fp(clock, factor);
+ crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
crtc_state->dpll_hw_state.dpll = ilk_dpll(crtc_state, clock, reduced_clock);
}
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (10 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
` (10 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the redundant 'dev' argument from i9xx_pll_refclk()
and rename its variables to conform to modern standards.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 43d36ea56798..5246b8a8d461 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -369,17 +369,16 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
return clock->dot;
}
-static int i9xx_pll_refclk(struct drm_device *dev,
- const struct intel_crtc_state *pipe_config)
+static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- u32 dpll = pipe_config->dpll_hw_state.dpll;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ u32 dpll = crtc_state->dpll_hw_state.dpll;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- return dev_priv->display.vbt.lvds_ssc_freq;
- else if (HAS_PCH_SPLIT(dev_priv))
+ return i915->display.vbt.lvds_ssc_freq;
+ else if (HAS_PCH_SPLIT(i915))
return 120000;
- else if (DISPLAY_VER(dev_priv) != 2)
+ else if (DISPLAY_VER(i915) != 2)
return 96000;
else
return 48000;
@@ -425,7 +424,7 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
u32 fp;
struct dpll clock;
int port_clock;
- int refclk = i9xx_pll_refclk(dev, pipe_config);
+ int refclk = i9xx_pll_refclk(pipe_config);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = pipe_config->dpll_hw_state.fp0;
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (11 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:26 ` [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code Ville Syrjala
` (9 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We are alreayd passing the crtc_state to *_crtc_clock_get().
Passing the crtc as well is 100% redundant, so don't do it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c | 21 ++++++++-----------
drivers/gpu/drm/i915/display/intel_dpll.h | 9 +++-----
.../gpu/drm/i915/display/intel_pch_display.c | 2 +-
4 files changed, 16 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ba8a9c671e..806595cf8f97 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3092,11 +3092,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
if (IS_CHERRYVIEW(dev_priv))
- chv_crtc_clock_get(crtc, pipe_config);
+ chv_crtc_clock_get(pipe_config);
else if (IS_VALLEYVIEW(dev_priv))
- vlv_crtc_clock_get(crtc, pipe_config);
+ vlv_crtc_clock_get(pipe_config);
else
- i9xx_crtc_clock_get(crtc, pipe_config);
+ i9xx_crtc_clock_get(pipe_config);
/*
* Normally the dotclock is filled in by the encoder .get_config()
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 5246b8a8d461..9d57262ac577 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -415,11 +415,10 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll = pipe_config->dpll_hw_state.dpll;
u32 fp;
struct dpll clock;
@@ -507,11 +506,10 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = port_clock;
}
-void vlv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
struct dpll clock;
u32 mdiv;
@@ -534,11 +532,10 @@ void vlv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
}
-void chv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
struct dpll clock;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index c11c18277266..dc47affba2ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -42,12 +42,9 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
-void vlv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
-void chv_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config);
+void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config);
+void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config);
+void chv_crtc_clock_get(struct intel_crtc_state *pipe_config);
void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index baf679759e00..252483581c96 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -474,7 +474,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* read out port_clock from the DPLL */
- i9xx_crtc_clock_get(crtc, crtc_state);
+ i9xx_crtc_clock_get(crtc_state);
/*
* In case there is an active pipe without active ports,
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (12 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
@ 2024-04-12 18:26 ` Ville Syrjala
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
` (8 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:26 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename all the ye olde 'pipe_config's to the modern
'crtc_state' name in the legacy DPLL code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 30 +++++++++++------------
drivers/gpu/drm/i915/display/intel_dpll.h | 6 ++---
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9d57262ac577..4df40a14d0f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -415,20 +415,20 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 dpll = pipe_config->dpll_hw_state.dpll;
+ u32 dpll = crtc_state->dpll_hw_state.dpll;
u32 fp;
struct dpll clock;
int port_clock;
- int refclk = i9xx_pll_refclk(pipe_config);
+ int refclk = i9xx_pll_refclk(crtc_state);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
- fp = pipe_config->dpll_hw_state.fp0;
+ fp = crtc_state->dpll_hw_state.fp0;
else
- fp = pipe_config->dpll_hw_state.fp1;
+ fp = crtc_state->dpll_hw_state.fp1;
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev_priv)) {
@@ -503,12 +503,12 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config)
* port_clock to compute adjusted_mode.crtc_clock in the
* encoder's get_config() function.
*/
- pipe_config->port_clock = port_clock;
+ crtc_state->port_clock = port_clock;
}
-void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
struct dpll clock;
@@ -516,7 +516,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -529,12 +529,12 @@ void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
- pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
+ crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
}
-void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
@@ -543,7 +543,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -562,7 +562,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
- pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
+ crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index dc47affba2ba..49591bda7f8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -42,9 +42,9 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config);
-void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config);
-void chv_crtc_clock_get(struct intel_crtc_state *pipe_config);
+void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
+void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
+void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (13 preceding siblings ...)
2024-04-12 18:26 ` [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code Ville Syrjala
@ 2024-04-12 18:27 ` Ville Syrjala
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
` (7 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:27 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add some local 'hw_state' variables to the old DPLL code.
Will help with unionizing the dpll_hw_state later.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 98 +++++++++++++----------
1 file changed, 54 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 4df40a14d0f1..b6fbc481c9e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -372,9 +372,9 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- u32 dpll = crtc_state->dpll_hw_state.dpll;
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
- if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
+ if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
return i915->display.vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(i915))
return 120000;
@@ -419,7 +419,8 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 dpll = crtc_state->dpll_hw_state.dpll;
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ u32 dpll = hw_state->dpll;
u32 fp;
struct dpll clock;
int port_clock;
@@ -511,12 +512,13 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
struct dpll clock;
u32 mdiv;
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -538,12 +540,13 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
struct dpll clock;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -1065,19 +1068,20 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
if (IS_PINEVIEW(dev_priv)) {
- crtc_state->dpll_hw_state.fp0 = pnv_dpll_compute_fp(clock);
- crtc_state->dpll_hw_state.fp1 = pnv_dpll_compute_fp(reduced_clock);
+ hw_state->fp0 = pnv_dpll_compute_fp(clock);
+ hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock);
} else {
- crtc_state->dpll_hw_state.fp0 = i9xx_dpll_compute_fp(clock);
- crtc_state->dpll_hw_state.fp1 = i9xx_dpll_compute_fp(reduced_clock);
+ hw_state->fp0 = i9xx_dpll_compute_fp(clock);
+ hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
}
- crtc_state->dpll_hw_state.dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
+ hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
if (DISPLAY_VER(dev_priv) >= 4)
- crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
+ hw_state->dpll_md = i965_dpll_md(crtc_state);
}
static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
@@ -1132,10 +1136,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- crtc_state->dpll_hw_state.fp0 = i9xx_dpll_compute_fp(clock);
- crtc_state->dpll_hw_state.fp1 = i9xx_dpll_compute_fp(reduced_clock);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
- crtc_state->dpll_hw_state.dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
+ hw_state->fp0 = i9xx_dpll_compute_fp(clock);
+ hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
+
+ hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
}
static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1331,12 +1337,13 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
int factor = ilk_fb_cb_factor(crtc_state);
- crtc_state->dpll_hw_state.fp0 = ilk_dpll_compute_fp(clock, factor);
- crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
+ hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);
+ hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
- crtc_state->dpll_hw_state.dpll = ilk_dpll(crtc_state, clock, reduced_clock);
+ hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
}
static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1429,8 +1436,10 @@ static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
{
- crtc_state->dpll_hw_state.dpll = vlv_dpll(crtc_state);
- crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+
+ hw_state->dpll = vlv_dpll(crtc_state);
+ hw_state->dpll_md = i965_dpll_md(crtc_state);
}
static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
@@ -1453,8 +1462,10 @@ static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
void chv_compute_dpll(struct intel_crtc_state *crtc_state)
{
- crtc_state->dpll_hw_state.dpll = chv_dpll(crtc_state);
- crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
+ struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+
+ hw_state->dpll = chv_dpll(crtc_state);
+ hw_state->dpll_md = i965_dpll_md(crtc_state);
}
static int chv_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1810,7 +1821,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 dpll = crtc_state->dpll_hw_state.dpll;
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
enum pipe pipe = crtc->pipe;
int i;
@@ -1820,36 +1831,35 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
if (i9xx_has_pps(dev_priv))
assert_pps_unlocked(dev_priv, pipe);
- intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
- intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
+ intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);
+ intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
/*
* Apparently we need to have VGA mode enabled prior to changing
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
/* Wait for the clocks to stabilize. */
intel_de_posting_read(dev_priv, DPLL(pipe));
udelay(150);
if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write(dev_priv, DPLL_MD(pipe),
- crtc_state->dpll_hw_state.dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
} else {
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
}
/* We do this three times for luck */
for (i = 0; i < 3; i++) {
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
intel_de_posting_read(dev_priv, DPLL(pipe));
udelay(150); /* wait for warmup */
}
@@ -1979,9 +1989,10 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
enum pipe pipe = crtc->pipe;
- intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
intel_de_posting_read(dev_priv, DPLL(pipe));
udelay(150);
@@ -1993,6 +2004,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
enum pipe pipe = crtc->pipe;
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
@@ -2002,16 +2014,14 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
/* Enable Refclk */
intel_de_write(dev_priv, DPLL(pipe),
- crtc_state->dpll_hw_state.dpll &
- ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
+ hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
- if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
+ if (hw_state->dpll & DPLL_VCO_ENABLE) {
vlv_prepare_pll(crtc_state);
_vlv_enable_pll(crtc_state);
}
- intel_de_write(dev_priv, DPLL_MD(pipe),
- crtc_state->dpll_hw_state.dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
intel_de_posting_read(dev_priv, DPLL_MD(pipe));
}
@@ -2114,6 +2124,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
@@ -2134,7 +2145,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
udelay(1);
/* Enable PLL */
- intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
+ intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
/* Check PLL is locked */
if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
@@ -2145,6 +2156,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
enum pipe pipe = crtc->pipe;
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
@@ -2154,9 +2166,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
/* Enable Refclk and SSC */
intel_de_write(dev_priv, DPLL(pipe),
- crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
+ hw_state->dpll & ~DPLL_VCO_ENABLE);
- if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
+ if (hw_state->dpll & DPLL_VCO_ENABLE) {
chv_prepare_pll(crtc_state);
_chv_enable_pll(crtc_state);
}
@@ -2169,10 +2181,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
* the value from DPLLBMD to either pipe B or C.
*/
intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
- intel_de_write(dev_priv, DPLL_MD(PIPE_B),
- crtc_state->dpll_hw_state.dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
intel_de_write(dev_priv, CBR4_VLV, 0);
- dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
+ dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
/*
* DPLLB VGA mode also seems to cause problems.
@@ -2182,8 +2193,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
(intel_de_read(dev_priv, DPLL(PIPE_B)) &
DPLL_VGA_MODE_DIS) == 0);
} else {
- intel_de_write(dev_priv, DPLL_MD(pipe),
- crtc_state->dpll_hw_state.dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
intel_de_posting_read(dev_priv, DPLL_MD(pipe));
}
}
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (14 preceding siblings ...)
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
@ 2024-04-12 18:27 ` Ville Syrjala
2024-04-12 18:27 ` [PATCH 17/18] drm/i915: Unionize dpll_hw_state Ville Syrjala
` (6 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:27 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_dpll_hw_state has a spot for all possible
PLL registers across all platforms (well, apart from
cx0/snps). This makes it rather confusing when trying to
figure out which members belong to which platform(s).
Split the struct up into five different platform specific
sub-structures. For now this will actually increase the size
a little bit as we have to duplicate a few members from
skl to icl, but that will be remedied soon when we turn
the thing into a union.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 35 ++--
drivers/gpu/drm/i915/display/intel_dpll.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 183 ++++++++++++------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 33 ++--
.../gpu/drm/i915/display/intel_pch_display.c | 2 +-
6 files changed, 162 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 806595cf8f97..96ed1490fec7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3074,13 +3074,13 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
if (DISPLAY_VER(dev_priv) >= 4) {
- tmp = pipe_config->dpll_hw_state.dpll_md;
+ tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
pipe_config->pixel_multiplier =
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
- tmp = pipe_config->dpll_hw_state.dpll;
+ tmp = pipe_config->dpll_hw_state.i9xx.dpll;
pipe_config->pixel_multiplier =
((tmp & SDVO_MULTIPLIER_MASK)
>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b6fbc481c9e5..b9f1c5370598 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -372,7 +372,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
return i915->display.vbt.lvds_ssc_freq;
@@ -385,9 +385,10 @@ static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
}
void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
if (DISPLAY_VER(dev_priv) >= 4) {
u32 tmp;
@@ -419,7 +420,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
u32 dpll = hw_state->dpll;
u32 fp;
struct dpll clock;
@@ -427,9 +428,9 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
int refclk = i9xx_pll_refclk(crtc_state);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
- fp = crtc_state->dpll_hw_state.fp0;
+ fp = hw_state->fp0;
else
- fp = crtc_state->dpll_hw_state.fp1;
+ fp = hw_state->fp1;
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev_priv)) {
@@ -512,7 +513,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
struct dpll clock;
u32 mdiv;
int refclk = 100000;
@@ -540,7 +541,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
struct dpll clock;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
@@ -1068,7 +1069,7 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
if (IS_PINEVIEW(dev_priv)) {
hw_state->fp0 = pnv_dpll_compute_fp(clock);
@@ -1136,7 +1137,7 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
hw_state->fp0 = i9xx_dpll_compute_fp(clock);
hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
@@ -1337,7 +1338,7 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
const struct dpll *clock,
const struct dpll *reduced_clock)
{
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
int factor = ilk_fb_cb_factor(crtc_state);
hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);
@@ -1436,7 +1437,7 @@ static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
{
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
hw_state->dpll = vlv_dpll(crtc_state);
hw_state->dpll_md = i965_dpll_md(crtc_state);
@@ -1462,7 +1463,7 @@ static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
void chv_compute_dpll(struct intel_crtc_state *crtc_state)
{
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
hw_state->dpll = chv_dpll(crtc_state);
hw_state->dpll_md = i965_dpll_md(crtc_state);
@@ -1821,7 +1822,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
int i;
@@ -1989,7 +1990,7 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
@@ -2004,7 +2005,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
@@ -2124,7 +2125,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
@@ -2156,7 +2157,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 49591bda7f8b..a86a79408af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -24,7 +24,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
- struct intel_dpll_hw_state *hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state);
void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
void chv_compute_dpll(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1a78093e41f5..4709b290be97 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -520,8 +520,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;
@@ -555,8 +556,9 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
@@ -637,8 +639,10 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
}
static void ibx_dump_hw_state(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
+
drm_printf(p, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
"fp0: 0x%x, fp1: 0x%x\n",
hw_state->dpll,
@@ -647,9 +651,12 @@ static void ibx_dump_hw_state(struct drm_printer *p,
hw_state->fp1);
}
-static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *a,
- const struct intel_dpll_hw_state *b)
+static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
+ const struct intel_dpll_hw_state *_b)
{
+ const struct i9xx_dpll_hw_state *a = &_a->i9xx;
+ const struct i9xx_dpll_hw_state *b = &_b->i9xx;
+
return a->dpll == b->dpll &&
a->dpll_md == b->dpll_md &&
a->fp0 == b->fp0 &&
@@ -679,8 +686,9 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
@@ -690,8 +698,10 @@ static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+
intel_de_write(i915, SPLL_CTL, hw_state->spll);
intel_de_posting_read(i915, SPLL_CTL);
udelay(20);
@@ -731,8 +741,9 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;
@@ -752,8 +763,9 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
u32 val;
@@ -978,8 +990,9 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
int refclk;
int n, p, r;
u32 wrpll = hw_state->wrpll;
@@ -1023,7 +1036,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
unsigned int p, n2, r2;
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
@@ -1103,7 +1116,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
int link_clock = 0;
@@ -1131,7 +1144,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
return -EINVAL;
@@ -1155,8 +1168,9 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
int link_clock = 0;
switch (hw_state->spll & SPLL_FREQ_MASK) {
@@ -1231,15 +1245,20 @@ static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
}
static void hsw_dump_hw_state(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+
drm_printf(p, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
hw_state->wrpll, hw_state->spll);
}
-static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *a,
- const struct intel_dpll_hw_state *b)
+static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
+ const struct intel_dpll_hw_state *_b)
{
+ const struct hsw_dpll_hw_state *a = &_a->hsw;
+ const struct hsw_dpll_hw_state *b = &_b->hsw;
+
return a->wrpll == b->wrpll &&
a->spll == b->spll;
}
@@ -1271,7 +1290,7 @@ static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
return true;
}
@@ -1339,7 +1358,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -1353,8 +1372,9 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
static void skl_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1374,8 +1394,10 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+
skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
}
@@ -1397,13 +1419,14 @@ static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
- u32 val;
+ struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
bool ret;
+ u32 val;
wakeref = intel_display_power_get_if_enabled(i915,
POWER_DOMAIN_DISPLAY_CORE);
@@ -1434,8 +1457,9 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -1706,8 +1730,9 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
int ref_clock = i915->display.dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
@@ -1778,7 +1803,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
struct skl_wrpll_params wrpll_params = {};
int ret;
@@ -1816,7 +1841,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
static int
skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
u32 ctrl1;
/*
@@ -1853,8 +1878,9 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
int link_clock = 0;
switch ((hw_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
@@ -1931,16 +1957,18 @@ static int skl_get_dpll(struct intel_atomic_state *state,
static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(i915, pll, hw_state);
+ return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(i915, pll, hw_state);
+ return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -1950,15 +1978,20 @@ static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
}
static void skl_dump_hw_state(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+
drm_printf(p, "dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
hw_state->ctrl1, hw_state->cfgcr1, hw_state->cfgcr2);
}
-static bool skl_compare_hw_state(const struct intel_dpll_hw_state *a,
- const struct intel_dpll_hw_state *b)
+static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
+ const struct intel_dpll_hw_state *_b)
{
+ const struct skl_dpll_hw_state *a = &_a->skl;
+ const struct skl_dpll_hw_state *b = &_b->skl;
+
return a->ctrl1 == b->ctrl1 &&
a->cfgcr1 == b->cfgcr1 &&
a->cfgcr2 == b->cfgcr2;
@@ -1999,8 +2032,9 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;
@@ -2120,8 +2154,9 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
enum dpio_phy phy;
@@ -2253,7 +2288,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
const struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state;
+ struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
int clock = crtc_state->port_clock;
int vco = clk_div->vco;
u32 prop_coef, int_coef, gain_ctl, targ_cnt;
@@ -2319,8 +2354,9 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
struct dpll clock;
clock.m1 = 2;
@@ -2412,8 +2448,10 @@ static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
}
static void bxt_dump_hw_state(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+
drm_printf(p, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
@@ -2423,9 +2461,12 @@ static void bxt_dump_hw_state(struct drm_printer *p,
hw_state->pcsdw12);
}
-static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *a,
- const struct intel_dpll_hw_state *b)
+static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
+ const struct intel_dpll_hw_state *_b)
{
+ const struct bxt_dpll_hw_state *a = &_a->bxt;
+ const struct bxt_dpll_hw_state *b = &_b->bxt;
+
return a->ebb0 == b->ebb0 &&
a->ebb4 == b->ebb4 &&
a->pll0 == b->pll0 &&
@@ -2708,7 +2749,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
/*
* The PLL outputs multiple frequencies at the same time, selection is
@@ -2779,8 +2820,9 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
int ref_clock = icl_wrpll_ref_clock(i915);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -2840,8 +2882,9 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
static void icl_calc_dpll_state(struct drm_i915_private *i915,
const struct skl_wrpll_params *pll_params,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
u32 dco_fraction = pll_params->dco_fraction;
if (ehl_combo_pll_div_frac_wa_needed(i915))
@@ -2866,7 +2909,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
- struct intel_dpll_hw_state *hw_state,
+ struct icl_dpll_hw_state *hw_state,
bool is_dkl)
{
static const u8 div1_vals[] = { 7, 5, 3, 2 };
@@ -2945,9 +2988,10 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* adapted to integer-only calculation, that's why it looks so different.
*/
static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
int refclk_khz = i915->display.dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
@@ -3149,8 +3193,9 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3487,8 +3532,9 @@ static void icl_put_dplls(struct intel_atomic_state *state,
static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
intel_wakeref_t wakeref;
@@ -3553,8 +3599,9 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
intel_wakeref_t wakeref;
@@ -3624,9 +3671,10 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state,
+ struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
+ struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
bool ret = false;
@@ -3684,23 +3732,23 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
- return icl_pll_get_hw_state(i915, pll, hw_state, enable_reg);
+ return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
}
static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state)
{
- return icl_pll_get_hw_state(i915, pll, hw_state, TBT_PLL_ENABLE);
+ return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
static void icl_dpll_write(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
@@ -3742,7 +3790,7 @@ static void icl_dpll_write(struct drm_i915_private *i915,
static void icl_mg_pll_write(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3785,7 +3833,7 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
static void dkl_pll_write(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
u32 val;
@@ -3900,8 +3948,9 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
static void combo_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
icl_pll_power_enable(i915, pll, enable_reg);
@@ -3923,8 +3972,10 @@ static void combo_pll_enable(struct drm_i915_private *i915,
static void tbt_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+
icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
icl_dpll_write(i915, pll, hw_state);
@@ -3942,8 +3993,9 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
static void mg_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
icl_pll_power_enable(i915, pll, enable_reg);
@@ -4024,8 +4076,10 @@ static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
}
static void icl_dump_hw_state(struct drm_printer *p,
- const struct intel_dpll_hw_state *hw_state)
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
+ const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+
drm_printf(p, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, "
"mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
"mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
@@ -4045,9 +4099,12 @@ static void icl_dump_hw_state(struct drm_printer *p,
hw_state->mg_pll_tdc_coldst_bias);
}
-static bool icl_compare_hw_state(const struct intel_dpll_hw_state *a,
- const struct intel_dpll_hw_state *b)
+static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
+ const struct intel_dpll_hw_state *_b)
{
+ const struct icl_dpll_hw_state *a = &_a->icl;
+ const struct icl_dpll_hw_state *b = &_b->icl;
+
/* FIXME split combo vs. mg more thoroughly */
return a->cfgcr0 == b->cfgcr0 &&
a->cfgcr1 == b->cfgcr1 &&
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d63d0651b6a1..95438f12c4f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -181,18 +181,19 @@ enum icl_port_dpll_id {
ICL_PORT_DPLL_COUNT,
};
-struct intel_dpll_hw_state {
- /* i9xx, pch plls */
+struct i9xx_dpll_hw_state {
u32 dpll;
u32 dpll_md;
u32 fp0;
u32 fp1;
+};
- /* hsw, bdw */
+struct hsw_dpll_hw_state {
u32 wrpll;
u32 spll;
+};
- /* skl */
+struct skl_dpll_hw_state {
/*
* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
* lower part of ctrl1 and they get shifted into position when writing
@@ -202,20 +203,18 @@ struct intel_dpll_hw_state {
u32 ctrl1;
/* HDMI only, 0 when used for DP */
u32 cfgcr1, cfgcr2;
+};
- /* icl */
- u32 cfgcr0;
+struct bxt_dpll_hw_state {
+ u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
+};
+
+struct icl_dpll_hw_state {
+ u32 cfgcr0, cfgcr1;
/* tgl */
u32 div0;
- /* bxt */
- u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
-
- /*
- * ICL uses the following, already defined:
- * u32 cfgcr0, cfgcr1;
- */
u32 mg_refclkin_ctl;
u32 mg_clktop2_coreclkctl1;
u32 mg_clktop2_hsclkctl;
@@ -230,6 +229,14 @@ struct intel_dpll_hw_state {
u32 mg_pll_tdc_coldst_bias_mask;
};
+struct intel_dpll_hw_state {
+ struct i9xx_dpll_hw_state i9xx;
+ struct hsw_dpll_hw_state hsw;
+ struct skl_dpll_hw_state skl;
+ struct bxt_dpll_hw_state bxt;
+ struct icl_dpll_hw_state icl;
+};
+
/**
* struct intel_shared_dpll_state - hold the DPLL atomic state
*
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 252483581c96..826e38a9e6a4 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -529,7 +529,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
&crtc_state->dpll_hw_state);
drm_WARN_ON(&dev_priv->drm, !pll_active);
- tmp = crtc_state->dpll_hw_state.dpll;
+ tmp = crtc_state->dpll_hw_state.i9xx.dpll;
crtc_state->pixel_multiplier =
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 17/18] drm/i915: Unionize dpll_hw_state
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (15 preceding siblings ...)
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
@ 2024-04-12 18:27 ` Ville Syrjala
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
` (5 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:27 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_dpll_hw_state contains space for all possible PLL
register values across all platforms. That is rather wasteful
as each machine only needs to store the registers values
that are appropriate for the platform.
Turn intel_dpll_hw_state into a union so that we don't
waste memory for the register values of other platforms.
And let's use an anonymous union so that we don't have
to do tons of s/struct/union/ all over the place.
pahole:
struct intel_dpll_hw_state {
- struct i9xx_dpll_hw_state i9xx; /* 0 16 */
- struct hsw_dpll_hw_state hsw; /* 16 8 */
- struct skl_dpll_hw_state skl; /* 24 12 */
- struct bxt_dpll_hw_state bxt; /* 36 44 */
- /* --- cacheline 1 boundary (64 bytes) was 16 bytes ago --- */
- struct icl_dpll_hw_state icl; /* 80 60 */
+ union {
+ struct i9xx_dpll_hw_state i9xx; /* 0 16 */
+ struct hsw_dpll_hw_state hsw; /* 0 8 */
+ struct skl_dpll_hw_state skl; /* 0 12 */
+ struct bxt_dpll_hw_state bxt; /* 0 44 */
+ struct icl_dpll_hw_state icl; /* 0 60 */
+ }; /* 0 60 */
- /* size: 140, cachelines: 3, members: 5 */
- /* last cacheline: 12 bytes */
+ /* size: 60, cachelines: 1, members: 1 */
+ /* last cacheline: 60 bytes */
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 95438f12c4f0..d0ec6196d398 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -230,11 +230,13 @@ struct icl_dpll_hw_state {
};
struct intel_dpll_hw_state {
- struct i9xx_dpll_hw_state i9xx;
- struct hsw_dpll_hw_state hsw;
- struct skl_dpll_hw_state skl;
- struct bxt_dpll_hw_state bxt;
- struct icl_dpll_hw_state icl;
+ union {
+ struct i9xx_dpll_hw_state i9xx;
+ struct hsw_dpll_hw_state hsw;
+ struct skl_dpll_hw_state skl;
+ struct bxt_dpll_hw_state bxt;
+ struct icl_dpll_hw_state icl;
+ };
};
/**
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (16 preceding siblings ...)
2024-04-12 18:27 ` [PATCH 17/18] drm/i915: Unionize dpll_hw_state Ville Syrjala
@ 2024-04-12 18:27 ` Ville Syrjala
2024-04-15 14:26 ` Jani Nikula
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
` (4 subsequent siblings)
22 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2024-04-12 18:27 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For some reason the snps/cx0 PLL states were added into
a union alongside dpll_hw_state. Just suck them into
dpll_hw_state so that we don't have so many levels of
unions/etc.
TODO: Get rid of 'clock' from the snps/cx0 PLL states
as it is not a register values and thus doesn't
belong there
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++-----
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++--
.../drm/i915/display/intel_display_types.h | 43 +------------------
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 39 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 +--
6 files changed, 58 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2c4bf33155f..8e3b13884bb8 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1827,7 +1827,7 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state;
+ struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
int i;
if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -1859,7 +1859,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
- crtc_state->cx0pll_state.c10 = *tables[i];
+ crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
intel_c10pll_update_pll(crtc_state, encoder);
return 0;
@@ -1899,7 +1899,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10;
+ const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10;
int i;
intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
@@ -2079,7 +2079,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
/* try computed C20 HDMI tables before using consolidated tables */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
- &crtc_state->cx0pll_state.c20) == 0)
+ &crtc_state->dpll_hw_state.cx0pll.c20) == 0)
return 0;
}
@@ -2089,7 +2089,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
- crtc_state->cx0pll_state.c20 = *tables[i];
+ crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
return 0;
}
}
@@ -2335,7 +2335,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
+ const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
bool dp = false;
int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
u32 clock = crtc_state->port_clock;
@@ -2484,9 +2484,9 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
/* TODO: HDMI FRL */
/* DP2.0 10G and 20G rates enable MPLLA*/
if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
- val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
+ val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
else
- val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
@@ -3025,7 +3025,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
struct intel_c10pll_state *mpllb_hw_state)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- const struct intel_c10pll_state *mpllb_sw_state = &state->cx0pll_state.c10;
+ const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10;
int i;
if (intel_crtc_needs_fastset(state))
@@ -3075,7 +3075,7 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
struct intel_c20pll_state *mpll_hw_state)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20;
+ const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3255d4e375af..2e2be08dd26c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4011,8 +4011,8 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
} else {
- intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state);
- crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);
+ intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
+ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
}
intel_ddi_get_config(encoder, crtc_state);
@@ -4021,8 +4021,8 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
static void dg2_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
- crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
+ intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);
+ crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);
intel_ddi_get_config(encoder, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0f4bd5710796..387119c0254c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1004,18 +1004,6 @@ enum intel_output_format {
INTEL_OUTPUT_FORMAT_YCBCR444,
};
-struct intel_mpllb_state {
- u32 clock; /* in KHz */
- u32 ref_control;
- u32 mpllb_cp;
- u32 mpllb_div;
- u32 mpllb_div2;
- u32 mpllb_fracn1;
- u32 mpllb_fracn2;
- u32 mpllb_sscen;
- u32 mpllb_sscstep;
-};
-
/* Used by dp and fdi links */
struct intel_link_m_n {
u32 tu;
@@ -1031,31 +1019,6 @@ struct intel_csc_matrix {
u16 postoff[3];
};
-struct intel_c10pll_state {
- u32 clock; /* in KHz */
- u8 tx;
- u8 cmn;
- u8 pll[20];
-};
-
-struct intel_c20pll_state {
- u32 clock; /* in kHz */
- u16 tx[3];
- u16 cmn[4];
- union {
- u16 mplla[10];
- u16 mpllb[11];
- };
-};
-
-struct intel_cx0pll_state {
- union {
- struct intel_c10pll_state c10;
- struct intel_c20pll_state c20;
- };
- bool ssc_enabled;
-};
-
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1200,11 +1163,7 @@ struct intel_crtc_state {
struct intel_shared_dpll *shared_dpll;
/* Actual register state of the dpll, for shared dpll cross-checking. */
- union {
- struct intel_dpll_hw_state dpll_hw_state;
- struct intel_mpllb_state mpllb_state;
- struct intel_cx0pll_state cx0pll_state;
- };
+ struct intel_dpll_hw_state dpll_hw_state;
/*
* ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b9f1c5370598..49274d632716 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1222,7 +1222,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
return ret;
/* TODO: Do the readback via intel_compute_shared_dplls() */
- crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);
+ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d0ec6196d398..f09e513ce05b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -229,6 +229,43 @@ struct icl_dpll_hw_state {
u32 mg_pll_tdc_coldst_bias_mask;
};
+struct intel_mpllb_state {
+ u32 clock; /* in KHz */
+ u32 ref_control;
+ u32 mpllb_cp;
+ u32 mpllb_div;
+ u32 mpllb_div2;
+ u32 mpllb_fracn1;
+ u32 mpllb_fracn2;
+ u32 mpllb_sscen;
+ u32 mpllb_sscstep;
+};
+
+struct intel_c10pll_state {
+ u32 clock; /* in KHz */
+ u8 tx;
+ u8 cmn;
+ u8 pll[20];
+};
+
+struct intel_c20pll_state {
+ u32 clock; /* in kHz */
+ u16 tx[3];
+ u16 cmn[4];
+ union {
+ u16 mplla[10];
+ u16 mpllb[11];
+ };
+};
+
+struct intel_cx0pll_state {
+ union {
+ struct intel_c10pll_state c10;
+ struct intel_c20pll_state c20;
+ };
+ bool ssc_enabled;
+};
+
struct intel_dpll_hw_state {
union {
struct i9xx_dpll_hw_state i9xx;
@@ -236,6 +273,8 @@ struct intel_dpll_hw_state {
struct skl_dpll_hw_state skl;
struct bxt_dpll_hw_state bxt;
struct icl_dpll_hw_state icl;
+ struct intel_mpllb_state mpllb;
+ struct intel_cx0pll_state cx0pll;
};
};
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 53dbcdf140b5..e6df1f92def5 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -1811,7 +1811,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
- crtc_state->mpllb_state = *tables[i];
+ crtc_state->dpll_hw_state.mpllb = *tables[i];
return 0;
}
}
@@ -1823,7 +1823,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
+ const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
enum phy phy = intel_encoder_to_phy(encoder);
i915_reg_t enable_reg = (phy <= PHY_D ?
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
@@ -2001,7 +2001,7 @@ void intel_mpllb_state_verify(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_mpllb_state mpllb_hw_state = {};
- const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
+ const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb;
struct intel_encoder *encoder;
if (!IS_DG2(i915))
--
2.43.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
@ 2024-04-15 14:06 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2024-04-15 14:06 UTC (permalink / raw
To: Ville Syrjala, intel-gfx
On Fri, 12 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The *_compute_dpll() functions generally contain
> two things:
> - huge pile of inline code to calculate the DPLL
> register value
> - a few calls to helpers to calculate the
> DPLL_MD and FP register values
>
> Pull the DPLL register value calculations into a helpers
> as well, so that *_compute_dpll() can focus on higher
> level tasks.
In addition to what the subject says, this touches vlv/chv paths.
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 115 ++++++++++++++--------
> 1 file changed, 75 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 9e1f94a2ce92..0625b9c436c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1013,17 +1013,15 @@ static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
> return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> }
>
> -static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
> - const struct dpll *clock,
> - const struct dpll *reduced_clock)
> +static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dpll;
>
> - i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
> -
> - dpll = DPLL_VGA_MODE_DIS;
> + dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
> dpll |= DPLLB_MODE_LVDS;
> @@ -1082,24 +1080,33 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
> else
> dpll |= PLL_REF_INPUT_DREFCLK;
>
> - dpll |= DPLL_VCO_ENABLE;
> - crtc_state->dpll_hw_state.dpll = dpll;
> + return dpll;
> +}
> +
> +static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
> +
> + crtc_state->dpll_hw_state.dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
>
> if (DISPLAY_VER(dev_priv) >= 4)
> crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
> }
>
> -static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> - const struct dpll *clock,
> - const struct dpll *reduced_clock)
> +static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dpll;
>
> - i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
> -
> - dpll = DPLL_VGA_MODE_DIS;
> + dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> @@ -1136,8 +1143,16 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> else
> dpll |= PLL_REF_INPUT_DREFCLK;
>
> - dpll |= DPLL_VCO_ENABLE;
> - crtc_state->dpll_hw_state.dpll = dpll;
> + return dpll;
> +}
> +
> +static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> +{
> + i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
> +
> + crtc_state->dpll_hw_state.dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
> }
>
> static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1266,17 +1281,15 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
> crtc_state->dpll_hw_state.fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
> }
>
> -static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
> - const struct dpll *clock,
> - const struct dpll *reduced_clock)
> +static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dpll;
>
> - ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
> -
> - dpll = 0;
> + dpll = DPLL_VCO_ENABLE;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
> dpll |= DPLLB_MODE_LVDS;
> @@ -1338,9 +1351,16 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
> else
> dpll |= PLL_REF_INPUT_DREFCLK;
>
> - dpll |= DPLL_VCO_ENABLE;
> + return dpll;
> +}
>
> - crtc_state->dpll_hw_state.dpll = dpll;
> +static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
> + const struct dpll *clock,
> + const struct dpll *reduced_clock)
> +{
> + ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
> +
> + crtc_state->dpll_hw_state.dpll = ilk_dpll(crtc_state, clock, reduced_clock);
> }
>
> static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1413,36 +1433,51 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> return intel_reserve_shared_dplls(state, crtc, NULL);
> }
>
> +static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + u32 dpll;
> +
> + dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> +
> + if (crtc->pipe != PIPE_A)
> + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> + /* DPLL not used with DSI, but still need the rest set up */
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> + dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> +
> + return dpll;
> +}
> +
> void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
> +{
> + crtc_state->dpll_hw_state.dpll = vlv_dpll(crtc_state);
> + crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
> +}
> +
> +static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + u32 dpll;
>
> - crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> + dpll = DPLL_SSC_REF_CLK_CHV |
> DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> +
> if (crtc->pipe != PIPE_A)
> - crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> /* DPLL not used with DSI, but still need the rest set up */
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> - crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
> - DPLL_EXT_BUFFER_ENABLE_VLV;
> + dpll |= DPLL_VCO_ENABLE;
>
> - crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
> + return dpll;
> }
>
> void chv_compute_dpll(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -
> - crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> - DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> - if (crtc->pipe != PIPE_A)
> - crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> -
> - /* DPLL not used with DSI, but still need the rest set up */
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> - crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
> -
> + crtc_state->dpll_hw_state.dpll = chv_dpll(crtc_state);
> crtc_state->dpll_hw_state.dpll_md = i965_dpll_md(crtc_state);
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
@ 2024-04-15 14:26 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2024-04-15 14:26 UTC (permalink / raw
To: Ville Syrjala, intel-gfx
On Fri, 12 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index d0ec6196d398..f09e513ce05b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -229,6 +229,43 @@ struct icl_dpll_hw_state {
> u32 mg_pll_tdc_coldst_bias_mask;
> };
>
> +struct intel_mpllb_state {
> + u32 clock; /* in KHz */
> + u32 ref_control;
> + u32 mpllb_cp;
> + u32 mpllb_div;
> + u32 mpllb_div2;
> + u32 mpllb_fracn1;
> + u32 mpllb_fracn2;
> + u32 mpllb_sscen;
> + u32 mpllb_sscstep;
> +};
> +
> +struct intel_c10pll_state {
> + u32 clock; /* in KHz */
> + u8 tx;
> + u8 cmn;
> + u8 pll[20];
> +};
> +
> +struct intel_c20pll_state {
> + u32 clock; /* in kHz */
> + u16 tx[3];
> + u16 cmn[4];
> + union {
> + u16 mplla[10];
> + u16 mpllb[11];
> + };
> +};
> +
> +struct intel_cx0pll_state {
> + union {
> + struct intel_c10pll_state c10;
> + struct intel_c20pll_state c20;
> + };
> + bool ssc_enabled;
> +};
IMO struct intel_cx0pll_state should be dropped in follow-up, with
ssc_enabled moved to both intel_c10pll_state and intel_c20pll_state...
> +
> struct intel_dpll_hw_state {
> union {
> struct i9xx_dpll_hw_state i9xx;
> @@ -236,6 +273,8 @@ struct intel_dpll_hw_state {
> struct skl_dpll_hw_state skl;
> struct bxt_dpll_hw_state bxt;
> struct icl_dpll_hw_state icl;
> + struct intel_mpllb_state mpllb;
> + struct intel_cx0pll_state cx0pll;
...and both added here i.e. the union at a step higher.
BR,
Jani.
> };
> };
>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 00/18] drm/i915: PLL refactoring
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (17 preceding siblings ...)
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
@ 2024-04-15 14:26 ` Jani Nikula
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2024-04-15 14:26 UTC (permalink / raw
To: Ville Syrjala, intel-gfx
On Fri, 12 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> A bunch of refactoring around PLLs. Main feature is
> the unionization of dpll_hw_state. The eventual goal
> is to unify the approach for PLLs across all platforms
> instead of the current "shared PLLs are somehow
> different than other PLLs" approach.
The entire series is
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Ville Syrjälä (18):
> drm/i915: Replace hand rolled PLL state dump with
> intel_dpll_dump_hw_state()
> drm/i915: Use printer for the rest of PLL debugfs dump
> drm/i915: Rename PLL hw_state variables/arguments
> drm/i915: Introduce some local PLL state variables
> drm/i915: Extract ilk_fb_cb_factor()
> drm/i915: Extract ilk_dpll_compute_fp()
> drm/i915: Extract i9xx_dpll_get_hw_state()
> drm/i915: Pass the PLL hw_state to pll->enable()
> drm/i915: Extract i965_dpll_md()
> drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
> drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
> drm/i915: Modernize i9xx_pll_refclk()
> drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
> drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
> drm/i915: Add local DPLL 'hw_state' variables
> drm/i915: Carve up struct intel_dpll_hw_state
> drm/i915: Unionize dpll_hw_state
> drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 30 +-
> .../drm/i915/display/intel_display_debugfs.c | 39 +-
> .../drm/i915/display/intel_display_types.h | 43 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 338 +++++++-----
> drivers/gpu/drm/i915/display/intel_dpll.h | 12 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 489 ++++++++++--------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 80 ++-
> .../gpu/drm/i915/display/intel_pch_display.c | 4 +-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 +-
> 11 files changed, 581 insertions(+), 488 deletions(-)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: PLL refactoring
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (18 preceding siblings ...)
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
@ 2024-04-15 14:54 ` Patchwork
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-04-15 14:54 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: PLL refactoring
URL : https://patchwork.freedesktop.org/series/132392/
State : warning
== Summary ==
Error: dim checkpatch failed
14bdc0367571 drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state()
c07ae2c34376 drm/i915: Use printer for the rest of PLL debugfs dump
6bddd5b19e86 drm/i915: Rename PLL hw_state variables/arguments
-:345: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#345: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2852:
+ hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
total: 0 errors, 1 warnings, 0 checks, 604 lines checked
cc06bcedebfb drm/i915: Introduce some local PLL state variables
556a7d6a2bd1 drm/i915: Extract ilk_fb_cb_factor()
ec8d5fca4aca drm/i915: Extract ilk_dpll_compute_fp()
c98904ae3912 drm/i915: Extract i9xx_dpll_get_hw_state()
b71270cf5abf drm/i915: Pass the PLL hw_state to pll->enable()
38c9026555e2 drm/i915: Extract i965_dpll_md()
ae27779441b1 drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
c673e5a40815 drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
a113d7ae2667 drm/i915: Modernize i9xx_pll_refclk()
edf028ec40c2 drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
1e12b7a384c9 drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
560a05be0d68 drm/i915: Add local DPLL 'hw_state' variables
00fd678e3c41 drm/i915: Carve up struct intel_dpll_hw_state
e4b09211a12c drm/i915: Unionize dpll_hw_state
780e3fc506c5 drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
-:119: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4015:
+ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-:130: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#130: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4025:
+ crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);
-:211: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#211: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1225:
+ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
total: 0 errors, 3 warnings, 0 checks, 239 lines checked
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: PLL refactoring
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (19 preceding siblings ...)
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2024-04-15 14:54 ` Patchwork
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork
22 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-04-15 14:54 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: PLL refactoring
URL : https://patchwork.freedesktop.org/series/132392/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: PLL refactoring
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (20 preceding siblings ...)
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-04-15 15:01 ` Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork
22 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-04-15 15:01 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12785 bytes --]
== Series Details ==
Series: drm/i915: PLL refactoring
URL : https://patchwork.freedesktop.org/series/132392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14574 -> Patchwork_132392v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/index.html
Participating hosts (37 -> 36)
------------------------------
Additional (3): bat-jsl-1 fi-apl-guc bat-mtlp-6
Missing (4): fi-kbl-7567u bat-dg2-11 fi-snb-2520m fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_132392v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-1: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
- bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#1849] / [i915#2582])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
- bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4083])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@load:
- bat-dg2-8: [PASS][12] -> [DMESG-WARN][13] ([i915#10014])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/bat-dg2-8/igt@i915_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-dg2-8/igt@i915_module_load@load.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#6621])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-9: NOTRUN -> [ABORT][15] ([i915#10366])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-dg2-9/igt@i915_selftest@live@hangcheck.html
- bat-adls-6: NOTRUN -> [DMESG-WARN][16] ([i915#5591])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-adls-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4212] / [i915#9792]) +8 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#5190] / [i915#9792])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-1: NOTRUN -> [SKIP][19] ([i915#4103]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#9792]) +17 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-1: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#9886])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][22] ([i915#3637] / [i915#9792]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-1: NOTRUN -> [SKIP][23]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][24] ([i915#5274] / [i915#9792])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][25] ([i915#4342] / [i915#5354] / [i915#9792])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][26] +17 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/fi-apl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pm_backlight@basic-brightness:
- bat-mtlp-6: NOTRUN -> [SKIP][27] ([i915#5354] / [i915#9792])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-cursor-plane-move:
- bat-mtlp-6: NOTRUN -> [SKIP][28] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-1: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-6: NOTRUN -> [SKIP][30] ([i915#3555] / [i915#8809] / [i915#9792])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][31] ([i915#3708] / [i915#9792])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-6: NOTRUN -> [SKIP][32] ([i915#3708] / [i915#4077]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-read:
- bat-mtlp-6: NOTRUN -> [SKIP][33] ([i915#3708]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-mtlp-6: NOTRUN -> [SKIP][34] ([i915#10216] / [i915#3708])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-mtlp-6/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_engines:
- bat-adls-6: [TIMEOUT][35] ([i915#10026] / [i915#10134]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/bat-adls-6/igt@i915_selftest@live@gt_engines.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-adls-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hugepages:
- bat-dg2-9: [ABORT][37] ([i915#10366]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/bat-dg2-9/igt@i915_selftest@live@hugepages.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/bat-dg2-9/igt@i915_selftest@live@hugepages.html
[i915#10014]: https://gitlab.freedesktop.org/drm/intel/issues/10014
[i915#10026]: https://gitlab.freedesktop.org/drm/intel/issues/10026
[i915#10134]: https://gitlab.freedesktop.org/drm/intel/issues/10134
[i915#10216]: https://gitlab.freedesktop.org/drm/intel/issues/10216
[i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9792]: https://gitlab.freedesktop.org/drm/intel/issues/9792
[i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886
Build changes
-------------
* Linux: CI_DRM_14574 -> Patchwork_132392v1
CI-20190529: 20190529
CI_DRM_14574: a503d0d68ea39792b2740a7af033bd42fb84f4a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7806: 849cd963ce7e8222dcf17cc872d355181fd2c2a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132392v1: a503d0d68ea39792b2740a7af033bd42fb84f4a5 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
bca7b0b53516 drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
f716e7d37c29 drm/i915: Unionize dpll_hw_state
ef4fcbfd464c drm/i915: Carve up struct intel_dpll_hw_state
e6ae1147ce9b drm/i915: Add local DPLL 'hw_state' variables
fe01de354df0 drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
2e616ec17ad1 drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
98a5e984c0eb drm/i915: Modernize i9xx_pll_refclk()
c216a72e4409 drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
de912dadfeb1 drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
0cf86b5cb993 drm/i915: Extract i965_dpll_md()
f133d591c5f4 drm/i915: Pass the PLL hw_state to pll->enable()
b71d29ca84d0 drm/i915: Extract i9xx_dpll_get_hw_state()
56f8d7d0744b drm/i915: Extract ilk_dpll_compute_fp()
6d90d4433e37 drm/i915: Extract ilk_fb_cb_factor()
110b877c2d3d drm/i915: Introduce some local PLL state variables
7e6b08849004 drm/i915: Rename PLL hw_state variables/arguments
0ea3d51f941b drm/i915: Use printer for the rest of PLL debugfs dump
5822435b5eb7 drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/index.html
[-- Attachment #2: Type: text/html, Size: 15682 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: PLL refactoring
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
` (21 preceding siblings ...)
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-04-15 19:06 ` Patchwork
22 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2024-04-15 19:06 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 81653 bytes --]
== Series Details ==
Series: drm/i915: PLL refactoring
URL : https://patchwork.freedesktop.org/series/132392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14574_full -> Patchwork_132392v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
Known issues
------------
Here are the changes found in Patchwork_132392v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-rkl: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@cold-reset-bound:
- shard-dg1: NOTRUN -> [SKIP][3] ([i915#7701])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#7701])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@device_reset@unbind-cold-reset-rebind.html
- shard-tglu: NOTRUN -> [SKIP][5] ([i915#7701])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@device_reset@unbind-cold-reset-rebind.html
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#7701])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#7701])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#8414]) +7 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8414]) +7 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@drm_fdinfo@busy-hang@rcs0.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][10] -> [FAIL][11] ([i915#7742])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#8414])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#4873])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@gem_caching@reads.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#9323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#9323])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#7697])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#8562])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_create@create-ext-set-pat.html
- shard-dg1: NOTRUN -> [SKIP][18] ([i915#8562])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][19] -> [FAIL][20] ([i915#6268])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#8555])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#8555]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_ctx_persistence@heartbeat-stop.html
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#8555]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_sseu@engines:
- shard-dg1: NOTRUN -> [SKIP][24] ([i915#280]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-args:
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#280])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: NOTRUN -> [FAIL][26] ([i915#5784])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg1: NOTRUN -> [SKIP][27] ([i915#4036])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#4525])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#6334]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_capture@many-4k-zero:
- shard-dg1: NOTRUN -> [FAIL][30] ([i915#9606])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-solo:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4473]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][33] ([i915#2842])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][34] ([i915#2842]) +3 other tests fail
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: [PASS][35] -> [FAIL][36] ([i915#2842])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu: [PASS][37] -> [FAIL][38] ([i915#2842])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-sync:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4473] / [i915#4771])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#3539]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#3281]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3281]) +10 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_exec_reloc@basic-wc-gtt:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3281]) +9 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@gem_exec_reloc@basic-wc-gtt.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3281]) +9 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_schedule@reorder-wide:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4537] / [i915#4812])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#4812]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#4860]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][48] ([i915#10378])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4613]) +3 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglu: NOTRUN -> [SKIP][50] ([i915#4613]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][51] ([i915#4613]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk5/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#4613]) +4 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#4565])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@gem_mmap_gtt@basic-wc:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4077]) +14 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@gem_mmap_gtt@basic-wc.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4077]) +6 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@gem_mmap_gtt@cpuset-medium-copy.html
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4077]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_wc@bad-offset:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#4083]) +3 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@gem_mmap_wc@bad-offset.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][58] ([i915#4083]) +6 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_mmap_wc@write-read.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3282])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_pread@display:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#3282]) +5 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@gem_pread@display.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][61] ([i915#2658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk5/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#3282]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gem_pread@snoop.html
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#3282]) +4 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@gem_pread@snoop.html
* igt@gem_pxp@create-protected-buffer:
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#4270])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@gem_pxp@create-protected-buffer.html
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#4270])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#4270]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#4270]) +3 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#4270]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#5190] / [i915#8428]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#8428]) +6 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4079]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#4079]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@access-control:
- shard-dg1: NOTRUN -> [SKIP][73] ([i915#3297])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#3297]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#3297] / [i915#4880])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-rkl: NOTRUN -> [SKIP][76] ([i915#3297])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg1: NOTRUN -> [SKIP][77] ([i915#3297] / [i915#4958])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gem_userptr_blits@sd-probe.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#2527]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#2856]) +3 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#2856])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@gen9_exec_parse@shadow-peek.html
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#2527]) +3 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@gen9_exec_parse@shadow-peek.html
- shard-tglu: NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: NOTRUN -> [ABORT][83] ([i915#9820])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][84] -> [INCOMPLETE][85] ([i915#9849])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: NOTRUN -> [INCOMPLETE][86] ([i915#9820])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-glk: NOTRUN -> [ABORT][87] ([i915#9849])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk3/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: NOTRUN -> [ABORT][88] ([i915#10131] / [i915#9820])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: NOTRUN -> [INCOMPLETE][89] ([i915#9820] / [i915#9849])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_mult@media-freq@gt1:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#6590]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@i915_pm_freq_mult@media-freq@gt1.html
* igt@i915_pm_rc6_residency@rc6-fence@gt0:
- shard-tglu: NOTRUN -> [WARN][91] ([i915#2681])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-fence@gt0.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#6621])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#8925])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@i915_pm_rps@thresholds-idle@gt1:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#3555] / [i915#8925])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@i915_pm_rps@thresholds-idle@gt1.html
* igt@i915_query@test-query-geometry-subslices:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#5723])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@i915_query@test-query-geometry-subslices.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#5190]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#5190])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4215])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg1: NOTRUN -> [SKIP][99] ([i915#4212])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#8709]) +11 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-4-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#8709]) +11 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#10333])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_async_flips@test-cursor.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#3555])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#1769] / [i915#3555])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][105] ([i915#1769])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-b-hdmi-a-1:
- shard-glk: NOTRUN -> [INCOMPLETE][106] ([i915#9878])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk5/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-b-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#4538] / [i915#5286]) +4 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#5286])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [PASS][109] -> [FAIL][110] ([i915#5138])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#5286]) +4 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#5286])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#3638]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#4538] / [i915#5190])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][115] ([i915#3638]) +5 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#6187])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][117] +32 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][118] +15 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][119] ([i915#4538]) +6 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#6095]) +59 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
- shard-snb: NOTRUN -> [SKIP][121] +9 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-snb5/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#10278])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#10278])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
- shard-tglu: NOTRUN -> [SKIP][124] ([i915#10278])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#6095]) +31 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-edp-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#10278])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#10278]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#6095]) +3 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#10307] / [i915#6095]) +137 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#6095]) +45 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-10/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#7213]) +3 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#7828]) +9 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#7828]) +9 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#7828]) +8 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#7828]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
- shard-tglu: NOTRUN -> [SKIP][137] ([i915#7828]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#7116] / [i915#9424]) +3 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#3116])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@legacy@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][140] ([i915#7173])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html
* igt@kms_content_protection@lic-type-1:
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#9424])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@uevent:
- shard-rkl: NOTRUN -> [SKIP][142] ([i915#7118] / [i915#9424]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-tglu: NOTRUN -> [SKIP][143] ([i915#3555]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#8814]) +2 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3555]) +6 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#3555]) +4 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#3359]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#3359]) +2 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#5354]) +4 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#4103])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#4103] / [i915#4213]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#9809]) +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][153] -> [FAIL][154] ([i915#2346])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#9067])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#4213])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#9833])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
- shard-tglu: NOTRUN -> [SKIP][158] ([i915#9723])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
- shard-mtlp: NOTRUN -> [SKIP][159] ([i915#9833])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#9227])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][161] ([i915#9723]) +1 other test skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_feature_discovery@chamelium:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#4854])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#1839])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_feature_discovery@display-2x.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#4881]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#9934]) +5 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglu: NOTRUN -> [SKIP][166] ([i915#3637])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#3637]) +7 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
- shard-dg2: NOTRUN -> [SKIP][168] +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#2587] / [i915#2672])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#2587] / [i915#2672]) +4 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#2672]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#2672]) +5 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#2672])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#2672] / [i915#3555]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#2672] / [i915#3555])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-dg2: [PASS][176] -> [FAIL][177] ([i915#6880])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#1825]) +30 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#1825]) +26 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#5439])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg1: NOTRUN -> [SKIP][181] ([i915#9766])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][182] +9 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][183] ([i915#8708]) +15 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#3458]) +20 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3458]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#3023]) +18 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#8708]) +3 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#8708]) +10 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#8228])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_hdr@invalid-metadata-sizes.html
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#3555] / [i915#8228])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#8228])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_hdr@invalid-metadata-sizes.html
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8228])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#3555] / [i915#8228])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b:
- shard-mtlp: [PASS][194] -> [ABORT][195] ([i915#10698])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-mtlp-5/igt@kms_plane@pixel-format-source-clamping@pipe-b.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_plane@pixel-format-source-clamping@pipe-b.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][196] ([i915#10647]) +1 other test fail
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#3582]) +7 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][198] ([i915#8292])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#9423]) +3 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#9423]) +3 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][201] ([i915#5176]) +7 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-edp-1.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#9423]) +3 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#5235]) +9 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#5235]) +7 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#5235]) +9 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#5235] / [i915#9423]) +3 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#3555] / [i915#5235]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_pm_backlight@basic-brightness:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#5354])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#9812])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#3361])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#3361])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg1: NOTRUN -> [SKIP][213] ([i915#9519]) +2 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf@psr2-pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][214] ([i915#9808]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf@psr2-pipe-b-edp-1.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][215] +55 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][216] ([i915#9683])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-blt:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#9688]) +13 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_psr@fbc-pr-primary-blt.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][218] ([i915#1072] / [i915#9732]) +1 other test skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
- shard-tglu: NOTRUN -> [SKIP][219] ([i915#9732]) +1 other test skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#1072] / [i915#9732]) +26 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html
* igt@kms_psr@psr2-sprite-plane-onoff:
- shard-glk: NOTRUN -> [SKIP][221] +210 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk1/igt@kms_psr@psr2-sprite-plane-onoff.html
* igt@kms_psr@psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][222] ([i915#1072] / [i915#9732]) +17 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@kms_psr@psr2-suspend.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-mtlp: NOTRUN -> [SKIP][223] ([i915#4235])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-mtlp: NOTRUN -> [SKIP][224] ([i915#5289])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][225] ([i915#5289]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#3555]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][227] ([i915#5030]) +2 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#5030] / [i915#9041])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#8623])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [PASS][230] -> [FAIL][231] ([i915#9196])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-snb5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#9906])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][233] ([i915#2437])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk8/igt@kms_writeback@writeback-fb-id.html
- shard-mtlp: NOTRUN -> [SKIP][234] ([i915#2437])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-rkl: NOTRUN -> [SKIP][235] ([i915#2437])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][236] ([i915#2436])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#7387])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@perf@global-sseu-config.html
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#7387])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@perf@global-sseu-config.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-dg1: NOTRUN -> [SKIP][239] ([i915#2433])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-mtlp: NOTRUN -> [FAIL][240] ([i915#4349]) +1 other test fail
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-5/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg1: NOTRUN -> [SKIP][241] ([i915#8850])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][242] ([i915#8516])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-16/igt@perf_pmu@rc6-all-gts.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#3708])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-17/igt@prime_vgem@basic-fence-flip.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][244] ([i915#9917])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-6/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#9917])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][246] ([i915#9781])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-1/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg1: NOTRUN -> [SKIP][247] ([i915#4818])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_get_bo_offset@create-get-offsets:
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#2575]) +12 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-18/igt@v3d/v3d_get_bo_offset@create-get-offsets.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#2575]) +9 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-7/igt@v3d/v3d_perfmon@create-perfmon-exceed.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][250] ([i915#2575])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done:
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#7711]) +10 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-13/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html
* igt@vc4/vc4_label_bo@set-bad-name:
- shard-tglu: NOTRUN -> [SKIP][252] ([i915#2575]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@vc4/vc4_label_bo@set-bad-name.html
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#7711])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@vc4/vc4_label_bo@set-bad-name.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-mtlp: NOTRUN -> [SKIP][254] ([i915#7711]) +6 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-mtlp-6/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#7711]) +5 other tests skip
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-tglu: [INCOMPLETE][256] ([i915#10513]) -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-4/igt@gem_eio@kms.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglu: [FAIL][258] ([i915#2842]) -> [PASS][259] +1 other test pass
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][260] ([i915#2842]) -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][262] ([i915#5493]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: [FAIL][264] ([i915#3743]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][266] ([i915#2346]) -> [PASS][267]
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@blocking-wf_vblank@b-hdmi-a4:
- shard-dg1: [FAIL][268] ([i915#2122]) -> [PASS][269] +1 other test pass
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg1-18/igt@kms_flip@blocking-wf_vblank@b-hdmi-a4.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg1-15/igt@kms_flip@blocking-wf_vblank@b-hdmi-a4.html
* igt@kms_flip@blocking-wf_vblank@b-vga1:
- shard-snb: [FAIL][270] ([i915#2122]) -> [PASS][271] +1 other test pass
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-snb7/igt@kms_flip@blocking-wf_vblank@b-vga1.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-snb7/igt@kms_flip@blocking-wf_vblank@b-vga1.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][272] ([i915#9295]) -> [PASS][273]
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-4/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][274] ([i915#4281]) -> [PASS][275]
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][276] ([i915#9519]) -> [PASS][277] +4 other tests pass
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][278] ([i915#9519]) -> [PASS][279] +1 other test pass
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][280] ([i915#9196]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-dg2: [SKIP][282] ([i915#3458]) -> [SKIP][283] ([i915#10433] / [i915#3458]) +4 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [SKIP][284] ([i915#10433] / [i915#3458]) -> [SKIP][285] ([i915#3458])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-dg2: [SKIP][286] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][287] ([i915#1072] / [i915#9732]) +5 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: [SKIP][288] ([i915#1072] / [i915#9732]) -> [SKIP][289] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-10/igt@kms_psr@psr2-primary-mmap-gtt.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][290] ([i915#9100]) -> [FAIL][291] ([i915#7484])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-4/igt@perf@non-zero-reason@0-rcs0.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-6/igt@perf@non-zero-reason@0-rcs0.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][292] ([i915#9351]) -> [INCOMPLETE][293] ([i915#5493])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14574/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10333]: https://gitlab.freedesktop.org/drm/intel/issues/10333
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/intel/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/intel/issues/10513
[i915#10647]: https://gitlab.freedesktop.org/drm/intel/issues/10647
[i915#10698]: https://gitlab.freedesktop.org/drm/intel/issues/10698
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9041]: https://gitlab.freedesktop.org/drm/intel/issues/9041
[i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
[i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/intel/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/intel/issues/9766
[i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9878]: https://gitlab.freedesktop.org/drm/intel/issues/9878
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14574 -> Patchwork_132392v1
CI-20190529: 20190529
CI_DRM_14574: a503d0d68ea39792b2740a7af033bd42fb84f4a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7806: 849cd963ce7e8222dcf17cc872d355181fd2c2a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132392v1: a503d0d68ea39792b2740a7af033bd42fb84f4a5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132392v1/index.html
[-- Attachment #2: Type: text/html, Size: 98782 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2024-04-15 19:06 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
2024-04-15 14:06 ` Jani Nikula
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
2024-04-12 18:26 ` [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code Ville Syrjala
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 17/18] drm/i915: Unionize dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
2024-04-15 14:26 ` Jani Nikula
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.