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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aTMpo1PZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99FECC433F1; Tue, 2 Apr 2024 14:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712067927; bh=05KPAcK7dAHejAqXCS3gStMEGMQcesXYI/mYO3QHKbg=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=aTMpo1PZGrw4qjemIspGevm8YLHd2f/XrXbhGu3W9kgoM99qOUtJWV0Q8wTv7foSh IxUF/IdqAwa09OU7wlFmkoL0wH1VLwZ1GjlU/FnLR3kODxIL7BcswcOFUNt/J8kL/N 1SCMR5XQxyX9jJvyECbCP3cuVoZq4T6iAi/CFNB9W1eonl2PZYx+sGPhB70uFlUsqr FSHsrn9UzLA2ljcisrcmoyCiH8vwodEUACVpX8gDOpdT3yr73f7bbnu84lL4GLjtrb C5u8/sWIZnRDlnKnUvP8M2sya7/64U8HFSKg0+OlrqPS6q16Y1euvumdy7mtWOA69f 0RmSF7TtmDAug== From: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= To: Pu Lehui , Stefan O'Rear , Conor Dooley Cc: bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Mykola Lysenko , Manu Bretelle , Pu Lehui Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions In-Reply-To: References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> <20240328-ferocity-repose-c554f75a676c@spud> Date: Tue, 02 Apr 2024 16:25:24 +0200 Message-ID: <87cyr7rgdn.fsf@all.your.base.are.belong.to.us> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Pu Lehui writes: > On 2024/3/29 6:07, Conor Dooley wrote: >> On Thu, Mar 28, 2024 at 03:34:31PM -0400, Stefan O'Rear wrote: >>> On Thu, Mar 28, 2024, at 8:49 AM, Pu Lehui wrote: >>>> From: Pu Lehui >>>> >>>> This patch relaxes the restrictions on the Zbb instructions. The hardw= are >>>> is capable of recognizing the Zbb instructions independently, eliminat= ing >>>> the need for reliance on kernel compile configurations. >>> >>> This doesn't make sense to me. >>=20 >> It doesn't make sense to me either. Of course the hardware's capability >> to understand an instruction is independent of whether or not a >> toolchain is capable of actually emitting the instruction. >>=20 >>> RISCV_ISA_ZBB is defined as: >>> >>> Adds support to dynamically detect the presence of the ZBB >>> extension (basic bit manipulation) and enable its usage. >>> >>> In other words, RISCV_ISA_ZBB=3Dn should disable everything that attemp= ts >>> to detect Zbb at runtime. It is mostly relevant for code size reduction, >>> which is relevant for BPF since if RISCV_ISA_ZBB=3Dn all rvzbb_enabled() >>> checks can be constant-folded. > > Thanks for review. My initial thought was the same as yours, but after=20 > discussions [0] and test verifications, the hardware can indeed=20 > recognize the zbb instruction even if the kernel has not enabled=20 > CONFIG_RISCV_ISA_ZBB. As Conor mentioned, we are just acting as a JIT to= =20 > emit zbb instruction here. Maybe is_hw_zbb_capable() will be better? I still think Lehui's patch is correct; Building a kernel that can boot on multiple platforms (w/ or w/o Zbb support) and not having Zbb insn in the kernel proper, and iff Zbb is available at run-time the BPF JIT will emit Zbb. For these kind of optimizations, (IMO) it's better to let the BPF JIT decide at run-time. Bj=C3=B6rn