From: Sander Vanheule <sander@svanheule.net>
To: Pavel Machek <pavel@ucw.cz>, Rob Herring <robh+dt@kernel.org>,
Lee Jones <lee.jones@linaro.org>, Mark Brown <broonie@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Michael Walle <michael@walle.cc>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
linux-leds@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>,
Andy Shevchenko <andy.shevchenko@gmail.com>,
linux-kernel@vger.kernel.org,
Sander Vanheule <sander@svanheule.net>
Subject: [PATCH v5 2/8] gpio: regmap: Add quirk for aliased data registers
Date: Sat, 12 Jun 2021 23:12:32 +0200 [thread overview]
Message-ID: <5d8e5e8a29ecf39da48beb94c42003a5c686ec4e.1623532208.git.sander@svanheule.net> (raw)
In-Reply-To: <cover.1623532208.git.sander@svanheule.net>
Some chips have the read-only input and write-only output data registers
aliased to the same offset. As a result it is not possible to perform
read-modify-writes on the output values, when a line is still configured
as input.
Add a quirk for aliased data registers, and document how the regmap
should be set up for correct operation.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
drivers/gpio/gpio-regmap.c | 7 ++++++-
include/linux/gpio/regmap.h | 13 +++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
index 134cedf151a7..3a3d0d9a945c 100644
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -15,6 +15,7 @@ struct gpio_regmap {
struct device *parent;
struct regmap *regmap;
struct gpio_chip gpio_chip;
+ unsigned int quirks;
int reg_stride;
int ngpio_per_reg;
@@ -68,7 +69,10 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset)
if (ret)
return ret;
- ret = regmap_read(gpio->regmap, reg, &val);
+ if (gpio->quirks & GPIO_REGMAP_QUIRK_ALIASED_DATA)
+ ret = regmap_read_bypassed(gpio->regmap, reg, &val);
+ else
+ ret = regmap_read(gpio->regmap, reg, &val);
if (ret)
return ret;
@@ -227,6 +231,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
gpio->parent = config->parent;
gpio->regmap = config->regmap;
+ gpio->quirks = config->quirks;
gpio->ngpio_per_reg = config->ngpio_per_reg;
gpio->reg_stride = config->reg_stride;
gpio->reg_mask_xlate = config->reg_mask_xlate;
diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
index 334dd928042b..b0751a10fa4a 100644
--- a/include/linux/gpio/regmap.h
+++ b/include/linux/gpio/regmap.h
@@ -12,6 +12,17 @@ struct regmap;
#define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1))
#define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO)
+enum gpio_regmap_quirk {
+ /*
+ * For hardware where the (read-only) input and (write-only) output
+ * registers are aliased to the same offset. In this case the register
+ * must not be marked as volatile and a regcache must be used, to cache
+ * the write-only output values. Register reads for the input values
+ * will be performed by bypassing the cache.
+ */
+ GPIO_REGMAP_QUIRK_ALIASED_DATA = BIT(0),
+};
+
/**
* struct gpio_regmap_config - Description of a generic regmap gpio_chip.
* @parent: The parent device
@@ -31,6 +42,7 @@ struct regmap;
* @reg_stride: (Optional) May be set if the registers (of the
* same type, dat, set, etc) are not consecutive.
* @ngpio_per_reg: Number of GPIOs per register
+ * @quirks: Flags indicating GPIO chip hardware issues
* @irq_domain: (Optional) IRQ domain if the controller is
* interrupt-capable
* @reg_mask_xlate: (Optional) Translates base address and GPIO
@@ -73,6 +85,7 @@ struct gpio_regmap_config {
unsigned int reg_dir_out_base;
int reg_stride;
int ngpio_per_reg;
+ unsigned int quirks;
struct irq_domain *irq_domain;
int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
--
2.31.1
next prev parent reply other threads:[~2021-06-12 21:13 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-12 21:12 [PATCH v5 0/8] RTL8231 GPIO expander support Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 1/8] regmap: Support atomic forced uncached reads Sander Vanheule
2021-06-12 21:23 ` Andy Shevchenko
2021-06-14 10:33 ` Mark Brown
2021-06-12 21:12 ` Sander Vanheule [this message]
2021-06-12 21:29 ` [PATCH v5 2/8] gpio: regmap: Add quirk for aliased data registers Andy Shevchenko
2021-07-07 20:53 ` Sander Vanheule
2021-07-08 14:23 ` Mark Brown
2021-06-12 21:12 ` [PATCH v5 3/8] dt-bindings: leds: Binding for RTL8231 scan matrix Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 4/8] dt-bindings: mfd: Binding for RTL8231 Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 5/8] mfd: Add RTL8231 core device Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 6/8] pinctrl: Add RTL8231 pin control and GPIO support Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 7/8] leds: Add support for RTL8231 LED scan matrix Sander Vanheule
2021-06-12 21:12 ` [PATCH v5 8/8] MAINTAINERS: Add RTL8231 MFD driver Sander Vanheule
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