From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC0CC48BE6 for ; Wed, 16 Jun 2021 20:55:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C81B6613BD for ; Wed, 16 Jun 2021 20:55:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233771AbhFPU52 (ORCPT ); Wed, 16 Jun 2021 16:57:28 -0400 Received: from mga18.intel.com ([134.134.136.126]:4658 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233698AbhFPU50 (ORCPT ); Wed, 16 Jun 2021 16:57:26 -0400 IronPort-SDR: vgr2Wem75ct1II1HTo5e24PhBKOWxXVRR4x/dhv7zMZ9CEwGMHSH9NgGRnJZqEHRpfDChWqIBL JYGMlbkKcyBA== X-IronPort-AV: E=McAfee;i="6200,9189,10016"; a="193566112" X-IronPort-AV: E=Sophos;i="5.83,278,1616482800"; d="scan'208";a="193566112" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2021 13:55:12 -0700 IronPort-SDR: SSiWYl/RT9CXsxDerOaJR4O7AUUMNSrJPwsmLm4ltxbmkuI/egTIMOOQCaNKTr1Nplo/VYYrlU 94xi6SjyirRg== X-IronPort-AV: E=Sophos;i="5.83,278,1616482800"; d="scan'208";a="415878089" Received: from jamarin-mobl1.amr.corp.intel.com (HELO [10.209.105.29]) ([10.209.105.29]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2021 13:55:11 -0700 Subject: Re: [patch 00/41] x86/fpu: Spring cleaning and PKRU sanitizing To: Thomas Gleixner , LKML Cc: Andy Lutomirski , Dave Hansen , Fenghua Yu , Tony Luck , Yu-cheng Yu , Sebastian Andrzej Siewior , Borislav Petkov , Peter Zijlstra , Kan Liang References: <20210611161523.508908024@linutronix.de> <871r98vsjy.ffs@nanos.tec.linutronix.de> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <871r98vsjy.ffs@nanos.tec.linutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/11/21 5:24 PM, Thomas Gleixner wrote: > The Intel SDM states in volume 1, chapter 13.6 > > PROCESSOR TRACKING OF XSAVE-MANAGED STATE > > * PKRU state. PKRU state is in its initial configuration if the value > of the PKRU is 0. > > But that's just not true. > > wrpkru(0) > assert(!(xgetbv(1) & XFEATURE_PKRU); Hi Thomas, It's pretty clear that Intel's implementation was intentional. It was certainly no accident that it was implemented this way. I'm a bit confused why you expected to see XINUSE[PKRU]=0 up in your example. The CPU is *free* to set XINUSE[PKRU]=0, but it appears that the example expects that it *must* set XINUSE[PKRU]=0. I do wish the SDM had been excruciatingly explicit in defining: initial configuration vs. initial state All features in their "initial state" have their "initial configuration" values, but not all features with their "initial configuration" values are in their "initial state". > But the Intel SDM is blury about this: > > XINUSE denotes the state-component bitmap corresponding to the init > optimization. If XINUSE[i] = 0, state component i is known to be in > its initial configuration; otherwise XINUSE[i] = 1. It is possible for > XINUSE[i] to be 1 even when state component i is in its initial > configuration. On a processor that does not support the init > optimization, XINUSE[i] is always 1 for every value of i. > > IOW there is no consistency vs. XINUSE and initial state guaranteed at > all. So why should the kernel worry about this? Exactly, there is really no consistency guarantee. This was written to give the CPU designers some flexibility so that they could opt to omit "init tracker" hardware if they chose. Or, so that they could be a bit lazy about implementing one. Imagine what would happen if the AMD PKRU init tracking behavior (write all 0's, get XINUSE[PKRU]=0) was *required* XSAVE behavior. Every ZMM register write would potentially need to go checking ~2k of state to see if the rest of the state is all 0's. > If anyone cares about consistency of XINUSE vs. the actual component > state then please redirect the complaints to INTEL. I think we can take a _bit_ of the blame on the kernel side too. The kernel has very good reasons for managing PKRU with WRPKRU instead of XSAVE. *But*, it also tossed out XINUSE[PKRU] consistency in the process. I'm not sure we should be looking to the hardware to bring that back. > Either the hardware folks get their act together or software which > relies on consistency (cough, cough) like rr has to cope with it. > > Making the kernel to pretend that all of this is consistent under all > circumstances is a futile attempt to ignore reality. > > This inconsistency can only be fixed in hardware/ucode. End of story. I agree with this. If it's going to be fixed, the kernel simply doesn't have the tools to do it. We either need new ISA or new hardware/ucode. I'm just not convinced it's worth fixing for PKRU.