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spf=pass smtp.mailfrom=patrice.chotard@foss.st.com Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14O7VcL3003876; Mon, 24 May 2021 09:40:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=CzwSik3stdWuIG+rOtbcamUDfA7zpreRnKUroFiVgFs=; b=1/75g9YMNVzF9zn+zAxnupP7F/2YBwFt3UACGMhrP0YJuf5gr7HgE+20fwmXHiSltxs9 yPEtdJgVDISEFR0tgbL/MEHEMo4hdKJ46LB/nW5myWHlBAqTD7tpQYI/xf1BVi6yFx1G 5tzOMfWW7YjhtU8f5jdEtMohSM0cExt5D7opiCqL7WH7inyxA5S6JMTzoAJqjvwQcl9l g0jQLYQqdk1fBpyd+Yux5MCFRIjulgHS6d/t53ZoTWQdHE2ma040XXWQCL3qTdNa9cDT gNkScMS1Pn8AfbhVfBx0udih8VLZNRpbthF6TFXQfVGtetYXRVfYJMo8rV2TfpoKehYF ZA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 38qk3y44bs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 May 2021 09:40:08 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E459110002A; Mon, 24 May 2021 09:40:07 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B6D0F21B53D; Mon, 24 May 2021 09:40:07 +0200 (CEST) Received: from lmecxl0573.lme.st.com (10.75.127.47) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 24 May 2021 09:40:06 +0200 Subject: Re: [PATCH] spi: stm32_qspi: Fix short data write operation To: Daniil Stas , CC: Patrick Delaunay References: <20210523222449.1495352-1-daniil.stas@posteo.net> <20210523222449.1495352-2-daniil.stas@posteo.net> From: Patrice CHOTARD Message-ID: <4e531f04-4228-05e6-6bdb-32c29becb38f@foss.st.com> Date: Mon, 24 May 2021 09:40:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210523222449.1495352-2-daniil.stas@posteo.net> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-24_04:2021-05-20, 2021-05-24 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Hi Daniil On 5/24/21 12:24 AM, Daniil Stas wrote: > TCF flag only means that all data was sent to FIFO. To check if the > data was sent out of FIFO we should also wait for the BUSY flag to be > cleared. Otherwise there is a race condition which can lead to > inability to write short (one byte long) data. > > Signed-off-by: Daniil Stas > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > drivers/spi/stm32_qspi.c | 29 +++++++++++++++-------------- > 1 file changed, 15 insertions(+), 14 deletions(-) > > diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c > index 4acc9047b9..8f4aabc3d1 100644 > --- a/drivers/spi/stm32_qspi.c > +++ b/drivers/spi/stm32_qspi.c > @@ -148,23 +148,24 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv, > const struct spi_mem_op *op) > { > u32 sr; > - int ret; > - > - if (!op->data.nbytes) > - return _stm32_qspi_wait_for_not_busy(priv); > + int ret = 0; > > - ret = readl_poll_timeout(&priv->regs->sr, sr, > - sr & STM32_QSPI_SR_TCF, > - STM32_QSPI_CMD_TIMEOUT_US); > - if (ret) { > - log_err("cmd timeout (stat:%#x)\n", sr); > - } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { > - log_err("transfer error (stat:%#x)\n", sr); > - ret = -EIO; > + if (op->data.nbytes) { > + ret = readl_poll_timeout(&priv->regs->sr, sr, > + sr & STM32_QSPI_SR_TCF, > + STM32_QSPI_CMD_TIMEOUT_US); > + if (ret) { > + log_err("cmd timeout (stat:%#x)\n", sr); > + } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { > + log_err("transfer error (stat:%#x)\n", sr); > + ret = -EIO; > + } > + /* clear flags */ > + writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); > } > > - /* clear flags */ > - writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr); > + if (!ret) > + ret = _stm32_qspi_wait_for_not_busy(priv); > > return ret; > } > Have you got a simple test to reproduce the described race condition ? Thanks Patrice