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Thu, 28 Mar 2024 15:34:52 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-333-gbfea15422e-fm-20240327.001-gbfea1542 MIME-Version: 1.0 Message-Id: <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> In-Reply-To: <20240328124916.293173-3-pulehui@huaweicloud.com> References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> Date: Thu, 28 Mar 2024 15:34:31 -0400 From: "Stefan O'Rear" To: "Pu Lehui" , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org Cc: =?UTF-8?Q?Bj=C3=B6rn_T=C3=B6pel?= , "Alexei Starovoitov" , "Daniel Borkmann" , "Andrii Nakryiko" , "Martin KaFai Lau" , "Eduard Zingerman" , "Song Liu" , "Yonghong Song" , "John Fastabend" , "KP Singh" , "Stanislav Fomichev" , "Hao Luo" , "Jiri Olsa" , "Mykola Lysenko" , "Manu Bretelle" , "Pu Lehui" Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_123458_869367_35785D7D X-CRM114-Status: GOOD ( 16.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Mar 28, 2024, at 8:49 AM, Pu Lehui wrote: > From: Pu Lehui > > This patch relaxes the restrictions on the Zbb instructions. The hardware > is capable of recognizing the Zbb instructions independently, eliminating > the need for reliance on kernel compile configurations. This doesn't make sense to me. RISCV_ISA_ZBB is defined as: Adds support to dynamically detect the presence of the ZBB extension (basic bit manipulation) and enable its usage. In other words, RISCV_ISA_ZBB=n should disable everything that attempts to detect Zbb at runtime. It is mostly relevant for code size reduction, which is relevant for BPF since if RISCV_ISA_ZBB=n all rvzbb_enabled() checks can be constant-folded. If BPF needs to become an exception (why?), this should be mentioned in Kconfig. -s > Signed-off-by: Pu Lehui > --- > arch/riscv/net/bpf_jit.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 5fc374ed98ea..bcf109b88df5 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -20,7 +20,7 @@ static inline bool rvc_enabled(void) > > static inline bool rvzbb_enabled(void) > { > - return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > + return riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > } > > enum { > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fout4-smtp.messagingengine.com (fout4-smtp.messagingengine.com [103.168.172.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A124142AA1; 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Thu, 28 Mar 2024 15:34:52 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-333-gbfea15422e-fm-20240327.001-gbfea1542 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <3ed9fe94-2610-41eb-8a00-a9f37fcf2b1a@app.fastmail.com> In-Reply-To: <20240328124916.293173-3-pulehui@huaweicloud.com> References: <20240328124916.293173-1-pulehui@huaweicloud.com> <20240328124916.293173-3-pulehui@huaweicloud.com> Date: Thu, 28 Mar 2024 15:34:31 -0400 From: "Stefan O'Rear" To: "Pu Lehui" , bpf@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org Cc: =?UTF-8?Q?Bj=C3=B6rn_T=C3=B6pel?= , "Alexei Starovoitov" , "Daniel Borkmann" , "Andrii Nakryiko" , "Martin KaFai Lau" , "Eduard Zingerman" , "Song Liu" , "Yonghong Song" , "John Fastabend" , "KP Singh" , "Stanislav Fomichev" , "Hao Luo" , "Jiri Olsa" , "Mykola Lysenko" , "Manu Bretelle" , "Pu Lehui" Subject: Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions Content-Type: text/plain On Thu, Mar 28, 2024, at 8:49 AM, Pu Lehui wrote: > From: Pu Lehui > > This patch relaxes the restrictions on the Zbb instructions. The hardware > is capable of recognizing the Zbb instructions independently, eliminating > the need for reliance on kernel compile configurations. This doesn't make sense to me. RISCV_ISA_ZBB is defined as: Adds support to dynamically detect the presence of the ZBB extension (basic bit manipulation) and enable its usage. In other words, RISCV_ISA_ZBB=n should disable everything that attempts to detect Zbb at runtime. It is mostly relevant for code size reduction, which is relevant for BPF since if RISCV_ISA_ZBB=n all rvzbb_enabled() checks can be constant-folded. If BPF needs to become an exception (why?), this should be mentioned in Kconfig. -s > Signed-off-by: Pu Lehui > --- > arch/riscv/net/bpf_jit.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 5fc374ed98ea..bcf109b88df5 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -20,7 +20,7 @@ static inline bool rvc_enabled(void) > > static inline bool rvzbb_enabled(void) > { > - return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > + return riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > } > > enum { > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv