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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id x18-20020a170906b09200b00a47df55cf5esm3123065ejy.13.2024.03.26.14.02.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Mar 2024 14:02:29 -0700 (PDT) Message-ID: <236a104c-fc16-4b3d-9a00-e16517c00e3a@linaro.org> Date: Tue, 26 Mar 2024 22:02:27 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode To: Bjorn Andersson , Neil Armstrong Cc: Luca Weiss , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240229-topic-sm8x50-upstream-phy-combo-typec-mux-v1-0-07e24a231840@linaro.org> <7a7aa05f-9ae6-4ca0-a423-224fc78fbd0c@linaro.org> Content-Language: en-US From: Konrad Dybcio Autocrypt: addr=konrad.dybcio@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16.03.2024 5:01 PM, Bjorn Andersson wrote: > On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote: >> On 15/03/2024 18:19, Luca Weiss wrote: >>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote: >>>> Register a typec mux in order to change the PHY mode on the Type-C >>>> mux events depending on the mode and the svid when in Altmode setup. >>>> >>>> The DisplayPort phy should be left enabled if is still powered on >>>> by the DRM DisplayPort controller, so bail out until the DisplayPort >>>> PHY is not powered off. >>>> >>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states >>>> will be set in between of USB-Only, Combo and DisplayPort Only so >>>> this will leave enough time to the DRM DisplayPort controller to >>>> turn of the DisplayPort PHY. >>>> >>>> The patchset also includes bindings changes and DT changes. >>>> >>>> This has been successfully tested on an SM8550 board, but the >>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort, >>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works >>>> as expected. >>>> >>>> The DisplayPort 4 lanes setup can be check with: >>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug >>>> name = msm_dp >>>> drm_dp_link >>>> rate = 540000 >>>> num_lanes = 4 >>> >>> Hi Neil, >>> >>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I >>> haven't had any success so far. >>> > [..] >>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached >>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11 >> >> Interesting #1 means the 4 lanes are not physically connected to the other side, >> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY, >> or some fixups in the init tables. >> > > I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the > same outcome. Looking at the AUX reads, after switching to 4-lane the > link training is failing on all 4 lanes, in contrast to succeeding only > on the first 2 if you e.g. forget to mux the other two. > > As such, my expectation is that there's something wrong in the QMP PHY > (or possibly redriver) for this platform. Do we have any downstream tag where 4lane dp works? I'm willing to believe the PHY story.. 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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id x18-20020a170906b09200b00a47df55cf5esm3123065ejy.13.2024.03.26.14.02.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Mar 2024 14:02:29 -0700 (PDT) Message-ID: <236a104c-fc16-4b3d-9a00-e16517c00e3a@linaro.org> Date: Tue, 26 Mar 2024 22:02:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode To: Bjorn Andersson , Neil Armstrong Cc: Luca Weiss , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240229-topic-sm8x50-upstream-phy-combo-typec-mux-v1-0-07e24a231840@linaro.org> <7a7aa05f-9ae6-4ca0-a423-224fc78fbd0c@linaro.org> Content-Language: en-US From: Konrad Dybcio Autocrypt: addr=konrad.dybcio@linaro.org; keydata= xsFNBF9ALYUBEADWAhxdTBWrwAgDQQzc1O/bJ5O7b6cXYxwbBd9xKP7MICh5YA0DcCjJSOum BB/OmIWU6X+LZW6P88ZmHe+KeyABLMP5s1tJNK1j4ntT7mECcWZDzafPWF4F6m4WJOG27kTJ HGWdmtO+RvadOVi6CoUDqALsmfS3MUG5Pj2Ne9+0jRg4hEnB92AyF9rW2G3qisFcwPgvatt7 TXD5E38mLyOPOUyXNj9XpDbt1hNwKQfiidmPh5e7VNAWRnW1iCMMoKqzM1Anzq7e5Afyeifz zRcQPLaqrPjnKqZGL2BKQSZDh6NkI5ZLRhhHQf61fkWcUpTp1oDC6jWVfT7hwRVIQLrrNj9G MpPzrlN4YuAqKeIer1FMt8cq64ifgTzxHzXsMcUdclzq2LTk2RXaPl6Jg/IXWqUClJHbamSk t1bfif3SnmhA6TiNvEpDKPiT3IDs42THU6ygslrBxyROQPWLI9IL1y8S6RtEh8H+NZQWZNzm UQ3imZirlPjxZtvz1BtnnBWS06e7x/UEAguj7VHCuymVgpl2Za17d1jj81YN5Rp5L9GXxkV1 aUEwONM3eCI3qcYm5JNc5X+JthZOWsbIPSC1Rhxz3JmWIwP1udr5E3oNRe9u2LIEq+wH/toH kpPDhTeMkvt4KfE5m5ercid9+ZXAqoaYLUL4HCEw+HW0DXcKDwARAQABzShLb25yYWQgRHli Y2lvIDxrb25yYWQuZHliY2lvQGxpbmFyby5vcmc+wsGOBBMBCAA4FiEEU24if9oCL2zdAAQV R4cBcg5dfFgFAmQ5bqwCGwMFCwkIBwIGFQoJCAsCBBYCAwECHgECF4AACgkQR4cBcg5dfFjO BQ//YQV6fkbqQCceYebGg6TiisWCy8LG77zV7DB0VMIWJv7Km7Sz0QQrHQVzhEr3trNenZrf yy+o2tQOF2biICzbLM8oyQPY8B///KJTWI2khoB8IJSJq3kNG68NjPg2vkP6CMltC/X3ohAo xL2UgwN5vj74QnlNneOjc0vGbtA7zURNhTz5P/YuTudCqcAbxJkbqZM4WymjQhe0XgwHLkiH 5LHSZ31MRKp/+4Kqs4DTXMctc7vFhtUdmatAExDKw8oEz5NbskKbW+qHjW1XUcUIrxRr667V GWH6MkVceT9ZBrtLoSzMLYaQXvi3sSAup0qiJiBYszc/VOu3RbIpNLRcXN3KYuxdQAptacTE mA+5+4Y4DfC3rUSun+hWLDeac9z9jjHm5rE998OqZnOU9aztbd6zQG5VL6EKgsVXAZD4D3RP x1NaAjdA3MD06eyvbOWiA5NSzIcC8UIQvgx09xm7dThCuQYJR4Yxjd+9JPJHI6apzNZpDGvQ BBZzvwxV6L1CojUEpnilmMG1ZOTstktWpNzw3G2Gis0XihDUef0MWVsQYJAl0wfiv/0By+XK mm2zRR+l/dnzxnlbgJ5pO0imC2w0TVxLkAp0eo0LHw619finad2u6UPQAkZ4oj++iIGrJkt5 Lkn2XgB+IW8ESflz6nDY3b5KQRF8Z6XLP0+IEdLOOARkOW7yEgorBgEEAZdVAQUBAQdAwmUx xrbSCx2ksDxz7rFFGX1KmTkdRtcgC6F3NfuNYkYDAQgHwsF2BBgBCAAgFiEEU24if9oCL2zd AAQVR4cBcg5dfFgFAmQ5bvICGwwACgkQR4cBcg5dfFju1Q//Xta1ShwL0MLSC1KL1lXGXeRM 8arzfyiB5wJ9tb9U/nZvhhdfilEDLe0jKJY0RJErbdRHsalwQCrtq/1ewQpMpsRxXzAjgfRN jc4tgxRWmI+aVTzSRpywNahzZBT695hMz81cVZJoZzaV0KaMTlSnBkrviPz1nIGHYCHJxF9r cIu0GSIyUjZ/7xslxdvjpLth16H27JCWDzDqIQMtg61063gNyEyWgt1qRSaK14JIH/DoYRfn jfFQSC8bffFjat7BQGFz4ZpRavkMUFuDirn5Tf28oc5ebe2cIHp4/kajTx/7JOxWZ80U70mA cBgEeYSrYYnX+UJsSxpzLc/0sT1eRJDEhI4XIQM4ClIzpsCIN5HnVF76UQXh3a9zpwh3dk8i bhN/URmCOTH+LHNJYN/MxY8wuukq877DWB7k86pBs5IDLAXmW8v3gIDWyIcgYqb2v8QO2Mqx YMqL7UZxVLul4/JbllsQB8F/fNI8AfttmAQL9cwo6C8yDTXKdho920W4WUR9k8NT/OBqWSyk bGqMHex48FVZhexNPYOd58EY9/7mL5u0sJmo+jTeb4JBgIbFPJCFyng4HwbniWgQJZ1WqaUC nas9J77uICis2WH7N8Bs9jy0wQYezNzqS+FxoNXmDQg2jetX8en4bO2Di7Pmx0jXA4TOb9TM izWDgYvmBE8= In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240326_140232_784167_15A06CC8 X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 16.03.2024 5:01 PM, Bjorn Andersson wrote: > On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote: >> On 15/03/2024 18:19, Luca Weiss wrote: >>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote: >>>> Register a typec mux in order to change the PHY mode on the Type-C >>>> mux events depending on the mode and the svid when in Altmode setup. >>>> >>>> The DisplayPort phy should be left enabled if is still powered on >>>> by the DRM DisplayPort controller, so bail out until the DisplayPort >>>> PHY is not powered off. >>>> >>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states >>>> will be set in between of USB-Only, Combo and DisplayPort Only so >>>> this will leave enough time to the DRM DisplayPort controller to >>>> turn of the DisplayPort PHY. >>>> >>>> The patchset also includes bindings changes and DT changes. >>>> >>>> This has been successfully tested on an SM8550 board, but the >>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort, >>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works >>>> as expected. >>>> >>>> The DisplayPort 4 lanes setup can be check with: >>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug >>>> name = msm_dp >>>> drm_dp_link >>>> rate = 540000 >>>> num_lanes = 4 >>> >>> Hi Neil, >>> >>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I >>> haven't had any success so far. >>> > [..] >>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached >>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11 >> >> Interesting #1 means the 4 lanes are not physically connected to the other side, >> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY, >> or some fixups in the init tables. >> > > I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the > same outcome. Looking at the AUX reads, after switching to 4-lane the > link training is failing on all 4 lanes, in contrast to succeeding only > on the first 2 if you e.g. forget to mux the other two. > > As such, my expectation is that there's something wrong in the QMP PHY > (or possibly redriver) for this platform. Do we have any downstream tag where 4lane dp works? I'm willing to believe the PHY story.. Konrad -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy