* [PATCH 0/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
@ 2024-05-16 17:10 Daniel Henrique Barboza
2024-05-16 17:10 ` [PATCH 1/1] " Daniel Henrique Barboza
0 siblings, 1 reply; 4+ messages in thread
From: Daniel Henrique Barboza @ 2024-05-16 17:10 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, akihiko.odaki, alex.bennee, mjt, Daniel Henrique Barboza
Hi,
Commit 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
changed 'reg_width' for vector regs, a change that I believe to be
unintended, and we're unable to print vector regs in GDB ATM.
The following is a gdb output of a simple program running with
qemu-riscv64 when trying to print the value of 'v1' after a 'vle'
insns:
(gdb) p $v1
$1 = {q = 0x0, l = 0x0, w = 0x0, s = {57920}, b = {64, 226}}
(gdb)
After this patch:
(gdb) p $v1
$1 = {q = {9781192033638379298842687819604544}, l = {530239482618432, 530239482618432}, w = {123456, 123456,
123456, 123456}, s = {57920, 1, 57920, 1, 57920, 1, 57920, 1}, b = {64, 226, 1, 0, 64, 226, 1, 0, 64, 226, 1,
0, 64, 226, 1, 0}}
(gdb)
Michael, this is a good pick for qemu-stable.
Daniel Henrique Barboza (1):
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.44.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-05-16 17:10 [PATCH 0/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() Daniel Henrique Barboza
@ 2024-05-16 17:10 ` Daniel Henrique Barboza
2024-05-17 1:04 ` LIU Zhiwei
2024-05-17 17:56 ` Alex Bennée
0 siblings, 2 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2024-05-16 17:10 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, akihiko.odaki, alex.bennee, mjt, Daniel Henrique Barboza,
Robin Dapp
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d0cc5762c2..358158c42a 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
{
RISCVCPU *cpu = RISCV_CPU(cs);
- int reg_width = cpu->cfg.vlenb;
+ int reg_width = cpu->cfg.vlenb << 3;
GDBFeatureBuilder builder;
int i;
--
2.44.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-05-16 17:10 ` [PATCH 1/1] " Daniel Henrique Barboza
@ 2024-05-17 1:04 ` LIU Zhiwei
2024-05-17 17:56 ` Alex Bennée
1 sibling, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2024-05-17 1:04 UTC (permalink / raw
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, palmer,
akihiko.odaki, alex.bennee, mjt, Robin Dapp
On 2024/5/17 1:10, Daniel Henrique Barboza wrote:
> Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
> in bytes, when in this context we want 'reg_width' as the length in
> bits.
>
> Fix 'reg_width' back to the value in bits like 7cb59921c05a
> ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
> beforehand.
>
> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
> Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> ---
> target/riscv/gdbstub.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index d0cc5762c2..358158c42a 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
> static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> - int reg_width = cpu->cfg.vlenb;
> + int reg_width = cpu->cfg.vlenb << 3;
> GDBFeatureBuilder builder;
> int i;
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-05-16 17:10 ` [PATCH 1/1] " Daniel Henrique Barboza
2024-05-17 1:04 ` LIU Zhiwei
@ 2024-05-17 17:56 ` Alex Bennée
1 sibling, 0 replies; 4+ messages in thread
From: Alex Bennée @ 2024-05-17 17:56 UTC (permalink / raw
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, akihiko.odaki, mjt, Robin Dapp
Daniel Henrique Barboza <dbarboza@ventanamicro.com> writes:
> Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
> in bytes, when in this context we want 'reg_width' as the length in
> bits.
>
> Fix 'reg_width' back to the value in bits like 7cb59921c05a
> ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
> beforehand.
>
> Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
> Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/gdbstub.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index d0cc5762c2..358158c42a 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
> static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> - int reg_width = cpu->cfg.vlenb;
> + int reg_width = cpu->cfg.vlenb << 3;
You could consider renaming the var to reg_bits for clarity but
otherwise:
Acked-by: Alex Bennée <alex.bennee@linaro.org>
> GDBFeatureBuilder builder;
> int i;
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 4+ messages in thread
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2024-05-16 17:10 [PATCH 0/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() Daniel Henrique Barboza
2024-05-16 17:10 ` [PATCH 1/1] " Daniel Henrique Barboza
2024-05-17 1:04 ` LIU Zhiwei
2024-05-17 17:56 ` Alex Bennée
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