* [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs
@ 2024-05-01 16:22 Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 01/22] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC Jonas Karlman
` (21 more replies)
0 siblings, 22 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
This series adds support for new clocks used in Linux kernel v6.8 DTs,
sync device trees with v6.8 and updates board defconfigs to enable
common features that is known to be working on RK3399 boards.
A follow up series will be sent that fully move RK3399 and a few other
RK SoCs that recently synced DTs to v6.8 to use OF_UPSTREAM.
Changes in v2:
- Split series in two, this is the second part
- Implement partial instead of dummy support for SCLK_PCIEPHY_REF
- Temporarily add ethernet0 alias to rk3399-u-boot.dtsi
- Keep dfi node for all boot phases
- Only enable AHCI/SCSI on boards that have PCIe slot or board vendor
sell a SATA HAT
- Collect r-b tags
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
Boot times after this series using rock-pi-4-rk3399:
=> bootstage report
Timer summary in microseconds (12 records):
Mark Elapsed Stage
172,783 SPL
434,458 261,675 end phase
8,810 8,810 board_init_f
1,381,128 1,372,318 board_init_r
2,304,264 923,136 eth_common_init
2,472,339 168,075 eth_initialize
2,479,534 7,195 main_loop
2,479,847 313 cli_loop
Accumulated time:
29,672 dm_spl
893,082 dm_f
12,854 of_live
13,792 dm_r
This series depends on the following series:
- rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC [1]
A copy of this series and its depend can be found at [2]
[1] https://patchwork.ozlabs.org/cover/1929673/
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v2-part2
Jonas Karlman (22):
clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC
clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock
clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support
rockchip: rk3399: Sync SoC DT from Linux kernel v6.8
rockchip: rk3399-gru: Sync DT from Linux kernel v6.8
rockchip: rk3399-puma: Sync DT from Linux kernel v6.8
rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig
rockchip: rk3399-eaidk-610: Sync DT from v6.8 and update defconfig
rockchip: rk3399-leez: Sync DT from v6.8 and update defconfig
rockchip: rk3399-evb: Sync DT from v6.8 and update defconfig
rockchip: rk3399-firefly: Sync DT from v6.8 and update defconfig
rockchip: rk3399-orangepi: Sync DT from v6.8 and update defconfig
rockchip: rk3399-roc-pc: Sync DT from v6.8 and update defconfig
rockchip: rk3399-nanopi-4: Sync DT from v6.8 and update defconfig
rockchip: rk3399-rock960: Sync DT from v6.8 and update defconfig
rockchip: rk3399-khadas: Sync DT from v6.8 and update defconfig
rockchip: rk3399-rock-pi-4: Sync DT from v6.8 and update defconfig
rockchip: rk3399-rockpro64: Sync DT from v6.8 and update defconfig
rockchip: rk3399-pinebook-pro: Sync DT from v6.8 and update defconfig
rockchip: rk3399-pinephone-pro: Sync DT from v6.8 and update defconfig
rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++
arch/arm/dts/rk3399-eaidk-610.dts | 3 +-
arch/arm/dts/rk3399-evb-u-boot.dtsi | 11 +-
arch/arm/dts/rk3399-evb.dts | 3 +-
arch/arm/dts/rk3399-ficus.dts | 4 +
arch/arm/dts/rk3399-firefly.dts | 17 +-
arch/arm/dts/rk3399-gru-bob.dts | 8 +-
arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++-
arch/arm/dts/rk3399-gru-kevin.dts | 3 +-
arch/arm/dts/rk3399-gru-u-boot.dtsi | 10 +-
arch/arm/dts/rk3399-gru.dtsi | 52 +++-
arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 +
arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 5 +
arch/arm/dts/rk3399-khadas-edge-v.dts | 4 +
arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +-
arch/arm/dts/rk3399-leez-p710.dts | 8 +-
arch/arm/dts/rk3399-nanopc-t4.dts | 2 +-
arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +---
arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +-
arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +-
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 4 +
arch/arm/dts/rk3399-nanopi4.dtsi | 7 +-
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +-
arch/arm/dts/rk3399-opp.dtsi | 6 +-
arch/arm/dts/rk3399-orangepi.dts | 12 +-
arch/arm/dts/rk3399-pinebook-pro.dts | 24 +-
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 12 +
arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 16 +-
arch/arm/dts/rk3399-puma-haikou.dts | 42 ++-
arch/arm/dts/rk3399-puma.dtsi | 17 +-
arch/arm/dts/rk3399-roc-pc.dtsi | 15 +-
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 +
arch/arm/dts/rk3399-rock-4c-plus.dts | 1 +
arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 +
arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +-
arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 +
arch/arm/dts/rk3399-rock-pi-4c.dts | 10 +
arch/arm/dts/rk3399-rock960.dtsi | 5 +-
arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++-
arch/arm/dts/rk3399-u-boot.dtsi | 54 ++--
arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++--
arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +-
.../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++
configs/eaidk-610-rk3399_defconfig | 11 +-
configs/evb-rk3399_defconfig | 6 +-
configs/ficus-rk3399_defconfig | 22 +-
configs/firefly-rk3399_defconfig | 9 +-
configs/khadas-edge-captain-rk3399_defconfig | 29 +-
configs/khadas-edge-rk3399_defconfig | 27 +-
configs/khadas-edge-v-rk3399_defconfig | 29 +-
configs/leez-rk3399_defconfig | 10 +-
configs/nanopc-t4-rk3399_defconfig | 10 +-
configs/nanopi-m4-2gb-rk3399_defconfig | 18 +-
configs/nanopi-m4-rk3399_defconfig | 18 +-
configs/nanopi-m4b-rk3399_defconfig | 18 +-
configs/nanopi-neo4-rk3399_defconfig | 11 +-
configs/nanopi-r4s-rk3399_defconfig | 11 +-
configs/orangepi-rk3399_defconfig | 10 +-
configs/pinebook-pro-rk3399_defconfig | 6 +-
configs/pinephone-pro-rk3399_defconfig | 8 +-
configs/roc-pc-mezzanine-rk3399_defconfig | 7 +-
configs/roc-pc-rk3399_defconfig | 7 +-
configs/rock-4c-plus-rk3399_defconfig | 24 +-
configs/rock-4se-rk3399_defconfig | 23 +-
configs/rock-pi-4-rk3399_defconfig | 8 +
configs/rock-pi-4c-rk3399_defconfig | 24 +-
configs/rock-pi-n10-rk3399pro_defconfig | 8 +-
configs/rock960-rk3399_defconfig | 10 +-
configs/rockpro64-rk3399_defconfig | 7 +-
drivers/clk/rockchip/clk_rk3399.c | 67 +++-
include/dt-bindings/clock/rk3399-cru.h | 30 +-
72 files changed, 1462 insertions(+), 325 deletions(-)
--
2.43.2
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 01/22] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 02/22] clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock Jonas Karlman
` (20 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-cru.h with one from Linux kernel v6.2+ and fix use of the
SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
The dt-bindings/clock/rk3399-cru.h file could instead be dropped to pick
an updated version from dts/upstream. However for revewability and being
able to cherry-pick this series to v2024.04 this patch instead sync the
file, it will be removed in another series that switch to OF_UPSTREAM.
---
arch/arm/dts/rk3399-u-boot.dtsi | 2 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +-
include/dt-bindings/clock/rk3399-cru.h | 30 ++++++++++++++------------
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 4298552dd999..0357d6273b96 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -56,7 +56,7 @@
0x0 0xffa8c000 0x0 0x1000>;
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DDRCLK>;
+ clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
bootph-all;
};
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 80f65a237e8e..f0ce54067f8c 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
* return 0 to satisfy clk_set_defaults during device probe.
*/
return 0;
- case SCLK_DDRCLK:
+ case SCLK_DDRC:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
case PCLK_EFUSE1024NS:
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 211faf8fa891..39169d94a44e 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
@@ -121,16 +122,17 @@
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
-#define SCLK_USBPHY0_480M_SRC 168
-#define SCLK_USBPHY1_480M_SRC 169
-#define SCLK_DDRCLK 170
-#define SCLK_TESTOUT2 171
+#define SCLK_DDRC 168
+#define SCLK_TESTCLKOUT1 169
+#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180
#define DCLK_VOP1 181
#define DCLK_VOP0_DIV 182
#define DCLK_VOP1_DIV 183
#define DCLK_M0_PERILP 184
+#define DCLK_VOP0_FRAC 185
+#define DCLK_VOP1_FRAC 186
#define FCLK_CM0S 190
@@ -545,8 +547,8 @@
#define SRST_H_PERILP0 171
#define SRST_H_PERILP0_NOC 172
#define SRST_ROM 173
-#define SRST_CRYPTO_S 174
-#define SRST_CRYPTO_M 175
+#define SRST_CRYPTO0_S 174
+#define SRST_CRYPTO0_M 175
/* cru_softrst_con11 */
#define SRST_P_DCF 176
@@ -554,7 +556,7 @@
#define SRST_CM0S 178
#define SRST_CM0S_DBG 179
#define SRST_CM0S_PO 180
-#define SRST_CRYPTO 181
+#define SRST_CRYPTO0 181
#define SRST_P_PERILP1_SGRF 182
#define SRST_P_PERILP1_GRF 183
#define SRST_CRYPTO1_S 184
@@ -592,13 +594,13 @@
#define SRST_P_SPI0 214
#define SRST_P_SPI1 215
#define SRST_P_SPI2 216
-#define SRST_P_SPI4 217
-#define SRST_P_SPI5 218
+#define SRST_P_SPI3 217
+#define SRST_P_SPI4 218
#define SRST_SPI0 219
#define SRST_SPI1 220
#define SRST_SPI2 221
-#define SRST_SPI4 222
-#define SRST_SPI5 223
+#define SRST_SPI3 222
+#define SRST_SPI4 223
/* cru_softrst_con14 */
#define SRST_I2S0_8CH 224
@@ -720,8 +722,8 @@
#define SRST_H_CM0S_NOC 3
#define SRST_DBG_CM0S 4
#define SRST_PO_CM0S 5
-#define SRST_P_SPI3 6
-#define SRST_SPI3 7
+#define SRST_P_SPI6 6
+#define SRST_SPI6 7
#define SRST_P_TIMER_0_1 8
#define SRST_P_TIMER_0 9
#define SRST_P_TIMER_1 10
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 02/22] clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 01/22] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock Jonas Karlman
` (19 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to
400 MHz using an assigned-clock-rates prop of the CRU node.
U-Boot does not use or need this clock so add dummy support for getting
and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an
updated rk3399.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
---
drivers/clk/rockchip/clk_rk3399.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index f0ce54067f8c..5934771b4096 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -971,6 +971,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
break;
case PCLK_ALIVE:
case PCLK_WDT:
@@ -1061,6 +1062,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 01/22] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 02/22] clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-06 10:32 ` Kever Yang
2024-05-06 11:07 ` Quentin Schulz
2024-05-01 16:22 ` [PATCH v2 04/22] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support Jonas Karlman
` (18 subsequent siblings)
21 siblings, 2 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
use of 24 MHz parent and rate.
Add improved support for setting parent and rate of the pciephy refclk
to driver to better support assign-clock props for pciephy refclk in DT.
This limited implementation only support setting 24 or 100 MHz rate,
and expect npll and clk_pciephy_ref100m divider to use default values.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
---
drivers/clk/rockchip/clk_rk3399.c | 59 +++++++++++++++++++++++++++++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5934771b4096..0b3223611a32 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
return rk3399_saradc_get_clk(cru);
}
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
+{
+ if (readl(&cru->clksel_con[18]) & BIT(10))
+ return 100 * MHz;
+ else
+ return OSC_HZ;
+}
+
+static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz)
+{
+ if (hz == 100 * MHz)
+ rk_setreg(&cru->clksel_con[18], BIT(10));
+ else if (hz == OSC_HZ)
+ rk_clrreg(&cru->clksel_con[18], BIT(10));
+ else
+ return -EINVAL;
+
+ return rk3399_pciephy_get_clk(cru);
+}
+
static ulong rk3399_clk_get_rate(struct clk *clk)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -967,6 +987,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_SARADC:
rate = rk3399_saradc_get_clk(priv->cru);
break;
+ case SCLK_PCIEPHY_REF:
+ rate = rk3399_pciephy_get_clk(priv->cru);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
@@ -1058,6 +1081,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SARADC:
ret = rk3399_saradc_set_clk(priv->cru, rate);
break;
+ case SCLK_PCIEPHY_REF:
+ ret = rk3399_pciephy_set_clk(priv->cru, rate);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
@@ -1108,12 +1134,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
return -EINVAL;
}
+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ int ret;
+
+ if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+ rk_setreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "xin24m")) {
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
struct clk *parent)
{
switch (clk->id) {
case SCLK_RMII_SRC:
return rk3399_gmac_set_parent(clk, parent);
+ case SCLK_PCIEPHY_REF:
+ return rk3399_pciephy_set_parent(clk, parent);
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1204,7 +1257,8 @@ static int rk3399_clk_enable(struct clk *clk)
rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1298,7 +1352,8 @@ static int rk3399_clk_disable(struct clk *clk)
rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 04/22] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (2 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 05/22] rockchip: rk3399: Sync SoC DT from Linux kernel v6.8 Jonas Karlman
` (17 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix
reference clock period configuration.
Also replace use of 24000000 with the OSC_HZ constant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tags
---
drivers/clk/rockchip/clk_rk3399.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 0b3223611a32..67b2c05ec9ed 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -976,7 +976,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
- return 24000000;
+ case SCLK_USB3OTG0_REF:
+ case SCLK_USB3OTG1_REF:
+ return OSC_HZ;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 05/22] rockchip: rk3399: Sync SoC DT from Linux kernel v6.8
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (3 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 04/22] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 06/22] rockchip: rk3399-gru: Sync " Jonas Karlman
` (16 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync RK3399 SoC common .dtsi-files from Linux kernel v6.8.
The ethernet0 alias is moved to rk3399-u-boot.dtsi in this patch, the
alias will be added in board specific .dts-files and finally removed
from rk3399-u-boot.dtsi in following patches.
The rng node is replaced with crypto0 and crypto1, both can supply
random numbers.
There is no other intended change with this patch.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Add ethernet0 alias to rk3399-u-boot.dtsi
v2: Keep dfi node for all boot phases
v2: Collect r-b tag
---
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +++-
arch/arm/dts/rk3399-opp.dtsi | 6 +-
arch/arm/dts/rk3399-u-boot.dtsi | 55 +++---
arch/arm/dts/rk3399.dtsi | 289 +++++++++++++++++++++++++++----
4 files changed, 313 insertions(+), 68 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi
index 69cc9b05baa5..783120e9cebe 100644
--- a/arch/arm/dts/rk3399-op1-opp.dtsi
+++ b/arch/arm/dts/rk3399-op1-opp.dtsi
@@ -4,7 +4,7 @@
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -39,7 +39,7 @@
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -82,7 +82,7 @@
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
@@ -110,6 +110,27 @@
opp-microvolt = <1075000>;
};
};
+
+ dmc_opp_table: opp-table-3 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <928000000>;
+ opp-microvolt = <925000>;
+ };
+ };
};
&cpu_l0 {
@@ -136,6 +157,10 @@
operating-points-v2 = <&cluster1_opp>;
};
+&dmc {
+ operating-points-v2 = <&dmc_opp_table>;
+};
+
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi
index da41cd81ebb7..fee5e7111279 100644
--- a/arch/arm/dts/rk3399-opp.dtsi
+++ b/arch/arm/dts/rk3399-opp.dtsi
@@ -4,7 +4,7 @@
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -35,7 +35,7 @@
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -74,7 +74,7 @@
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 0357d6273b96..6af9621ac3d0 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -2,12 +2,11 @@
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
-#define USB_CLASS_HUB 9
-
#include "rockchip-u-boot.dtsi"
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
pci0 = &pcie0;
@@ -29,37 +28,6 @@
reg = <0x0 0xff620000 0x0 0x100>;
bootph-all;
};
-
- dfi: dfi@ff630000 {
- reg = <0x00 0xff630000 0x00 0x4000>;
- compatible = "rockchip,rk3399-dfi";
- rockchip,pmu = <&pmugrf>;
- clocks = <&cru PCLK_DDR_MON>;
- clock-names = "pclk_ddr_mon";
- bootph-all;
- };
-
- rng: rng@ff8b8000 {
- compatible = "rockchip,rk3399-crypto";
- reg = <0x0 0xff8b8000 0x0 0x1000>;
- };
-
- dmc: dmc {
- compatible = "rockchip,rk3399-dmc";
- reg = <0x0 0xffa80000 0x0 0x0800
- 0x0 0xffa80800 0x0 0x1800
- 0x0 0xffa82000 0x0 0x2000
- 0x0 0xffa84000 0x0 0x1000
- 0x0 0xffa88000 0x0 0x0800
- 0x0 0xffa88800 0x0 0x1800
- 0x0 0xffa8a000 0x0 0x2000
- 0x0 0xffa8c000 0x0 0x1000>;
- devfreq-events = <&dfi>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DDRC>;
- clock-names = "dmc_clk";
- bootph-all;
- };
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
@@ -91,6 +59,23 @@
bootph-all;
};
+&dfi {
+ bootph-all;
+};
+
+&dmc {
+ reg = <0x0 0xffa80000 0x0 0x0800
+ 0x0 0xffa80800 0x0 0x1800
+ 0x0 0xffa82000 0x0 0x2000
+ 0x0 0xffa84000 0x0 0x1000
+ 0x0 0xffa88000 0x0 0x0800
+ 0x0 0xffa88800 0x0 0x1800
+ 0x0 0xffa8a000 0x0 0x2000
+ 0x0 0xffa8c000 0x0 0x1000>;
+ bootph-all;
+ status = "okay";
+};
+
&emmc_phy {
bootph-pre-ram;
bootph-some-ram;
@@ -198,3 +183,7 @@
&vopl {
bootph-some-ram;
};
+
+&xin24m {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 3871c7fd83b0..6e12c5a920ca 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -19,7 +19,11 @@
#size-cells = <2>;
aliases {
- ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -124,6 +128,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+
+ thermal-idle {
+ #cooling-cells = <2>;
+ duration-us = <10000>;
+ exit-latency-us = <500>;
+ };
};
cpu_b1: cpu@101 {
@@ -136,6 +146,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+
+ thermal-idle {
+ #cooling-cells = <2>;
+ duration-us = <10000>;
+ exit-latency-us = <500>;
+ };
};
idle-states {
@@ -166,6 +182,15 @@
ports = <&vopl_out>, <&vopb_out>;
};
+ dmc: memory-controller {
+ compatible = "rockchip,rk3399-dmc";
+ rockchip,pmu = <&pmugrf>;
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRC>;
+ clock-names = "dmc_clk";
+ status = "disabled";
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -244,6 +269,33 @@
};
};
+ pcie0_ep: pcie-ep@f8000000 {
+ compatible = "rockchip,rk3399-pcie-ep";
+ reg = <0x0 0xfd000000 0x0 0x1000000>,
+ <0x0 0xfa000000 0x0 0x2000000>;
+ reg-names = "apb-base", "mem-base";
+ clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+ <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+ clock-names = "aclk", "aclk-perf",
+ "hclk", "pm";
+ max-functions = /bits/ 8 <8>;
+ num-lanes = <4>;
+ resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
+ <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
+ <&cru SRST_A_PCIE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+ "pm", "pclk", "aclk";
+ phys = <&pcie_phy 0>, <&pcie_phy 1>,
+ <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1",
+ "pcie-phy-2", "pcie-phy-3";
+ rockchip,max-outbound-regions = <32>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqnb_cpm>;
+ status = "disabled";
+ };
+
gmac: ethernet@fe300000 {
compatible = "rockchip,rk3399-gmac";
reg = <0x0 0xfe300000 0x0 0x10000>;
@@ -361,6 +413,54 @@
status = "disabled";
};
+ debug@fe430000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe430000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l0>;
+ };
+
+ debug@fe432000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe432000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l1>;
+ };
+
+ debug@fe434000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe434000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l2>;
+ };
+
+ debug@fe436000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe436000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l3>;
+ };
+
+ debug@fe610000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe610000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b0>;
+ };
+
+ debug@fe710000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe710000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b1>;
+ };
+
usbdrd3_0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
@@ -483,7 +583,7 @@
<0x0 0xfff10000 0 0x10000>, /* GICH */
<0x0 0xfff20000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
- its: interrupt-controller@fee20000 {
+ its: msi-controller@fee20000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
@@ -513,6 +613,26 @@
status = "disabled";
};
+ crypto0: crypto@ff8b0000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
+ reset-names = "master", "slave", "crypto-rst";
+ };
+
+ crypto1: crypto@ff8b8000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b8000 0x0 0x4000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
+ reset-names = "master", "slave", "crypto-rst";
+ };
+
i2c1: i2c@ff110000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff110000 0x0 0x1000>;
@@ -993,7 +1113,9 @@
power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
- <&cru HCLK_VDU>;
+ <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>,
+ <&cru SCLK_VDU_CORE>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
#power-domain-cells = <0>;
@@ -1235,6 +1357,15 @@
status = "disabled";
};
+ dfi: dfi@ff630000 {
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ compatible = "rockchip,rk3399-dfi";
+ rockchip,pmu = <&pmugrf>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ };
+
vpu: video-codec@ff650000 {
compatible = "rockchip,rk3399-vpu";
reg = <0x0 0xff650000 0x0 0x800>;
@@ -1251,7 +1382,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1260,7 +1390,7 @@
vdec: video-codec@ff660000 {
compatible = "rockchip,rk3399-vdec";
- reg = <0x0 0xff660000 0x0 0x400>;
+ reg = <0x0 0xff660000 0x0 0x480>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
@@ -1273,7 +1403,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VDU>;
@@ -1284,7 +1413,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1356,9 +1484,11 @@
clock-names = "apb_pclk";
};
- pmucru: pmu-clock-controller@ff750000 {
+ pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1369,6 +1499,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1382,7 +1514,8 @@
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
- <&cru PCLK_DDR>;
+ <&cru PCLK_DDR>,
+ <&cru ACLK_VDU>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1393,7 +1526,8 @@
<100000000>, <50000000>,
<400000000>, <400000000>,
<200000000>,
- <200000000>;
+ <200000000>,
+ <400000000>;
};
grf: syscon@ff770000 {
@@ -1477,6 +1611,7 @@
reg = <0xf780 0x24>;
clocks = <&sdhci>;
clock-names = "emmcclk";
+ drive-impedance-ohm = <50>;
#phy-cells = <0>;
status = "disabled";
};
@@ -1487,7 +1622,6 @@
clock-names = "refclk";
#phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
- drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
@@ -1582,8 +1716,9 @@
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
- pinctrl-names = "default";
+ pinctrl-names = "bclk_on", "bclk_off";
pinctrl-0 = <&i2s0_8ch_bus>;
+ pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#sound-dai-cells = <0>;
status = "disabled";
@@ -1619,7 +1754,7 @@
vopl: vop@ff8f0000 {
compatible = "rockchip,rk3399-vop-lit";
- reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
assigned-clock-rates = <400000000>, <100000000>;
@@ -1666,7 +1801,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
@@ -1676,7 +1810,7 @@
vopb: vop@ff900000 {
compatible = "rockchip,rk3399-vop-big";
- reg = <0x0 0xff900000 0x0 0x3efc>;
+ reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
assigned-clock-rates = <400000000>, <100000000>;
@@ -1723,7 +1857,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
@@ -1761,7 +1894,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1769,11 +1901,36 @@
rockchip,disable-mmu-reset;
};
+ isp1: isp1@ff920000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_ISP1>,
+ <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <&isp1_mmu>;
+ phys = <&mipi_dsi1>;
+ phy-names = "dphy";
+ power-domains = <&power RK3399_PD_ISP1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -1802,10 +1959,10 @@
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_SFR>,
- <&cru PLL_VPLL>,
+ <&cru SCLK_HDMI_CEC>,
<&cru PCLK_VIO_GRF>,
- <&cru SCLK_HDMI_CEC>;
- clock-names = "iahb", "isfr", "vpll", "grf", "cec";
+ <&cru PLL_VPLL>;
+ clock-names = "iahb", "isfr", "cec", "grf", "ref";
power-domains = <&power RK3399_PD_HDCP>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
@@ -1829,7 +1986,7 @@
};
};
- mipi_dsi: mipi@ff960000 {
+ mipi_dsi: dsi@ff960000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1857,15 +2014,20 @@
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
+
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+ mipi_out: port@1 {
+ reg = <1>;
+ };
};
};
- mipi_dsi1: mipi@ff968000 {
+ mipi_dsi1: dsi@ff968000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff968000 0x0 0x8000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1878,6 +2040,7 @@
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
ports {
@@ -1899,10 +2062,14 @@
remote-endpoint = <&vopl_out_mipi1>;
};
};
+
+ mipi1_out: port@1 {
+ reg = <1>;
+ };
};
};
- edp: edp@ff970000 {
+ edp: dp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1919,6 +2086,7 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
@@ -1934,6 +2102,10 @@
remote-endpoint = <&vopl_out_edp>;
};
};
+
+ edp_out: port@1 {
+ reg = <1>;
+ };
};
};
@@ -1946,6 +2118,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
#cooling-cells = <2>;
+ dynamic-power-coefficient = <2640>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
@@ -1958,7 +2131,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff720000 {
+ gpio0: gpio@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
@@ -1971,7 +2144,7 @@
#interrupt-cells = <0x2>;
};
- gpio1: gpio1@ff730000 {
+ gpio1: gpio@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
@@ -1984,7 +2157,7 @@
#interrupt-cells = <0x2>;
};
- gpio2: gpio2@ff780000 {
+ gpio2: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
@@ -1997,7 +2170,7 @@
#interrupt-cells = <0x2>;
};
- gpio3: gpio3@ff788000 {
+ gpio3: gpio@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
@@ -2010,7 +2183,7 @@
#interrupt-cells = <0x2>;
};
- gpio4: gpio4@ff790000 {
+ gpio4: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
@@ -2108,12 +2281,38 @@
output-low;
};
+ pcfg_input_enable: pcfg-input-enable {
+ input-enable;
+ };
+
+ pcfg_input_pull_up: pcfg-input-pull-up {
+ input-enable;
+ bias-pull-up;
+ };
+
+ pcfg_input_pull_down: pcfg-input-pull-down {
+ input-enable;
+ bias-pull-down;
+ };
+
clock {
clk_32k: clk-32k {
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
+ cif {
+ cif_clkin: cif-clkin {
+ rockchip,pins =
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ cif_clkouta: cif-clkouta {
+ rockchip,pins =
+ <2 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
edp {
edp_hpd: edp-hpd {
rockchip,pins =
@@ -2264,6 +2463,16 @@
<4 RK_PA0 1 &pcfg_pull_none>;
};
+ i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
+ rockchip,pins =
+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>,
@@ -2276,6 +2485,19 @@
<3 RK_PD7 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none>;
};
+
+ i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
+ rockchip,pins =
+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
};
i2s1 {
@@ -2287,6 +2509,15 @@
<4 RK_PA6 1 &pcfg_pull_none>,
<4 RK_PA7 1 &pcfg_pull_none>;
};
+
+ i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
+ rockchip,pins =
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
};
sdio0 {
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 06/22] rockchip: rk3399-gru: Sync DT from Linux kernel v6.8
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (4 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 05/22] rockchip: rk3399: Sync SoC DT from Linux kernel v6.8 Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 07/22] rockchip: rk3399-puma: " Jonas Karlman
` (15 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-gru related device tree from Linux kernel v6.8.
The spi_flash symbol is no longer part of upstream DT, it is re-defined
to allow existing reference use in related u-boot.dtsi-files.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
The spi_flash node should probably use bootph pre-ram/some-ram instead
of all to match other boards. I cannot test so it is kept as-is.
---
arch/arm/dts/rk3399-gru-bob.dts | 8 +-
arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++++++++++++++-
arch/arm/dts/rk3399-gru-kevin.dts | 3 +-
arch/arm/dts/rk3399-gru-u-boot.dtsi | 10 +-
arch/arm/dts/rk3399-gru.dtsi | 52 +++++-
5 files changed, 254 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts
index e6c1c94c8d69..1cba1d857c96 100644
--- a/arch/arm/dts/rk3399-gru-bob.dts
+++ b/arch/arm/dts/rk3399-gru-bob.dts
@@ -16,6 +16,7 @@
"google,bob-rev7", "google,bob-rev6",
"google,bob-rev5", "google,bob-rev4",
"google,bob", "google,gru", "rockchip,rk3399";
+ chassis-type = "convertible";
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51";
@@ -69,7 +70,7 @@
&spi0 {
status = "okay";
- cr50@0 {
+ tpm@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <&gpio0>;
@@ -87,3 +88,8 @@
};
};
};
+
+&wlan_host_wake_l {
+ /* Kevin has an external pull up, but Bob does not. */
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+};
diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi
index 1384dabbdf40..cacbad35cfc8 100644
--- a/arch/arm/dts/rk3399-gru-chromebook.dtsi
+++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi
@@ -198,7 +198,6 @@
power-supply = <&pp3300_disp>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
- pwm-delay-us = <10000>;
};
gpio_keys: gpio-keys {
@@ -206,7 +205,7 @@
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
- wake_on_bt: wake-on-bt {
+ wake_on_bt: key-wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -234,9 +233,24 @@
extcon = <&usbc_extcon0>, <&usbc_extcon1>;
};
+&dmc {
+ center-supply = <&ppvar_centerlogic>;
+ rockchip,pd-idle-dis-freq-hz = <800000000>;
+ rockchip,sr-idle-dis-freq-hz = <800000000>;
+ rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>;
+};
+
&edp {
status = "okay";
+ /*
+ * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only
+ * set this here, because rk3399-gru.dtsi ensures we can generate this
+ * off GPLL=600MHz, whereas some other RK3399 boards may not.
+ */
+ assigned-clocks = <&cru PCLK_EDP>;
+ assigned-clock-rates = <24000000>;
+
ports {
edp_out: port@1 {
reg = <1>;
@@ -251,6 +265,182 @@
};
};
+&gpio0 {
+ gpio-line-names = /* GPIO0 A 0-7 */
+ "AP_RTC_CLK_IN",
+ "EC_AP_INT_L",
+ "PP1800_AUDIO_EN",
+ "BT_HOST_WAKE_L",
+ "WLAN_MODULE_PD_L",
+ "H1_INT_OD_L",
+ "CENTERLOGIC_DVS_PWM",
+ "",
+
+ /* GPIO0 B 0-4 */
+ "WIFI_HOST_WAKE_L",
+ "PMUIO2_33_18_L",
+ "PP1500_EN",
+ "AP_EC_WARM_RESET_REQ",
+ "PP3000_EN";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A 0-7 */
+ "",
+ "",
+ "SPK_PA_EN",
+ "",
+ "TRACKPAD_INT_L",
+ "AP_EC_S3_S0_L",
+ "AP_EC_OVERTEMP",
+ "AP_SPI_FLASH_MISO",
+
+ /* GPIO1 B 0-7 */
+ "AP_SPI_FLASH_MOSI_R",
+ "AP_SPI_FLASH_CLK_R",
+ "AP_SPI_FLASH_CS_L_R",
+ "WLAN_MODULE_RESET_L",
+ "WIFI_DISABLE_L",
+ "MIC_INT",
+ "",
+ "AP_I2C_DVS_SDA",
+
+ /* GPIO1 C 0-7 */
+ "AP_I2C_DVS_SCL",
+ "AP_BL_EN",
+ /*
+ * AP_FLASH_WP is crossystem ABI. Schematics call it
+ * AP_FW_WP or CPU1_FW_WP, depending on the variant.
+ */
+ "AP_FLASH_WP",
+ "LITCPU_DVS_PWM",
+ "AP_I2C_AUDIO_SDA",
+ "AP_I2C_AUDIO_SCL",
+ "",
+ "HEADSET_INT_L";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A 0-7 */
+ "",
+ "",
+ "SD_IO_PWR_EN",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO2 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO2 C 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "AP_SPI_EC_MISO",
+ "AP_SPI_EC_MOSI",
+ "AP_SPI_EC_CLK",
+ "AP_SPI_EC_CS_L",
+
+ /* GPIO2 D 0-4 */
+ "BT_DEV_WAKE_L",
+ "",
+ "WIFI_PCIE_CLKREQ_L",
+ "WIFI_PERST_L",
+ "SD_PWR_3000_1800_L";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "AP_SPI_TPM_MISO",
+ "AP_SPI_TPM_MOSI_R",
+ "AP_SPI_TPM_CLK_R",
+ "AP_SPI_TPM_CS_L_R",
+
+ /* GPIO3 B 0-7 */
+ "EC_IN_RW",
+ "",
+ "AP_I2C_TP_SDA",
+ "AP_I2C_TP_SCL",
+ "AP_I2C_TP_PU_EN",
+ "TOUCH_INT_L",
+ "",
+ "",
+
+ /* GPIO3 C 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO3 D 0-7 */
+ "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI_0",
+ "I2S0_SDI_1",
+ "",
+ "I2S0_SDO_1",
+ "I2S0_SDO_0";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A 0-7 */
+ "I2S_MCLK",
+ "AP_I2C_MIC_SDA",
+ "AP_I2C_MIC_SCL",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 C 0-7 */
+ "AP_I2C_TS_SDA",
+ "AP_I2C_TS_SCL",
+ "GPU_DVS_PWM",
+ "UART_DBG_TX_AP_RX",
+ "UART_AP_TX_DBG_RX",
+ "",
+ "BIGCPU_DVS_PWM",
+ "EDP_HPD_3V0",
+
+ /* GPIO4 D 0-5 */
+ "SD_CARD_DET_L",
+ "USB_DP_HPD",
+ "TOUCH_RESET_L",
+ "PP3300_DISP_EN",
+ "",
+ "SD_SLOT_PWR_EN";
+};
+
ap_i2c_mic: &i2c1 {
status = "okay";
@@ -286,7 +476,7 @@ ap_i2c_tp: &i2c5 {
};
&cros_ec {
- cros_ec_pwm: ec-pwm {
+ cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};
@@ -319,8 +509,7 @@ ap_i2c_tp: &i2c5 {
&pci_rootport {
mvl_wifi: wifi@0,0 {
compatible = "pci1b4b,2b42";
- reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
- 0x83010000 0x0 0x00100000 0x0 0x00100000>;
+ reg = <0x0000 0x0 0x0 0x0 0x0>;
interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -395,6 +584,7 @@ ap_i2c_tp: &i2c5 {
};
wlan_host_wake_l: wlan-host-wake-l {
+ /* Kevin has an external pull up, but Bob does not */
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts
index 2bbef9fcbe27..2cc9b3386c16 100644
--- a/arch/arm/dts/rk3399-gru-kevin.dts
+++ b/arch/arm/dts/rk3399-gru-kevin.dts
@@ -24,6 +24,7 @@
"google,kevin-rev9", "google,kevin-rev8",
"google,kevin-rev7", "google,kevin-rev6",
"google,kevin", "google,gru", "rockchip,rk3399";
+ chassis-type = "convertible";
/* Power tree */
@@ -91,7 +92,7 @@
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
- pen-insert {
+ switch-pen-insert {
label = "Pen Insert";
/* Insert = low, eject = high */
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi
index 0cc40eb6d6f6..6bdc892bd913 100644
--- a/arch/arm/dts/rk3399-gru-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -78,12 +78,14 @@
/delete-property/ bootph-pre-ram;
};
+&spi1 {
+ spi_flash: flash@0 {
+ bootph-all;
+ };
+};
+
&spi5 {
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
};
-
-&spi_flash {
- bootph-all;
-};
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi
index b80f19066b57..d90fe4d40d48 100644
--- a/arch/arm/dts/rk3399-gru.dtsi
+++ b/arch/arm/dts/rk3399-gru.dtsi
@@ -250,7 +250,7 @@
pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
enable-active-high;
- enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1>,
<3000000 0x0>;
@@ -286,7 +286,7 @@
sound: sound {
compatible = "rockchip,rk3399-gru-sound";
- rockchip,cpu = <&i2s0 &i2s2>;
+ rockchip,cpu = <&i2s0 &spdif>;
};
};
@@ -373,6 +373,34 @@
<200000000>;
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+
+ rockchip,pd-idle-ns = <160>;
+ rockchip,sr-idle-ns = <10240>;
+ rockchip,sr-mc-gate-idle-ns = <40960>;
+ rockchip,srpd-lite-idle-ns = <61440>;
+ rockchip,standby-idle-ns = <81920>;
+
+ rockchip,ddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr4_odt_dis_freq = <666000000>;
+
+ rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
+ rockchip,srpd-lite-idle-dis-freq-hz = <0>;
+ rockchip,standby-idle-dis-freq-hz = <928000000>;
+};
+
+&dmc_opp_table {
+ opp03 {
+ opp-suspend;
+ };
+};
+
&emmc_phy {
status = "okay";
};
@@ -437,10 +465,6 @@ ap_i2c_audio: &i2c8 {
status = "okay";
};
-&i2s2 {
- status = "okay";
-};
-
&io_domains {
status = "okay";
@@ -461,10 +485,11 @@ ap_i2c_audio: &i2c8 {
vpcie0v9-supply = <&pp900_pcie>;
pci_rootport: pcie@0,0 {
- reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
+ reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
+ device_type = "pci";
};
};
@@ -537,13 +562,24 @@ ap_i2c_audio: &i2c8 {
vqmmc-supply = <&ppvar_sd_card_io>;
};
+&spdif {
+ status = "okay";
+
+ /*
+ * SPDIF is routed internally to DP; we either don't use these pins, or
+ * mux them to something else.
+ */
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+};
+
&spi1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
- spi_flash: spiflash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 07/22] rockchip: rk3399-puma: Sync DT from Linux kernel v6.8
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (5 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 06/22] rockchip: rk3399-gru: Sync " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 08/22] rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig Jonas Karlman
` (14 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Quentin Schulz, Klaus Goger
Cc: Dragan Simic, Christopher Obbard, Peter Robinson, u-boot,
Jonas Karlman
Sync rk3399-puma related device tree from Linux kernel v6.8.
The vdd_log node is already part of rk3399-puma.dtsi, only keep the
regulator-init-microvolt prop in u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: The SPL_PAD_TO defconfig change was moved to own patch in part1
v2: Collect r-b tags
---
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 16 ++------
arch/arm/dts/rk3399-puma-haikou.dts | 42 ++++++++++++++++++---
arch/arm/dts/rk3399-puma.dtsi | 17 ++++++++-
3 files changed, 56 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index 1930e5e10353..5a9bd320ec46 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -30,18 +30,6 @@
aliases {
spi5 = &spi5;
};
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-init-microvolt = <950000>;
- vin-supply = <&vcc5v0_sys>;
- };
};
&binman {
@@ -111,3 +99,7 @@
bootph-pre-sram;
bootph-pre-ram;
};
+
+&vdd_log {
+ regulator-init-microvolt = <950000>;
+};
diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts
index 115c14c0a3c6..18a98c4648ea 100644
--- a/arch/arm/dts/rk3399-puma-haikou.dts
+++ b/arch/arm/dts/rk3399-puma-haikou.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
@@ -18,6 +19,38 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&haikou_keys_pin>;
+ pinctrl-names = "default";
+
+ button-batlow-n {
+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "BATLOW#";
+ linux,code = <KEY_BATTERY>;
+ };
+
+ button-slp-btn-n {
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "SLP_BTN#";
+ linux,code = <KEY_SLEEP>;
+ };
+
+ button-wake-n {
+ gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
+ label = "WAKE#";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+
+ switch-lid-btn-n {
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "LID_BTN#";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ };
+ };
+
leds {
pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
@@ -165,11 +198,8 @@
};
&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&haikou_pin_hog>;
-
- hog {
- haikou_pin_hog: haikou-pin-hog {
+ buttons {
+ haikou_keys_pin: haikou-keys-pin {
rockchip,pins =
/* LID_BTN */
<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
@@ -177,7 +207,7 @@
<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
/* SLP_BTN# */
<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BIOS_DISABLE# */
+ /* WAKE# */
<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index aa3e21bd6c8f..c08e69391c01 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -9,6 +9,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
};
@@ -27,7 +28,7 @@
extcon_usb3: extcon-usb3 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_id>;
};
@@ -119,6 +120,20 @@
drive-impedance-ohm = <33>;
};
+&gpio0 {
+ /*
+ * The BIOS_DISABLE hog is a feedback pin for the actual status of the
+ * signal. This usually represents the state of a switch on the baseboard.
+ * The pin has a 10k pull-up resistor connected, so no pull-up setting is needed.
+ */
+ bios-disable-hog {
+ gpios = <RK_PB0 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ line-name = "bios_disable";
+ };
+};
+
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 08/22] rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (6 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 07/22] rockchip: rk3399-puma: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 09/22] rockchip: rk3399-eaidk-610: " Jonas Karlman
` (13 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jagan Teki
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-rock-pi-n10 related device tree from Linux kernel v6.8.
Remove SPL_GPIO=y, board does not use gpio in SPL.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
---
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++++++++++++++++++
arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 ++++++--
.../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++++++++
configs/rock-pi-n10-rk3399pro_defconfig | 8 ++--
4 files changed, 89 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi
index 717cb3dc816e..793951655b73 100644
--- a/arch/arm/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3288-vmarc-som.dtsi
@@ -231,11 +231,43 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ };
+};
+
&i2c5 {
status = "okay";
};
+&io_domains {
+ bb-supply = <&vcc_io>;
+ flash0-supply = <&vccio_flash>;
+ gpio1830-supply = <&vcc_18>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_wl>;
+ status = "okay";
+};
+
&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
};
@@ -251,6 +283,12 @@
};
};
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
@@ -282,6 +320,16 @@
};
};
+&sdio_pwrseq {
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */
+};
+
&usbphy {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
index e1cb426f2aa5..8823c924dc1d 100644
--- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi
@@ -13,8 +13,9 @@
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
+ ethernet0 = &gmac;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
};
vcc3v3_pcie: vcc-pcie-regulator {
@@ -297,11 +298,10 @@
clock-frequency = <400000>;
status = "okay";
- hym8563: hym8563@51 {
+ hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
@@ -347,7 +347,7 @@
pcie {
pcie_pwr: pcie-pwr {
- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -381,6 +381,16 @@
pmu1830-supply = <&vcc_1v8>;
};
+&sdio_pwrseq {
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+};
+
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
index 26b53eac4706..da1d548b7330 100644
--- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -15,6 +15,14 @@
#clock-cells = <0>;
};
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -78,6 +86,19 @@
status = "okay";
};
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index 234d0c9ab0f5..6d93b9e58003 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10"
@@ -18,7 +17,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -36,17 +35,20 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 09/22] rockchip: rk3399-eaidk-610: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (7 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 08/22] rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 10/22] rockchip: rk3399-leez: " Jonas Karlman
` (12 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Andy Yan
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-eaidk-610 device tree from Linux kernel v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
---
arch/arm/dts/rk3399-eaidk-610.dts | 3 ++-
configs/eaidk-610-rk3399_defconfig | 11 ++++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-eaidk-610.dts b/arch/arm/dts/rk3399-eaidk-610.dts
index d1f343345f67..173da81fc231 100644
--- a/arch/arm/dts/rk3399-eaidk-610.dts
+++ b/arch/arm/dts/rk3399-eaidk-610.dts
@@ -15,6 +15,7 @@
compatible = "openailab,eaidk-610", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -773,7 +774,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig
index eba6f90c605b..d9cde9ecced5 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,14 +31,19 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
@@ -50,5 +56,4 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 10/22] rockchip: rk3399-leez: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (8 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 09/22] rockchip: rk3399-eaidk-610: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 11/22] rockchip: rk3399-evb: " Jonas Karlman
` (11 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Andy Yan
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-leez-p710 device tree from Linux kernel v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
---
arch/arm/dts/rk3399-leez-p710.dts | 8 +++++---
configs/leez-rk3399_defconfig | 10 ++++++++--
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts
index 7c93f840bc64..cb69e2145fa9 100644
--- a/arch/arm/dts/rk3399-leez-p710.dts
+++ b/arch/arm/dts/rk3399-leez-p710.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -14,6 +15,7 @@
compatible = "leez,p710", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -55,7 +57,7 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- vim-supply = <&vcc3v3_sys>;
+ vin-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@@ -102,12 +104,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc5v0_sys>;
};
};
@@ -509,7 +511,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 13453e523444..903125aa5c1d 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,12 +31,18 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -57,5 +64,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 11/22] rockchip: rk3399-evb: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (9 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 10/22] rockchip: rk3399-leez: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 12/22] rockchip: rk3399-firefly: " Jonas Karlman
` (10 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-evb device tree from Linux kernel v6.8.
Drop bootph prop for i2c0 and rk808 node, PMIC support is not included
in TPL/SPL and PMIC regulators are working fine in U-Boot proper.
Change to use sdmmc_cd pinconf and drop cd-gpios for card detect pin.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Update commit message
v2: Collect r-b tag
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 11 +----------
arch/arm/dts/rk3399-evb.dts | 3 ++-
configs/evb-rk3399_defconfig | 6 +++---
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index 6dedfeec0722..3fa5fc0c9ddb 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -12,23 +12,14 @@
};
};
-&i2c0 {
- bootph-all;
-};
-
-&rk808 {
- bootph-all;
-};
-
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 7b717ebec8ff..55eca7a50a1f 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -12,6 +12,7 @@
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
};
@@ -55,7 +56,7 @@
};
edp_panel: edp-panel {
- compatible ="lg,lp079qx1-sp0v";
+ compatible = "lg,lp079qx1-sp0v";
backlight = <&backlight>;
enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
power-supply = <&vcc3v3_s0>;
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index afb79987464f..334259f73eb2 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -15,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -30,7 +30,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_HS400_SUPPORT=y
@@ -39,6 +38,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -69,5 +70,4 @@ CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 12/22] rockchip: rk3399-firefly: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (10 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 11/22] rockchip: rk3399-evb: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 13/22] rockchip: rk3399-orangepi: " Jonas Karlman
` (9 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-firefly device tree from Linux kernel v6.8.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Drop enable of AHCI/SCSI support
v2: Collect r-b tag
---
arch/arm/dts/rk3399-firefly.dts | 17 ++++++++++++-----
configs/firefly-rk3399_defconfig | 9 +++++++--
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index c4dd2a6b4836..260415d99aeb 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
@@ -15,6 +16,7 @@
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -86,7 +88,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -245,12 +247,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc_sys>;
};
};
@@ -298,6 +300,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
@@ -770,8 +777,8 @@
sd-uhs-sdr104;
/* Power supply */
- vqmmc-supply = &vcc1v8_s3; /* IO line */
- vmmc-supply = &vcc_sdio; /* card's power */
+ vqmmc-supply = <&vcc1v8_s3>; /* IO line */
+ vmmc-supply = <&vcc_sdio>; /* card's power */
#address-cells = <1>;
#size-cells = <0>;
@@ -781,7 +788,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index db98926b627a..9c94ac2f3012 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -34,13 +34,19 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -61,5 +67,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 13/22] rockchip: rk3399-orangepi: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (11 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 12/22] rockchip: rk3399-firefly: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 14/22] rockchip: rk3399-roc-pc: " Jonas Karlman
` (8 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jagan Teki
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-orangepi device tree from Linux kernel v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tag
---
arch/arm/dts/rk3399-orangepi.dts | 12 +++++++-----
configs/orangepi-rk3399_defconfig | 10 ++++++++--
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts
index 04b54abea3cc..e7551449e718 100644
--- a/arch/arm/dts/rk3399-orangepi.dts
+++ b/arch/arm/dts/rk3399-orangepi.dts
@@ -7,6 +7,7 @@
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/input/input.h"
+#include <dt-bindings/interrupt-controller/irq.h>
#include "dt-bindings/usb/pd.h"
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -16,6 +17,7 @@
compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -51,13 +53,13 @@
press-threshold-microvolt = <300000>;
};
- back {
+ button-back {
label = "Back";
linux,code = <KEY_BACK>;
press-threshold-microvolt = <985000>;
};
- menu {
+ button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <1314000>;
@@ -77,7 +79,7 @@
compatible = "gpio-keys";
autorepeat;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
@@ -166,12 +168,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc_sys>;
};
};
@@ -735,7 +737,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 703732ad15f0..2d0c9b77e584 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -31,12 +32,18 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
@@ -58,5 +65,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 14/22] rockchip: rk3399-roc-pc: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (12 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 13/22] rockchip: rk3399-orangepi: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 15/22] rockchip: rk3399-nanopi-4: " Jonas Karlman
` (7 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Levin Du,
Suniel Mahesh
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-roc-pc related device tree from Linux kernel v6.8.
Add SF_DEFAULT_SPEED=30000000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Drop enable of AHCI/SCSI support
v2: Collect r-b tag
---
arch/arm/dts/rk3399-roc-pc.dtsi | 15 ++++++++-------
configs/roc-pc-mezzanine-rk3399_defconfig | 7 ++++++-
configs/roc-pc-rk3399_defconfig | 7 +++++--
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi
index d1aaf8e83391..ca7a446b6568 100644
--- a/arch/arm/dts/rk3399-roc-pc.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc.dtsi
@@ -14,6 +14,7 @@
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdhci;
};
@@ -41,7 +42,7 @@
keyup-threshold-microvolt = <1500000>;
poll-interval = <100>;
- recovery {
+ button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
@@ -54,7 +55,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_l>;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -271,6 +272,8 @@
};
&hdmi {
+ avdd-0v9-supply = <&vcca0v9_hdmi>;
+ avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
@@ -310,8 +313,6 @@
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
- vcc13-supply = <&vcc3v3_sys>;
- vcc14-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_3v0>;
regulators {
@@ -371,8 +372,8 @@
};
};
- vcc1v8_hdmi: LDO_REG2 {
- regulator-name = "vcc1v8_hdmi";
+ vcca1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcca1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -735,7 +736,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <30000000>;
};
};
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index e13356faabbc..8141f803cf3b 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -43,12 +44,17 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -84,5 +90,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index dee342898d1f..b8adf430e9ea 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
@@ -43,12 +42,17 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -85,5 +89,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 15/22] rockchip: rk3399-nanopi-4: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (13 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 14/22] rockchip: rk3399-roc-pc: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 16/22] rockchip: rk3399-rock960: " Jonas Karlman
` (6 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jagan Teki,
Deepak Das, Alexandre Vicenzi, Xiaobo Tian
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-nanopi-4 related device tree from Linux kernel v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support M4 SATA HAT.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, boards does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Only enable AHCI/SCSI on M4 variant
v2: Skip enable of PCI on NEO4 variant
v2: Keep SDHCI enabled on R4S variant
v2: Collect r-b tag
---
arch/arm/dts/rk3399-nanopc-t4.dts | 2 +-
arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +------------------------
arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +-
arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +-
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 4 ++
arch/arm/dts/rk3399-nanopi4.dtsi | 7 ++--
configs/nanopc-t4-rk3399_defconfig | 10 +++--
configs/nanopi-m4-2gb-rk3399_defconfig | 18 ++++++--
configs/nanopi-m4-rk3399_defconfig | 18 ++++++--
configs/nanopi-m4b-rk3399_defconfig | 18 ++++++--
configs/nanopi-neo4-rk3399_defconfig | 11 +++--
configs/nanopi-r4s-rk3399_defconfig | 11 +++--
12 files changed, 81 insertions(+), 79 deletions(-)
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts
index 452728b82e42..3bf8f959e42c 100644
--- a/arch/arm/dts/rk3399-nanopc-t4.dts
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -39,7 +39,7 @@
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
- recovery {
+ button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
index 60358ab8c7df..e9cf71f224a3 100644
--- a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
+++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
@@ -10,57 +10,4 @@
*/
/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi M4";
- compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_core: vcc5v0-core {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_core";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_5v>;
- };
-
- vcc5v0_usb1: vcc5v0-usb1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb1";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb2: vcc5v0-usb2 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb2";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_usb2>;
-};
-
-&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
-};
+#include "rk3399-nanopi-m4.dts"
diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts b/arch/arm/dts/rk3399-nanopi-m4b.dts
index 72182c58cc46..65cb21837b0c 100644
--- a/arch/arm/dts/rk3399-nanopi-m4b.dts
+++ b/arch/arm/dts/rk3399-nanopi-m4b.dts
@@ -19,7 +19,7 @@
keyup-threshold-microvolt = <1500000>;
poll-interval = <100>;
- recovery {
+ button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts
index cef4d18b599d..fe5b52610010 100644
--- a/arch/arm/dts/rk3399-nanopi-r4s.dts
+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts
@@ -46,9 +46,9 @@
gpio-keys {
pinctrl-0 = <&reset_button_pin>;
- /delete-node/ power;
+ /delete-node/ key-power;
- reset {
+ key-reset {
debounce-interval = <50>;
gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
label = "reset";
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index e0d7a518dfc2..757361249968 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -20,3 +20,7 @@
&vcc3v0_sd {
bootph-pre-ram;
};
+
+&vcc_sdio {
+ regulator-init-microvolt = <3000000>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
index 8c0ff6c96e03..b7f1e47978a6 100644
--- a/arch/arm/dts/rk3399-nanopi4.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -18,6 +18,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -111,7 +112,7 @@
pinctrl-names = "default";
pinctrl-0 = <&power_key>;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -167,6 +168,7 @@
};
&emmc_phy {
+ rockchip,enable-strobe-pulldown;
status = "okay";
};
@@ -267,7 +269,7 @@
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
+ pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>;
rockchip,system-power-controller;
wakeup-source;
@@ -374,7 +376,6 @@
vcc_sdio: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
- regulator-init-microvolt = <3000000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio";
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 89c36e273a9b..3e89f3dcabd0 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -34,15 +34,20 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
@@ -68,5 +73,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig
index eb1d2c1f51fc..10bd9fba5388 100644
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig
@@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -22,6 +25,7 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -63,5 +76,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index bc0b90b3d861..f5305549716c 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -22,6 +25,7 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -63,5 +76,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig
index 678f4d9d823f..70de7e0a6d7f 100644
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig
@@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -22,6 +25,7 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -63,5 +76,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index d9b7a90e8402..7f936636d419 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -31,14 +32,19 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
@@ -63,5 +69,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index 1fcccf2bae6e..ef74628fb284 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -31,14 +32,19 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
@@ -66,5 +72,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 16/22] rockchip: rk3399-rock960: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (14 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 15/22] rockchip: rk3399-nanopi-4: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 17/22] rockchip: rk3399-khadas: " Jonas Karlman
` (5 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Manivannan Sadhasivam
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-rock960 related device tree from Linux kernel v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use
pwm-regulator or regulator-gpio compatible.
Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support
RockUSB and UMS gadget.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Drop enable of AHCI/SCSI support on ROCK960
v2: Collect r-b tag
---
arch/arm/dts/rk3399-ficus.dts | 4 ++++
arch/arm/dts/rk3399-rock960.dtsi | 5 ++++-
configs/ficus-rk3399_defconfig | 22 +++++++++++++++++-----
configs/rock960-rk3399_defconfig | 10 +++++++---
4 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
index 1ce85a5816e4..30e4879f322c 100644
--- a/arch/arm/dts/rk3399-ficus.dts
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -13,6 +13,10 @@
model = "96boards RK3399 Ficus";
compatible = "vamrs,ficus", "rockchip,rk3399";
+ aliases {
+ ethernet0 = &gmac;
+ };
+
chosen {
stdout-path = "serial2:1500000n8";
};
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi
index 25dc61c26a94..c920ddf44baf 100644
--- a/arch/arm/dts/rk3399-rock960.dtsi
+++ b/arch/arm/dts/rk3399-rock960.dtsi
@@ -7,6 +7,7 @@
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
@@ -127,6 +128,8 @@
};
&hdmi {
+ avdd-0v9-supply = <&vcca0v9_hdmi>;
+ avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
@@ -528,7 +531,7 @@
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index f4e3ebba8f46..0d97b7ecb3c7 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCK960_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -21,6 +24,7 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 3b5ab7dc5781..3ea872a2ca3e 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -12,11 +12,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_SYS_PBSIZE=1052
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -28,6 +27,8 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SF is not set
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
@@ -37,6 +38,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
@@ -71,9 +73,11 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 17/22] rockchip: rk3399-khadas: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (15 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 16/22] rockchip: rk3399-rock960: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 18/22] rockchip: rk3399-rock-pi-4: " Jonas Karlman
` (4 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Nick Xie
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Sync rk3399-khadas related device tree from Linux kernel v6.8.
Add SPI flash related options to support booting from SPI flash.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support
RockUSB and UMS gadget.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Drop enable of AHCI/SCSI support
v2: Collect r-b tag
---
arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 +++
arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 5 ++++
arch/arm/dts/rk3399-khadas-edge-v.dts | 4 +++
arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +++----
configs/khadas-edge-captain-rk3399_defconfig | 29 ++++++++++++++++++--
configs/khadas-edge-rk3399_defconfig | 27 ++++++++++++++----
configs/khadas-edge-v-rk3399_defconfig | 29 ++++++++++++++++++--
7 files changed, 92 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts
index 8302e51def52..99ac4ed0f13f 100644
--- a/arch/arm/dts/rk3399-khadas-edge-captain.dts
+++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts
@@ -10,6 +10,10 @@
/ {
model = "Khadas Edge-Captain";
compatible = "khadas,edge-captain", "rockchip,rk3399";
+
+ aliases {
+ ethernet0 = &gmac;
+ };
};
&gmac {
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
index 4a3b23e48313..dd7a84d2b4a8 100644
--- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
@@ -6,6 +6,11 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+&spiflash {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&vdd_log {
regulator-init-microvolt = <950000>;
};
diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts
index f5dcb99dc349..e12e7b4d64ca 100644
--- a/arch/arm/dts/rk3399-khadas-edge-v.dts
+++ b/arch/arm/dts/rk3399-khadas-edge-v.dts
@@ -10,6 +10,10 @@
/ {
model = "Khadas Edge-V";
compatible = "khadas,edge-v", "rockchip,rk3399";
+
+ aliases {
+ ethernet0 = &gmac;
+ };
};
&gmac {
diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi
index d5c7648c841d..9d9297bc5f04 100644
--- a/arch/arm/dts/rk3399-khadas-edge.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -80,12 +81,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vsys_3v3>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
- vin-supply = <&vsys_3v3>;
};
vsys: vsys {
@@ -122,7 +123,7 @@
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
- recovery {
+ button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
@@ -135,7 +136,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -682,7 +683,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
@@ -705,7 +706,6 @@
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index 230b9d796442..67086d9f2fc2 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -3,43 +3,63 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -48,6 +68,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -63,5 +84,7 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 9f13cbf58398..f752731dec01 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -3,20 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
@@ -24,21 +31,28 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -47,6 +61,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -62,5 +77,7 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index abc4f2054cfd..cb05a47f812b 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -3,43 +3,63 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -48,6 +68,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -63,5 +84,7 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 18/22] rockchip: rk3399-rock-pi-4: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (16 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 17/22] rockchip: rk3399-khadas: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 19/22] rockchip: rk3399-rockpro64: " Jonas Karlman
` (3 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, FUKAUMI Naoki,
Jonas Karlman, Christopher Obbard, Jagan Teki
Cc: Quentin Schulz, Dragan Simic, Peter Robinson, u-boot
Sync rk3399-rock-pi-4 related device tree from Linux kernel v6.8.
Add SPI flash related nodes and options to support boot from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support SATA HAT.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tags
---
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++
arch/arm/dts/rk3399-rock-4c-plus.dts | 1 +
arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++
arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++-
arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++
arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++
configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++-----
configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++--
configs/rock-pi-4-rk3399_defconfig | 8 +++++++
configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++--
10 files changed, 114 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 44dab14dc211..5ec15a845c1a 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -13,3 +13,15 @@
bootph-pre-ram;
bootph-some-ram;
};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts
index 8bfd5f88d1ef..7baf9d1b22fd 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus.dts
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -15,6 +15,7 @@
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
index 85ee5770add0..f9ad518d3adb 100644
--- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
@@ -4,3 +4,15 @@
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index b1b7f4ffb1d4..281a12180703 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
@@ -44,7 +45,7 @@
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
- clock-names = "ext_clock";
+ clock-names = "lpo";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
@@ -492,6 +493,7 @@
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
+ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
index 85ee5770add0..38385621deb1 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
@@ -4,3 +4,10 @@
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&spi1 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts
index d32efab74e94..de2ebe4cb4f3 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4c.dts
@@ -43,6 +43,16 @@
hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
};
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
&uart0 {
status = "okay";
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig
index 2024defb2bf0..e97fde17acc2 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -26,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -40,23 +44,32 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -77,7 +90,6 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig
index 9b2303fdf792..13f5f84b9836 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -36,14 +43,25 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -54,9 +72,11 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -77,7 +97,6 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index e5a2bba8e7ff..d474d91053c1 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -17,6 +17,7 @@ CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -43,6 +44,8 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -54,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -66,6 +73,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index 4a9d1c531c10..50c6755246f2 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -37,13 +44,25 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -54,9 +73,11 @@ CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -77,7 +98,6 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 19/22] rockchip: rk3399-rockpro64: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (17 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 18/22] rockchip: rk3399-rock-pi-4: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 20/22] rockchip: rk3399-pinebook-pro: " Jonas Karlman
` (2 subsequent siblings)
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jagan Teki,
Jonas Karlman
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot
Sync rk3399-rockpro64 device tree from Linux kernel v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tags
---
arch/arm/dts/rk3399-rockpro64.dtsi | 98 ++++++++++++++++++++++++++++--
configs/rockpro64-rk3399_defconfig | 7 ++-
2 files changed, 97 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi
index 6bff8db7d33e..f30b82a10ca3 100644
--- a/arch/arm/dts/rk3399-rockpro64.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64.dtsi
@@ -11,6 +11,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
@@ -20,6 +21,15 @@
stdout-path = "serial2:1500000n8";
};
+ /* enable for panel backlight support */
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <5>;
+ pwms = <&pwm0 0 1000000 0>;
+ status = "disabled";
+ };
+
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -33,7 +43,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
@@ -69,6 +79,7 @@
fan: pwm-fan {
compatible = "pwm-fan";
+ cooling-levels = <0 100 150 200 255>;
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
@@ -106,6 +117,14 @@
};
};
+ avdd: avdd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd";
+ regulator-min-microvolt = <11000000>;
+ regulator-max-microvolt = <11000000>;
+ vin-supply = <&vcc3v3_s0>;
+ };
+
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -212,12 +231,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1700000>;
- vin-supply = <&vcc5v0_sys>;
};
};
@@ -245,6 +264,34 @@
cpu-supply = <&vdd_cpu_b>;
};
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&emmc_phy {
status = "okay";
};
@@ -371,8 +418,6 @@
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
@@ -461,8 +506,6 @@
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -536,6 +579,19 @@
vbus-supply = <&vcc5v0_typec>;
status = "okay";
};
+
+ /* enable for pine64 touch screen support */
+ touch: touchscreen@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;
+ AVDD28-supply = <&vcc3v0_touch>;
+ VDDIO-supply = <&vcc3v0_touch>;
+ irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
};
&i2s0 {
@@ -571,6 +627,36 @@
gpio1830-supply = <&vcc_3v0>;
};
+/* enable for pine64 panel display support */
+&mipi_dsi {
+ clock-master;
+ status = "disabled";
+
+ ports {
+ mipi_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ mipi_panel: panel@0 {
+ compatible = "feiyang,fy07024di26a30d";
+ reg = <0>;
+ avdd-supply = <&avdd>;
+ backlight = <&backlight>;
+ dvdd-supply = <&vcc3v3_s0>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 173f8f75020d..4e1af37a1559 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
@@ -20,7 +21,6 @@ CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
@@ -34,6 +34,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -57,7 +58,10 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -96,5 +100,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 20/22] rockchip: rk3399-pinebook-pro: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (18 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 19/22] rockchip: rk3399-rockpro64: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 21/22] rockchip: rk3399-pinephone-pro: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Peter Robinson, Jonas Karlman
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, u-boot
Sync rk3399-pinebook-pro device tree from Linux kernel v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tags
---
arch/arm/dts/rk3399-pinebook-pro.dts | 24 +++++++-----------------
configs/pinebook-pro-rk3399_defconfig | 6 ++++--
2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts
index d6b68d77d63a..054c6a4d1a45 100644
--- a/arch/arm/dts/rk3399-pinebook-pro.dts
+++ b/arch/arm/dts/rk3399-pinebook-pro.dts
@@ -50,19 +50,9 @@
pinctrl-0 = <&panel_en_pin>;
power-supply = <&vcc3v3_panel>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- panel_in_edp: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&edp_out_panel>;
- };
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
};
};
};
@@ -76,7 +66,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lidbtn_pin>;
- lid {
+ switch-lid {
debounce-interval = <20>;
gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
label = "Lid";
@@ -92,7 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn_pin>;
- power {
+ key-power {
debounce-interval = <20>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "Power";
@@ -675,7 +665,7 @@
i2c-scl-rising-time-ns = <168>;
status = "okay";
- es8316: es8316@11 {
+ es8316: audio-codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
@@ -943,7 +933,7 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- sd-uhs-sdr104;
+ sd-uhs-sdr50;
vmmc-supply = <&vcc3v0_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index dd8bc2b72cc3..8ac6ddd49dea 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
@@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -98,5 +101,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 21/22] rockchip: rk3399-pinephone-pro: Sync DT from v6.8 and update defconfig
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (19 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 20/22] rockchip: rk3399-pinebook-pro: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
21 siblings, 0 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Peter Robinson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, u-boot,
Jonas Karlman
Sync rk3399-pinephone-pro device tree from Linux kernel v6.8.
Add SPI flash related node and options to support boot from SPI flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for serial console.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
v2: Collect r-b tags
---
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 12 ++
arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++++++++++++++++++
configs/pinephone-pro-rk3399_defconfig | 8 +-
3 files changed, 163 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index dcfcec4f3072..037cec10ce36 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -13,3 +13,15 @@
&sdmmc {
max-frequency = <20000000>;
};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
+};
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
index 04403a76238b..61f3fec5a8b1 100644
--- a/arch/arm/dts/rk3399-pinephone-pro.dts
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -10,6 +10,7 @@
*/
/dts-v1/;
+#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -29,6 +30,31 @@
stdout-path = "serial2:115200n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1600000>;
+ poll-interval = <100>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <100000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <600000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 50000 0>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -102,6 +128,37 @@
/* WL_REG_ON on module */
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+
+ /* MIPI DSI panel 1.8v supply */
+ vcc1v8_lcd: vcc1v8-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ };
+
+ /* MIPI DSI panel 2.8v supply */
+ vcc2v8_lcd: vcc2v8-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc2v8_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&vcc3v3_sys>;
+ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ };
+};
+
+&cpu_alert0 {
+ temperature = <65000>;
+};
+&cpu_alert1 {
+ temperature = <68000>;
};
&cpu_l0 {
@@ -132,6 +189,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
@@ -326,6 +388,25 @@
};
};
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+
+ touchscreen@14 {
+ compatible = "goodix,gt1158";
+ reg = <0x14>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>;
+ irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
+ AVDD28-supply = <&vcc3v0_touch>;
+ VDDIO-supply = <&vcc3v0_touch>;
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1440>;
+ };
+};
+
&cluster0_opp {
opp04 {
status = "disabled";
@@ -355,6 +436,39 @@
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+ clock-master;
+
+ ports {
+ mipi_out: port@1 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "hannstar,hsd060bhw4";
+ reg = <0>;
+ backlight = <&backlight>;
+ reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vcc2v8_lcd>;
+ iovcc-supply = <&vcc1v8_lcd>;
+ pinctrl-names = "default";
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
&pmu_io_domains {
pmu1830-supply = <&vcc_1v8>;
status = "okay";
@@ -422,6 +536,15 @@
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
@@ -472,3 +595,27 @@
&uart2 {
status = "okay";
};
+
+&vopb {
+ status = "okay";
+ assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
+ <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+ assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,
+ <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index c36898364b5d..1bb7b35a255c 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
@@ -33,7 +33,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -54,18 +53,20 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
@@ -85,5 +86,4 @@ CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
` (20 preceding siblings ...)
2024-05-01 16:22 ` [PATCH v2 21/22] rockchip: rk3399-pinephone-pro: " Jonas Karlman
@ 2024-05-01 16:22 ` Jonas Karlman
2024-05-01 20:23 ` Dragan Simic
` (2 more replies)
21 siblings, 3 replies; 30+ messages in thread
From: Jonas Karlman @ 2024-05-01 16:22 UTC (permalink / raw
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot, Jonas Karlman
Remove the obsolete ethernet0 alias now that all board device tree files
have been fully synced with Linux kernel v6.8.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
arch/arm/dts/rk3399-u-boot.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 6af9621ac3d0..b6b43271172e 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -6,7 +6,6 @@
/ {
aliases {
- ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
pci0 = &pcie0;
--
2.43.2
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
@ 2024-05-01 20:23 ` Dragan Simic
2024-05-02 8:23 ` Christopher Obbard
2024-05-02 10:50 ` Peter Robinson
2 siblings, 0 replies; 30+ messages in thread
From: Dragan Simic @ 2024-05-01 20:23 UTC (permalink / raw
To: Jonas Karlman
Cc: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Quentin Schulz, Christopher Obbard, Peter Robinson, u-boot
On 2024-05-01 18:22, Jonas Karlman wrote:
> Remove the obsolete ethernet0 alias now that all board device tree
> files
> have been fully synced with Linux kernel v6.8.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Nice, thanks for handling the move of the ethernetX aliases around.
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> ---
> v2: New patch
> ---
> arch/arm/dts/rk3399-u-boot.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi
> b/arch/arm/dts/rk3399-u-boot.dtsi
> index 6af9621ac3d0..b6b43271172e 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -6,7 +6,6 @@
>
> / {
> aliases {
> - ethernet0 = &gmac;
> mmc0 = &sdhci;
> mmc1 = &sdmmc;
> pci0 = &pcie0;
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
2024-05-01 20:23 ` Dragan Simic
@ 2024-05-02 8:23 ` Christopher Obbard
2024-05-02 10:50 ` Peter Robinson
2 siblings, 0 replies; 30+ messages in thread
From: Christopher Obbard @ 2024-05-02 8:23 UTC (permalink / raw
To: Jonas Karlman, Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Quentin Schulz, Dragan Simic, Peter Robinson, u-boot
Hi Jonas,
On Wed, 2024-05-01 at 16:22 +0000, Jonas Karlman wrote:
> Remove the obsolete ethernet0 alias now that all board device tree files
> have been fully synced with Linux kernel v6.8.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Looks good to me.
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
> ---
> v2: New patch
> ---
> arch/arm/dts/rk3399-u-boot.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-
> boot.dtsi
> index 6af9621ac3d0..b6b43271172e 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -6,7 +6,6 @@
>
> / {
> aliases {
> - ethernet0 = &gmac;
> mmc0 = &sdhci;
> mmc1 = &sdmmc;
> pci0 = &pcie0;
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
2024-05-01 20:23 ` Dragan Simic
2024-05-02 8:23 ` Christopher Obbard
@ 2024-05-02 10:50 ` Peter Robinson
2 siblings, 0 replies; 30+ messages in thread
From: Peter Robinson @ 2024-05-02 10:50 UTC (permalink / raw
To: Jonas Karlman
Cc: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Quentin Schulz, Dragan Simic, Christopher Obbard, u-boot
On Wed, 1 May 2024 at 17:25, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Remove the obsolete ethernet0 alias now that all board device tree files
> have been fully synced with Linux kernel v6.8.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
> ---
> v2: New patch
> ---
> arch/arm/dts/rk3399-u-boot.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
> index 6af9621ac3d0..b6b43271172e 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -6,7 +6,6 @@
>
> / {
> aliases {
> - ethernet0 = &gmac;
> mmc0 = &sdhci;
> mmc1 = &sdmmc;
> pci0 = &pcie0;
> --
> 2.43.2
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
2024-05-01 16:22 ` [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock Jonas Karlman
@ 2024-05-06 10:32 ` Kever Yang
2024-05-06 11:07 ` Quentin Schulz
1 sibling, 0 replies; 30+ messages in thread
From: Kever Yang @ 2024-05-06 10:32 UTC (permalink / raw
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot
On 2024/5/2 00:22, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
>
> The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
> use of 24 MHz parent and rate.
>
> Add improved support for setting parent and rate of the pciephy refclk
> to driver to better support assign-clock props for pciephy refclk in DT.
>
> This limited implementation only support setting 24 or 100 MHz rate,
> and expect npll and clk_pciephy_ref100m divider to use default values.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
> ---
> drivers/clk/rockchip/clk_rk3399.c | 59 +++++++++++++++++++++++++++++--
> 1 file changed, 57 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5934771b4096..0b3223611a32 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> return rk3399_saradc_get_clk(cru);
> }
>
> +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
> +{
> + if (readl(&cru->clksel_con[18]) & BIT(10))
> + return 100 * MHz;
> + else
> + return OSC_HZ;
> +}
> +
> +static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz)
> +{
> + if (hz == 100 * MHz)
> + rk_setreg(&cru->clksel_con[18], BIT(10));
> + else if (hz == OSC_HZ)
> + rk_clrreg(&cru->clksel_con[18], BIT(10));
> + else
> + return -EINVAL;
> +
> + return rk3399_pciephy_get_clk(cru);
> +}
> +
> static ulong rk3399_clk_get_rate(struct clk *clk)
> {
> struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -967,6 +987,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
> case SCLK_SARADC:
> rate = rk3399_saradc_get_clk(priv->cru);
> break;
> + case SCLK_PCIEPHY_REF:
> + rate = rk3399_pciephy_get_clk(priv->cru);
> + break;
> case ACLK_VIO:
> case ACLK_HDCP:
> case ACLK_GIC_PRE:
> @@ -1058,6 +1081,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
> case SCLK_SARADC:
> ret = rk3399_saradc_set_clk(priv->cru, rate);
> break;
> + case SCLK_PCIEPHY_REF:
> + ret = rk3399_pciephy_set_clk(priv->cru, rate);
> + break;
> case ACLK_VIO:
> case ACLK_HDCP:
> case ACLK_GIC_PRE:
> @@ -1108,12 +1134,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
> return -EINVAL;
> }
>
> +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
> + struct clk *parent)
> +{
> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> + const char *clock_output_name;
> + int ret;
> +
> + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
> + rk_setreg(&priv->cru->clksel_con[18], BIT(10));
> + return 0;
> + }
> +
> + ret = dev_read_string_index(parent->dev, "clock-output-names",
> + parent->id, &clock_output_name);
> + if (ret < 0)
> + return -ENODATA;
> +
> + if (!strcmp(clock_output_name, "xin24m")) {
> + rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
> struct clk *parent)
> {
> switch (clk->id) {
> case SCLK_RMII_SRC:
> return rk3399_gmac_set_parent(clk, parent);
> + case SCLK_PCIEPHY_REF:
> + return rk3399_pciephy_set_parent(clk, parent);
> }
>
> debug("%s: unsupported clk %ld\n", __func__, clk->id);
> @@ -1204,7 +1257,8 @@ static int rk3399_clk_enable(struct clk *clk)
> rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
> break;
> case SCLK_PCIEPHY_REF:
> - rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> + if (readl(&priv->cru->clksel_con[18]) & BIT(10))
> + rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
> break;
> default:
> debug("%s: unsupported clk %ld\n", __func__, clk->id);
> @@ -1298,7 +1352,8 @@ static int rk3399_clk_disable(struct clk *clk)
> rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
> break;
> case SCLK_PCIEPHY_REF:
> - rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> + if (readl(&priv->cru->clksel_con[18]) & BIT(10))
> + rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
> break;
> default:
> debug("%s: unsupported clk %ld\n", __func__, clk->id);
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
2024-05-01 16:22 ` [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock Jonas Karlman
2024-05-06 10:32 ` Kever Yang
@ 2024-05-06 11:07 ` Quentin Schulz
2024-05-06 15:17 ` Jonas Karlman
1 sibling, 1 reply; 30+ messages in thread
From: Quentin Schulz @ 2024-05-06 11:07 UTC (permalink / raw
To: Jonas Karlman, Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Quentin Schulz, Dragan Simic, Christopher Obbard, Peter Robinson,
u-boot
Hi Jonas,
On 5/1/24 6:22 PM, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
>
> The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
> use of 24 MHz parent and rate.
>
> Add improved support for setting parent and rate of the pciephy refclk
> to driver to better support assign-clock props for pciephy refclk in DT.
>
> This limited implementation only support setting 24 or 100 MHz rate,
> and expect npll and clk_pciephy_ref100m divider to use default values.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
> v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
> ---
> drivers/clk/rockchip/clk_rk3399.c | 59 +++++++++++++++++++++++++++++--
> 1 file changed, 57 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5934771b4096..0b3223611a32 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
> return rk3399_saradc_get_clk(cru);
> }
>
> +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
> +{
> + if (readl(&cru->clksel_con[18]) & BIT(10))
> + return 100 * MHz;
> + else
> + return OSC_HZ;
Could avoid the else since all if blocks return, no other logic than the
one matching the else can reach that part of the code.
Therefore:
"""
if (readl(&cru->clksel_con[18]) & BIT(10))
return 100 * MHz;
return OSC_HZ;
"""
works just as well.
Could also be
"""
return (readl(&cru->clksel_con[18]) & BIT(10)) ? 100 * MHz : OSC_HZ;
"""
[...]
> +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
> + struct clk *parent)
> +{
> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> + const char *clock_output_name;
> + int ret;
> +
> + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
> + rk_setreg(&priv->cru->clksel_con[18], BIT(10));
> + return 0;
> + }
> +
> + ret = dev_read_string_index(parent->dev, "clock-output-names",
> + parent->id, &clock_output_name);
Are you sure this works?
Considering that parent->id seems to store unique ids, like 167 for
SCLK_PCIEPHY_REF100M, I doubt we should be using it for
dev_read_string_index????
As per documentation:
"""
/**
* dev_read_string_index() - obtain an indexed string from a string list
*
* @dev: device to examine
* @propname: name of the property containing the string list
* @index: index of the string to return
* @outp: return location for the string
*
* Return:
* length of string, if found or -ve error value if not found
*/
int dev_read_string_index(const struct udevice *dev, const char *propname,
int index, const char **outp);
"""
So index here means the (index+1)'th string in the list of strings under
the "propname" DT property, I doubt we have properties with 167+ strings
in them?
I realize that rk3399_gmac_set_parent also uses this, so I'm a bit
puzzled right now...
Don't you want to use
dev_read_stringlist_search(parent->dev, "clock-output-names", "xin24m")
instead?
The rest looks good to me.
Cheers,
Quentin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
2024-05-06 11:07 ` Quentin Schulz
@ 2024-05-06 15:17 ` Jonas Karlman
2024-05-06 15:52 ` Quentin Schulz
0 siblings, 1 reply; 30+ messages in thread
From: Jonas Karlman @ 2024-05-06 15:17 UTC (permalink / raw
To: Quentin Schulz, Quentin Schulz
Cc: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson, Dragan Simic, Christopher Obbard,
Peter Robinson, u-boot
Hi Quentin,
On 2024-05-06 13:07, Quentin Schulz wrote:
> Hi Jonas,
>
> On 5/1/24 6:22 PM, Jonas Karlman wrote:
>> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
>> SCLK_PCIEPHY_REF clock.
>>
>> The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
>> use of 24 MHz parent and rate.
>>
>> Add improved support for setting parent and rate of the pciephy refclk
>> to driver to better support assign-clock props for pciephy refclk in DT.
>>
>> This limited implementation only support setting 24 or 100 MHz rate,
>> and expect npll and clk_pciephy_ref100m divider to use default values.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> ---
>> v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
>> ---
>> drivers/clk/rockchip/clk_rk3399.c | 59 +++++++++++++++++++++++++++++--
>> 1 file changed, 57 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
>> index 5934771b4096..0b3223611a32 100644
>> --- a/drivers/clk/rockchip/clk_rk3399.c
>> +++ b/drivers/clk/rockchip/clk_rk3399.c
>> @@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
>> return rk3399_saradc_get_clk(cru);
>> }
>>
>> +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
>> +{
>> + if (readl(&cru->clksel_con[18]) & BIT(10))
>> + return 100 * MHz;
>> + else
>> + return OSC_HZ;
>
> Could avoid the else since all if blocks return, no other logic than the
> one matching the else can reach that part of the code.
>
> Therefore:
>
> """
> if (readl(&cru->clksel_con[18]) & BIT(10))
> return 100 * MHz;
>
> return OSC_HZ;
> """
>
> works just as well.
I was considering above format at first, but chose to align return
statements for some reason.
I can change to this format in a v3, if needed :-)
>
> Could also be
>
> """
> return (readl(&cru->clksel_con[18]) & BIT(10)) ? 100 * MHz : OSC_HZ;
> """
>
> [...]
>> +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
>> + struct clk *parent)
>> +{
>> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
>> + const char *clock_output_name;
>> + int ret;
>> +
>> + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
>> + rk_setreg(&priv->cru->clksel_con[18], BIT(10));
>> + return 0;
>> + }
>> +
>> + ret = dev_read_string_index(parent->dev, "clock-output-names",
>> + parent->id, &clock_output_name);
>
> Are you sure this works?
It should work for the clk reference I tested, <&xin24m>, where the id
will be 0, it should also work for e.g. <&rk809 1>, id will be 1.
And if a &cru/&pmucru clk is referenced those nodes do not have the
clock-output-names prop, so ret should be -EINVAL (or -ENODATA).
>
> Considering that parent->id seems to store unique ids, like 167 for
> SCLK_PCIEPHY_REF100M, I doubt we should be using it for
> dev_read_string_index????
>
> As per documentation:
>
> """
> /**
> * dev_read_string_index() - obtain an indexed string from a string list
> *
> * @dev: device to examine
> * @propname: name of the property containing the string list
> * @index: index of the string to return
> * @outp: return location for the string
> *
> * Return:
> * length of string, if found or -ve error value if not found
> */
> int dev_read_string_index(const struct udevice *dev, const char *propname,
> int index, const char **outp);
> """
>
> So index here means the (index+1)'th string in the list of strings under
> the "propname" DT property, I doubt we have properties with 167+ strings
> in them?
I would expect the function to return -EINVAL or -ENODATA if it is called
with an out-of-bounds index value.
>
> I realize that rk3399_gmac_set_parent also uses this, so I'm a bit
> puzzled right now...
>
> Don't you want to use
>
> dev_read_stringlist_search(parent->dev, "clock-output-names", "xin24m")
>
> instead?
I think the implementation is correct and is what other rk clk drivers
do for gmac set parent ops.
Using dev_read_stringlist_search() could possible match a name for
"wrong" clock, e.g:
clk_ref: clock {
#clock-cells = <1>;
clock-output-names = "xin32k", "xin24m";
};
here only <&clk_ref 1> should match and not <&clk_ref 0>.
Regards,
Jonas
>
> The rest looks good to me.
>
> Cheers,
> Quentin
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock
2024-05-06 15:17 ` Jonas Karlman
@ 2024-05-06 15:52 ` Quentin Schulz
0 siblings, 0 replies; 30+ messages in thread
From: Quentin Schulz @ 2024-05-06 15:52 UTC (permalink / raw
To: Jonas Karlman, Quentin Schulz
Cc: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson, Dragan Simic, Christopher Obbard,
Peter Robinson, u-boot
Hi Jonas,
On 5/6/24 5:17 PM, Jonas Karlman wrote:
> Hi Quentin,
>
> On 2024-05-06 13:07, Quentin Schulz wrote:
>> Hi Jonas,
>>
>> On 5/1/24 6:22 PM, Jonas Karlman wrote:
>>> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
>>> SCLK_PCIEPHY_REF clock.
>>>
>>> The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
>>> use of 24 MHz parent and rate.
>>>
>>> Add improved support for setting parent and rate of the pciephy refclk
>>> to driver to better support assign-clock props for pciephy refclk in DT.
>>>
>>> This limited implementation only support setting 24 or 100 MHz rate,
>>> and expect npll and clk_pciephy_ref100m divider to use default values.
>>>
>>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>>> ---
>>> v2: Implement partial instead of dummy support for SCLK_PCIEPHY_REF
>>> ---
>>> drivers/clk/rockchip/clk_rk3399.c | 59 +++++++++++++++++++++++++++++--
>>> 1 file changed, 57 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
>>> index 5934771b4096..0b3223611a32 100644
>>> --- a/drivers/clk/rockchip/clk_rk3399.c
>>> +++ b/drivers/clk/rockchip/clk_rk3399.c
>>> @@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
>>> return rk3399_saradc_get_clk(cru);
>>> }
>>>
>>> +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
>>> +{
>>> + if (readl(&cru->clksel_con[18]) & BIT(10))
>>> + return 100 * MHz;
>>> + else
>>> + return OSC_HZ;
>>
>> Could avoid the else since all if blocks return, no other logic than the
>> one matching the else can reach that part of the code.
>>
>> Therefore:
>>
>> """
>> if (readl(&cru->clksel_con[18]) & BIT(10))
>> return 100 * MHz;
>>
>> return OSC_HZ;
>> """
>>
>> works just as well.
>
> I was considering above format at first, but chose to align return
> statements for some reason.
>
> I can change to this format in a v3, if needed :-)
>
Just a matter of taste :)
>>
>> Could also be
>>
>> """
>> return (readl(&cru->clksel_con[18]) & BIT(10)) ? 100 * MHz : OSC_HZ;
>> """
>>
>> [...]
>>> +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
>>> + struct clk *parent)
>>> +{
>>> + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
>>> + const char *clock_output_name;
>>> + int ret;
>>> +
>>> + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
>>> + rk_setreg(&priv->cru->clksel_con[18], BIT(10));
>>> + return 0;
>>> + }
>>> +
>>> + ret = dev_read_string_index(parent->dev, "clock-output-names",
>>> + parent->id, &clock_output_name);
>>
>> Are you sure this works?
>
> It should work for the clk reference I tested, <&xin24m>, where the id
> will be 0, it should also work for e.g. <&rk809 1>, id will be 1.
>
> And if a &cru/&pmucru clk is referenced those nodes do not have the
> clock-output-names prop, so ret should be -EINVAL (or -ENODATA).
>
>>
>> Considering that parent->id seems to store unique ids, like 167 for
>> SCLK_PCIEPHY_REF100M, I doubt we should be using it for
>> dev_read_string_index????
>>
>> As per documentation:
>>
>> """
>> /**
>> * dev_read_string_index() - obtain an indexed string from a string list
>> *
>> * @dev: device to examine
>> * @propname: name of the property containing the string list
>> * @index: index of the string to return
>> * @outp: return location for the string
>> *
>> * Return:
>> * length of string, if found or -ve error value if not found
>> */
>> int dev_read_string_index(const struct udevice *dev, const char *propname,
>> int index, const char **outp);
>> """
>>
>> So index here means the (index+1)'th string in the list of strings under
>> the "propname" DT property, I doubt we have properties with 167+ strings
>> in them?
>
> I would expect the function to return -EINVAL or -ENODATA if it is called
> with an out-of-bounds index value.
>
-ENODATA it seems. -EINVAL if the property doesn't exist.
>>
>> I realize that rk3399_gmac_set_parent also uses this, so I'm a bit
>> puzzled right now...
>>
>> Don't you want to use
>>
>> dev_read_stringlist_search(parent->dev, "clock-output-names", "xin24m")
>>
>> instead?
>
> I think the implementation is correct and is what other rk clk drivers
> do for gmac set parent ops.
>
> Using dev_read_stringlist_search() could possible match a name for
> "wrong" clock, e.g:
>
> clk_ref: clock {
> #clock-cells = <1>;
> clock-output-names = "xin32k", "xin24m";
> };
>
> here only <&clk_ref 1> should match and not <&clk_ref 0>.
>
Ah well, one more brain fart :) I somehow mixed things up and was
thinking about the values in clocks/assigned-clocks in one node needing
to match the offset in clock-names of that same node, which made no
sense. But we're talking about different things here :)
I guess it's just a matter of taste between the implementation in your
patch and the inverted logic which tries to find xin24m in
clock-output-names and checks its index matches parent->id. Consistency
is preferred, and the former is already used in other places, so let's
keep this.
Thanks for taking the time to explain.
This does seem reasonable to me, so:
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Thanks!
Quentin
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2024-05-06 15:52 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-01 16:22 [PATCH v2 00/22] rockchip: rk3399: Sync DT with v6.8 and update defconfigs Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 01/22] clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 02/22] clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock Jonas Karlman
2024-05-06 10:32 ` Kever Yang
2024-05-06 11:07 ` Quentin Schulz
2024-05-06 15:17 ` Jonas Karlman
2024-05-06 15:52 ` Quentin Schulz
2024-05-01 16:22 ` [PATCH v2 04/22] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 05/22] rockchip: rk3399: Sync SoC DT from Linux kernel v6.8 Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 06/22] rockchip: rk3399-gru: Sync " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 07/22] rockchip: rk3399-puma: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 08/22] rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 09/22] rockchip: rk3399-eaidk-610: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 10/22] rockchip: rk3399-leez: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 11/22] rockchip: rk3399-evb: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 12/22] rockchip: rk3399-firefly: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 13/22] rockchip: rk3399-orangepi: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 14/22] rockchip: rk3399-roc-pc: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 15/22] rockchip: rk3399-nanopi-4: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 16/22] rockchip: rk3399-rock960: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 17/22] rockchip: rk3399-khadas: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 18/22] rockchip: rk3399-rock-pi-4: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 19/22] rockchip: rk3399-rockpro64: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 20/22] rockchip: rk3399-pinebook-pro: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 21/22] rockchip: rk3399-pinephone-pro: " Jonas Karlman
2024-05-01 16:22 ` [PATCH v2 22/22] rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi Jonas Karlman
2024-05-01 20:23 ` Dragan Simic
2024-05-02 8:23 ` Christopher Obbard
2024-05-02 10:50 ` Peter Robinson
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