From: Jason Gunthorpe <jgg@ziepe.ca> To: Tomasz Jeznach <tjeznach@rivosinc.com> Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <apatel@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Nick Kossifidis <mick@ics.forth.gr>, Sebastien Boeuf <seb@rivosinc.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH v3 5/7] iommu/riscv: Device directory management. Date: Wed, 1 May 2024 11:57:31 -0300 [thread overview] Message-ID: <20240501145731.GE1723318@ziepe.ca> (raw) In-Reply-To: <ce3b82a20db0b776685269674ce9b7a926d5680d.1714494653.git.tjeznach@rivosinc.com> On Tue, Apr 30, 2024 at 01:01:55PM -0700, Tomasz Jeznach wrote: > Introduce device context allocation and device directory tree > management including capabilities discovery sequence, as described > in Chapter 2.1 of the RISC-V IOMMU Architecture Specification. > > Device directory mode will be auto detected using DDTP WARL property, > using highest mode supported by the driver and hardware. If none > supported can be configured, driver will fall back to global pass-through. > > First level DDTP page can be located in I/O (detected using DDTP WARL) > and system memory. > > Only simple identity and release (blocking) protection domains are > supported by this implementation. Why rename the concept? We call it a BLOCKING domain, just use that name please. > +static int riscv_iommu_attach_release_domain(struct iommu_domain *iommu_domain, > + struct device *dev) > +{ > + struct riscv_iommu_device *iommu = dev_to_iommu(dev); > + > + if (iommu->ddt_mode > RISCV_IOMMU_DDTP_MODE_BARE) > + riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); > + > + return 0; > +} > + > +static struct iommu_domain riscv_iommu_release_domain = { > + .type = IOMMU_DOMAIN_BLOCKED, > + .ops = &(const struct iommu_domain_ops) { > + .attach_dev = riscv_iommu_attach_release_domain, > + } > +}; 'riscv_iommu_release_domain' doesn't make sense.. Jason
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@ziepe.ca> To: Tomasz Jeznach <tjeznach@rivosinc.com> Cc: Anup Patel <apatel@ventanamicro.com>, devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>, linux@rivosinc.com, Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Sebastien Boeuf <seb@rivosinc.com>, iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Nick Kossifidis <mick@ics.forth.gr>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Robin Murphy <robin.murphy@arm.com>, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 5/7] iommu/riscv: Device directory management. Date: Wed, 1 May 2024 11:57:31 -0300 [thread overview] Message-ID: <20240501145731.GE1723318@ziepe.ca> (raw) In-Reply-To: <ce3b82a20db0b776685269674ce9b7a926d5680d.1714494653.git.tjeznach@rivosinc.com> On Tue, Apr 30, 2024 at 01:01:55PM -0700, Tomasz Jeznach wrote: > Introduce device context allocation and device directory tree > management including capabilities discovery sequence, as described > in Chapter 2.1 of the RISC-V IOMMU Architecture Specification. > > Device directory mode will be auto detected using DDTP WARL property, > using highest mode supported by the driver and hardware. If none > supported can be configured, driver will fall back to global pass-through. > > First level DDTP page can be located in I/O (detected using DDTP WARL) > and system memory. > > Only simple identity and release (blocking) protection domains are > supported by this implementation. Why rename the concept? We call it a BLOCKING domain, just use that name please. > +static int riscv_iommu_attach_release_domain(struct iommu_domain *iommu_domain, > + struct device *dev) > +{ > + struct riscv_iommu_device *iommu = dev_to_iommu(dev); > + > + if (iommu->ddt_mode > RISCV_IOMMU_DDTP_MODE_BARE) > + riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); > + > + return 0; > +} > + > +static struct iommu_domain riscv_iommu_release_domain = { > + .type = IOMMU_DOMAIN_BLOCKED, > + .ops = &(const struct iommu_domain_ops) { > + .attach_dev = riscv_iommu_attach_release_domain, > + } > +}; 'riscv_iommu_release_domain' doesn't make sense.. Jason _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-05-01 14:57 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-30 20:01 [PATCH v3 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-04-30 20:01 ` [PATCH v3 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 9:30 ` Conor Dooley 2024-05-01 9:30 ` Conor Dooley 2024-05-01 13:15 ` Rob Herring 2024-05-01 13:15 ` Rob Herring 2024-05-02 2:47 ` Tomasz Jeznach 2024-05-02 2:47 ` Tomasz Jeznach 2024-05-02 15:15 ` Conor Dooley 2024-05-02 15:15 ` Conor Dooley 2024-04-30 20:01 ` [PATCH v3 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 10:26 ` Baolu Lu 2024-05-01 10:26 ` Baolu Lu 2024-05-01 14:20 ` Jason Gunthorpe 2024-05-01 14:20 ` Jason Gunthorpe 2024-05-02 2:23 ` Baolu Lu 2024-05-02 2:23 ` Baolu Lu 2024-05-02 2:44 ` Tomasz Jeznach 2024-05-02 2:44 ` Tomasz Jeznach 2024-04-30 20:01 ` [PATCH v3 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 10:01 ` Baolu Lu 2024-05-01 10:01 ` Baolu Lu 2024-04-30 20:01 ` [PATCH v3 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 9:53 ` Baolu Lu 2024-05-01 9:53 ` Baolu Lu 2024-04-30 20:01 ` [PATCH v3 5/7] iommu/riscv: Device directory management Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 14:57 ` Jason Gunthorpe [this message] 2024-05-01 14:57 ` Jason Gunthorpe 2024-05-02 1:38 ` Baolu Lu 2024-05-02 1:38 ` Baolu Lu 2024-05-02 1:57 ` Baolu Lu 2024-05-02 1:57 ` Baolu Lu 2024-05-02 2:06 ` Baolu Lu 2024-05-02 2:06 ` Baolu Lu 2024-04-30 20:01 ` [PATCH v3 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-02 3:51 ` Baolu Lu 2024-05-02 3:51 ` Baolu Lu 2024-04-30 20:01 ` [PATCH v3 7/7] iommu/riscv: Paging domain support Tomasz Jeznach 2024-04-30 20:01 ` Tomasz Jeznach 2024-05-01 14:56 ` Jason Gunthorpe 2024-05-01 14:56 ` Jason Gunthorpe 2024-05-03 17:44 ` Tomasz Jeznach 2024-05-03 17:44 ` Tomasz Jeznach 2024-05-03 18:10 ` Jason Gunthorpe 2024-05-03 18:10 ` Jason Gunthorpe 2024-05-03 19:44 ` Tomasz Jeznach 2024-05-03 19:44 ` Tomasz Jeznach 2024-05-05 15:46 ` Jason Gunthorpe 2024-05-05 15:46 ` Jason Gunthorpe 2024-05-07 2:22 ` Tomasz Jeznach 2024-05-07 2:22 ` Tomasz Jeznach 2024-05-07 16:51 ` Jason Gunthorpe 2024-05-07 16:51 ` Jason Gunthorpe 2024-05-08 16:23 ` Tomasz Jeznach 2024-05-08 16:23 ` Tomasz Jeznach 2024-05-02 3:50 ` Baolu Lu 2024-05-02 3:50 ` Baolu Lu 2024-05-02 4:39 ` Tomasz Jeznach 2024-05-02 4:39 ` Tomasz Jeznach 2024-05-01 16:07 ` [PATCH v3 0/7] Linux RISC-V IOMMU Support Jason Gunthorpe 2024-05-01 16:07 ` Jason Gunthorpe
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