From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 14/18] drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
Date: Fri, 12 Apr 2024 21:26:59 +0300 [thread overview]
Message-ID: <20240412182703.19916-15-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20240412182703.19916-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename all the ye olde 'pipe_config's to the modern
'crtc_state' name in the legacy DPLL code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 30 +++++++++++------------
drivers/gpu/drm/i915/display/intel_dpll.h | 6 ++---
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9d57262ac577..4df40a14d0f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -415,20 +415,20 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 dpll = pipe_config->dpll_hw_state.dpll;
+ u32 dpll = crtc_state->dpll_hw_state.dpll;
u32 fp;
struct dpll clock;
int port_clock;
- int refclk = i9xx_pll_refclk(pipe_config);
+ int refclk = i9xx_pll_refclk(crtc_state);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
- fp = pipe_config->dpll_hw_state.fp0;
+ fp = crtc_state->dpll_hw_state.fp0;
else
- fp = pipe_config->dpll_hw_state.fp1;
+ fp = crtc_state->dpll_hw_state.fp1;
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev_priv)) {
@@ -503,12 +503,12 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config)
* port_clock to compute adjusted_mode.crtc_clock in the
* encoder's get_config() function.
*/
- pipe_config->port_clock = port_clock;
+ crtc_state->port_clock = port_clock;
}
-void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
struct dpll clock;
@@ -516,7 +516,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -529,12 +529,12 @@ void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config)
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
- pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
+ crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
}
-void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
+void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
@@ -543,7 +543,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
int refclk = 100000;
/* In case of DSI, DPLL will not be used */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
@@ -562,7 +562,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *pipe_config)
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
- pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
+ crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index dc47affba2ba..49591bda7f8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -42,9 +42,9 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-void i9xx_crtc_clock_get(struct intel_crtc_state *pipe_config);
-void vlv_crtc_clock_get(struct intel_crtc_state *pipe_config);
-void chv_crtc_clock_get(struct intel_crtc_state *pipe_config);
+void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
+void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
+void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
--
2.43.2
next prev parent reply other threads:[~2024-04-12 18:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 18:26 [PATCH 00/18] drm/i915: PLL refactoring Ville Syrjala
2024-04-12 18:26 ` [PATCH 01/18] drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 02/18] drm/i915: Use printer for the rest of PLL debugfs dump Ville Syrjala
2024-04-12 18:26 ` [PATCH 03/18] drm/i915: Rename PLL hw_state variables/arguments Ville Syrjala
2024-04-12 18:26 ` [PATCH 04/18] drm/i915: Introduce some local PLL state variables Ville Syrjala
2024-04-12 18:26 ` [PATCH 05/18] drm/i915: Extract ilk_fb_cb_factor() Ville Syrjala
2024-04-12 18:26 ` [PATCH 06/18] drm/i915: Extract ilk_dpll_compute_fp() Ville Syrjala
2024-04-12 18:26 ` [PATCH 07/18] drm/i915: Extract i9xx_dpll_get_hw_state() Ville Syrjala
2024-04-12 18:26 ` [PATCH 08/18] drm/i915: Pass the PLL hw_state to pll->enable() Ville Syrjala
2024-04-12 18:26 ` [PATCH 09/18] drm/i915: Extract i965_dpll_md() Ville Syrjala
2024-04-12 18:26 ` [PATCH 10/18] drm/i915: Extract {i9xx,i8xx,ilk}_dpll() Ville Syrjala
2024-04-15 14:06 ` Jani Nikula
2024-04-12 18:26 ` [PATCH 11/18] drm/i915: Inline {i9xx,ilk}_update_pll_dividers() Ville Syrjala
2024-04-12 18:26 ` [PATCH 12/18] drm/i915: Modernize i9xx_pll_refclk() Ville Syrjala
2024-04-12 18:26 ` [PATCH 13/18] drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() Ville Syrjala
2024-04-12 18:26 ` Ville Syrjala [this message]
2024-04-12 18:27 ` [PATCH 15/18] drm/i915: Add local DPLL 'hw_state' variables Ville Syrjala
2024-04-12 18:27 ` [PATCH 16/18] drm/i915: Carve up struct intel_dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 17/18] drm/i915: Unionize dpll_hw_state Ville Syrjala
2024-04-12 18:27 ` [PATCH 18/18] drm/i915: Suck snps/cx0 PLL states into dpll_hw_state Ville Syrjala
2024-04-15 14:26 ` Jani Nikula
2024-04-15 14:26 ` [PATCH 00/18] drm/i915: PLL refactoring Jani Nikula
2024-04-15 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-04-15 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-04-15 15:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 19:06 ` ✓ Fi.CI.IGT: " Patchwork
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