From: Eric Biggers <ebiggers@kernel.org>
To: Dave Hansen <dave.hansen@intel.com>
Cc: linux-crypto@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Andy Lutomirski <luto@kernel.org>,
"Chang S . Bae" <chang.seok.bae@intel.com>
Subject: Re: [PATCH v2 6/6] crypto: x86/aes-xts - wire up VAES + AVX10/512 implementation
Date: Thu, 4 Apr 2024 20:11:23 -0400 [thread overview]
Message-ID: <20240405001123.GA1958@quark.localdomain> (raw)
In-Reply-To: <c806bffe-6e87-4c51-ac99-4b2612d3c334@intel.com>
On Thu, Apr 04, 2024 at 04:53:12PM -0700, Dave Hansen wrote:
> On 4/4/24 16:36, Eric Biggers wrote:
> > 1. Never use zmm registers.
> ...
> > 4. Keep the proposed policy as the default behavior, but allow it to be
> > overridden on the kernel command line. This would be a bit more flexible;
> > however, most people don't change defaults anyway.
> >
> > When you write "Some folks will also surely disagree with the kernel policy
> > implemented here", are there any specific concerns that you anticipate?
>
> Some people care less about the frequency throttling and only care about
> max performance _using_ AVX512.
>
> > Note that Intel has acknowledged the zmm downclocking issues on Ice
> > Lake and suggested that using ymm registers instead would be
> > reasonable:>
> https://lore.kernel.org/linux-crypto/e8ce1146-3952-6977-1d0e-a22758e58914@intel.com/
> >
> > If there is really a controversy, my vote is that for now we just go with option
> > (1), i.e. drop this patch from the series. We can reconsider the issue when a
> > CPU is released with better 512-bit support.
>
> (1) is fine with me.
>
> (4) would also be fine. But I don't think it absolutely _has_ to be a
> boot-time switch. What prevents you from registering, say,
> "xts-aes-vaes-avx10" and then doing:
>
> if (avx512_is_desired())
> xts-aes-vaes-avx10_512(...);
> else
> xts-aes-vaes-avx10_256(...);
>
> at runtime?
>
> Where avx512_is_desired() can be changed willy-nilly, either with a
> command-line parameter or runtime knob. Sure, the performance might
> change versus what was measured, but I don't think that's a deal breaker.
>
> Then if folks want to do fancy benchmarks or model/family checks or
> whatever, they can do it in userspace at runtime.
It's certainly possible for a single crypto algorithm (using "algorithm" in the
crypto API sense of the word) to have multiple alternative code paths, and there
are examples of this in arch/x86/crypto/. However, I think this is a poor
practice, at least as the crypto API is currently designed, because it makes it
difficult to test the different code paths. Alternatives are best handled by
registering them as separate algorithms with different cra_priority values.
Also, I forgot one property of my patch, which is that because I made the
zmm_exclusion_list just decrease the priority of xts-aes-vaes-avx10_512 rather
than skipping registering it, the change actually can be undone at runtime by
increasing the priority of xts-aes-vaes-avx10_512 back to its original value.
Userspace can do it using the "crypto user configuration API"
(include/uapi/linux/cryptouser.h), specifically CRYPTO_MSG_UPDATEALG.
Maybe that is enough configurability already?
- Eric
next prev parent reply other threads:[~2024-04-05 0:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 8:03 [PATCH v2 0/6] Faster AES-XTS on modern x86_64 CPUs Eric Biggers
2024-03-29 8:03 ` [PATCH v2 1/6] x86: add kconfig symbols for assembler VAES and VPCLMULQDQ support Eric Biggers
2024-03-29 8:03 ` [PATCH v2 2/6] crypto: x86/aes-xts - add AES-XTS assembly macro for modern CPUs Eric Biggers
2024-03-29 8:03 ` [PATCH v2 3/6] crypto: x86/aes-xts - wire up AESNI + AVX implementation Eric Biggers
2024-03-29 8:03 ` [PATCH v2 4/6] crypto: x86/aes-xts - wire up VAES + AVX2 implementation Eric Biggers
2024-03-29 8:03 ` [PATCH v2 5/6] crypto: x86/aes-xts - wire up VAES + AVX10/256 implementation Eric Biggers
2024-03-29 8:03 ` [PATCH v2 6/6] crypto: x86/aes-xts - wire up VAES + AVX10/512 implementation Eric Biggers
2024-04-04 20:34 ` Dave Hansen
2024-04-04 23:36 ` Eric Biggers
2024-04-04 23:53 ` Dave Hansen
2024-04-05 0:11 ` Eric Biggers [this message]
2024-04-05 7:20 ` Herbert Xu
2024-03-29 9:03 ` [PATCH v2 0/6] Faster AES-XTS on modern x86_64 CPUs Ard Biesheuvel
2024-03-29 9:31 ` Eric Biggers
2024-04-03 0:44 ` Eric Biggers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240405001123.GA1958@quark.localdomain \
--to=ebiggers@kernel.org \
--cc=ardb@kernel.org \
--cc=chang.seok.bae@intel.com \
--cc=dave.hansen@intel.com \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.