* [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
@ 2024-03-26 14:42 ` Siddharth Vadapalli
0 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-26 14:42 UTC (permalink / raw
To: lpieralisi, kw, robh, bhelgaas, manivannan.sadhasivam,
fancer.lancer, u.kleine-koenig, cassel, dlemoal,
yoshihiro.shimoda.uh
Cc: linux-pci, linux-kernel, linux-arm-kernel, srk, s-vadapalli
In the process of converting .scan_bus() callbacks to .add_bus(), the
ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
The .scan_bus() method belonged to ks_pcie_host_ops which was specific
to controller version 3.65a, while the .add_bus() method had been added
to ks_pcie_ops which is shared between the controller versions 3.65a and
4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
ks_pcie_v3_65_add_bus() method is applicable to the controller version
4.90a which is present in AM654x SoCs.
Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
.msi_init callback "ks_pcie_msi_host_init()" which is specific to the
3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
avoid forward declaration.
Fixes: 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus")
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Suggested-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on linux-next tagged next-20240326.
v5:
https://lore.kernel.org/r/20240326111905.2369778-1-s-vadapalli@ti.com/
Changes since v5:
- Fixed indentation of comment as pointed out by:
Niklas Cassel <cassel@kernel.org>
at:
https://lore.kernel.org/r/ZgLUCqh12RMApzyr@x1-carbon/
- Collected Reviewed-by tag from:
Niklas Cassel <cassel@kernel.org>
Regards,
Siddharth.
drivers/pci/controller/dwc/pci-keystone.c | 136 ++++++++++------------
1 file changed, 60 insertions(+), 76 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 844de4418724..6cb3a4713009 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -245,8 +245,68 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
.irq_unmask = ks_pcie_msi_unmask,
};
+/**
+ * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
+ * PCIe host controller driver information.
+ *
+ * Since modification of dbi_cs2 involves different clock domain, read the
+ * status back to ensure the transition is complete.
+ */
+static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
+{
+ u32 val;
+
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ val |= DBI_CS2;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
+
+ do {
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ } while (!(val & DBI_CS2));
+}
+
+/**
+ * ks_pcie_clear_dbi_mode() - Disable DBI mode
+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
+ * PCIe host controller driver information.
+ *
+ * Since modification of dbi_cs2 involves different clock domain, read the
+ * status back to ensure the transition is complete.
+ */
+static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
+{
+ u32 val;
+
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ val &= ~DBI_CS2;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
+
+ do {
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ } while (val & DBI_CS2);
+}
+
static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
+
+ /* Configure and set up BAR0 */
+ ks_pcie_set_dbi_mode(ks_pcie);
+
+ /* Enable BAR0 */
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
+
+ ks_pcie_clear_dbi_mode(ks_pcie);
+
+ /*
+ * For BAR0, just setting bus address for inbound writes (MSI) should
+ * be sufficient. Use physical address to avoid any conflicts.
+ */
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
+
pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
return dw_pcie_allocate_domains(pp);
}
@@ -340,48 +400,6 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/**
- * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
- * PCIe host controller driver information.
- *
- * Since modification of dbi_cs2 involves different clock domain, read the
- * status back to ensure the transition is complete.
- */
-static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
-{
- u32 val;
-
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- val |= DBI_CS2;
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
-
- do {
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- } while (!(val & DBI_CS2));
-}
-
-/**
- * ks_pcie_clear_dbi_mode() - Disable DBI mode
- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
- * PCIe host controller driver information.
- *
- * Since modification of dbi_cs2 involves different clock domain, read the
- * status back to ensure the transition is complete.
- */
-static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
-{
- u32 val;
-
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- val &= ~DBI_CS2;
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
-
- do {
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- } while (val & DBI_CS2);
-}
-
static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
u32 val;
@@ -445,44 +463,10 @@ static struct pci_ops ks_child_pcie_ops = {
.write = pci_generic_config_write,
};
-/**
- * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
- * @bus: A pointer to the PCI bus structure.
- *
- * This sets BAR0 to enable inbound access for MSI_IRQ register
- */
-static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
-{
- struct dw_pcie_rp *pp = bus->sysdata;
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
-
- if (!pci_is_root_bus(bus))
- return 0;
-
- /* Configure and set up BAR0 */
- ks_pcie_set_dbi_mode(ks_pcie);
-
- /* Enable BAR0 */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
-
- ks_pcie_clear_dbi_mode(ks_pcie);
-
- /*
- * For BAR0, just setting bus address for inbound writes (MSI) should
- * be sufficient. Use physical address to avoid any conflicts.
- */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
-
- return 0;
-}
-
static struct pci_ops ks_pcie_ops = {
.map_bus = dw_pcie_own_conf_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
- .add_bus = ks_pcie_v3_65_add_bus,
};
/**
--
2.40.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
@ 2024-03-26 14:42 ` Siddharth Vadapalli
0 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-26 14:42 UTC (permalink / raw
To: lpieralisi, kw, robh, bhelgaas, manivannan.sadhasivam,
fancer.lancer, u.kleine-koenig, cassel, dlemoal,
yoshihiro.shimoda.uh
Cc: linux-pci, linux-kernel, linux-arm-kernel, srk, s-vadapalli
In the process of converting .scan_bus() callbacks to .add_bus(), the
ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
The .scan_bus() method belonged to ks_pcie_host_ops which was specific
to controller version 3.65a, while the .add_bus() method had been added
to ks_pcie_ops which is shared between the controller versions 3.65a and
4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
ks_pcie_v3_65_add_bus() method is applicable to the controller version
4.90a which is present in AM654x SoCs.
Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
.msi_init callback "ks_pcie_msi_host_init()" which is specific to the
3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
avoid forward declaration.
Fixes: 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus")
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Suggested-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on linux-next tagged next-20240326.
v5:
https://lore.kernel.org/r/20240326111905.2369778-1-s-vadapalli@ti.com/
Changes since v5:
- Fixed indentation of comment as pointed out by:
Niklas Cassel <cassel@kernel.org>
at:
https://lore.kernel.org/r/ZgLUCqh12RMApzyr@x1-carbon/
- Collected Reviewed-by tag from:
Niklas Cassel <cassel@kernel.org>
Regards,
Siddharth.
drivers/pci/controller/dwc/pci-keystone.c | 136 ++++++++++------------
1 file changed, 60 insertions(+), 76 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 844de4418724..6cb3a4713009 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -245,8 +245,68 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
.irq_unmask = ks_pcie_msi_unmask,
};
+/**
+ * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
+ * PCIe host controller driver information.
+ *
+ * Since modification of dbi_cs2 involves different clock domain, read the
+ * status back to ensure the transition is complete.
+ */
+static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
+{
+ u32 val;
+
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ val |= DBI_CS2;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
+
+ do {
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ } while (!(val & DBI_CS2));
+}
+
+/**
+ * ks_pcie_clear_dbi_mode() - Disable DBI mode
+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
+ * PCIe host controller driver information.
+ *
+ * Since modification of dbi_cs2 involves different clock domain, read the
+ * status back to ensure the transition is complete.
+ */
+static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
+{
+ u32 val;
+
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ val &= ~DBI_CS2;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
+
+ do {
+ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
+ } while (val & DBI_CS2);
+}
+
static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
+
+ /* Configure and set up BAR0 */
+ ks_pcie_set_dbi_mode(ks_pcie);
+
+ /* Enable BAR0 */
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
+
+ ks_pcie_clear_dbi_mode(ks_pcie);
+
+ /*
+ * For BAR0, just setting bus address for inbound writes (MSI) should
+ * be sufficient. Use physical address to avoid any conflicts.
+ */
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
+
pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
return dw_pcie_allocate_domains(pp);
}
@@ -340,48 +400,6 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/**
- * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
- * PCIe host controller driver information.
- *
- * Since modification of dbi_cs2 involves different clock domain, read the
- * status back to ensure the transition is complete.
- */
-static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
-{
- u32 val;
-
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- val |= DBI_CS2;
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
-
- do {
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- } while (!(val & DBI_CS2));
-}
-
-/**
- * ks_pcie_clear_dbi_mode() - Disable DBI mode
- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
- * PCIe host controller driver information.
- *
- * Since modification of dbi_cs2 involves different clock domain, read the
- * status back to ensure the transition is complete.
- */
-static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
-{
- u32 val;
-
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- val &= ~DBI_CS2;
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
-
- do {
- val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- } while (val & DBI_CS2);
-}
-
static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
u32 val;
@@ -445,44 +463,10 @@ static struct pci_ops ks_child_pcie_ops = {
.write = pci_generic_config_write,
};
-/**
- * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
- * @bus: A pointer to the PCI bus structure.
- *
- * This sets BAR0 to enable inbound access for MSI_IRQ register
- */
-static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
-{
- struct dw_pcie_rp *pp = bus->sysdata;
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
-
- if (!pci_is_root_bus(bus))
- return 0;
-
- /* Configure and set up BAR0 */
- ks_pcie_set_dbi_mode(ks_pcie);
-
- /* Enable BAR0 */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
-
- ks_pcie_clear_dbi_mode(ks_pcie);
-
- /*
- * For BAR0, just setting bus address for inbound writes (MSI) should
- * be sufficient. Use physical address to avoid any conflicts.
- */
- dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
-
- return 0;
-}
-
static struct pci_ops ks_pcie_ops = {
.map_bus = dw_pcie_own_conf_map_bus,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
- .add_bus = ks_pcie_v3_65_add_bus,
};
/**
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
2024-03-26 14:42 ` Siddharth Vadapalli
@ 2024-03-26 23:24 ` Bjorn Helgaas
-1 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2024-03-26 23:24 UTC (permalink / raw
To: Siddharth Vadapalli
Cc: lpieralisi, kw, robh, bhelgaas, manivannan.sadhasivam,
fancer.lancer, u.kleine-koenig, cassel, dlemoal,
yoshihiro.shimoda.uh, linux-pci, linux-kernel, linux-arm-kernel,
srk
On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> In the process of converting .scan_bus() callbacks to .add_bus(), the
> ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> to controller version 3.65a, while the .add_bus() method had been added
> to ks_pcie_ops which is shared between the controller versions 3.65a and
> 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> ks_pcie_v3_65_add_bus() method is applicable to the controller version
> 4.90a which is present in AM654x SoCs.
>
> Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> avoid forward declaration.
If it's possible to split this into two patches (one that strictly
*moves* the code without otherwise changing it, and another that makes
the actual fix), it would be easier to review the fix. It's a pain to
have to compare the code in the old location with that in the new
location.
Bjorn
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
@ 2024-03-26 23:24 ` Bjorn Helgaas
0 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2024-03-26 23:24 UTC (permalink / raw
To: Siddharth Vadapalli
Cc: lpieralisi, kw, robh, bhelgaas, manivannan.sadhasivam,
fancer.lancer, u.kleine-koenig, cassel, dlemoal,
yoshihiro.shimoda.uh, linux-pci, linux-kernel, linux-arm-kernel,
srk
On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> In the process of converting .scan_bus() callbacks to .add_bus(), the
> ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> to controller version 3.65a, while the .add_bus() method had been added
> to ks_pcie_ops which is shared between the controller versions 3.65a and
> 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> ks_pcie_v3_65_add_bus() method is applicable to the controller version
> 4.90a which is present in AM654x SoCs.
>
> Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> avoid forward declaration.
If it's possible to split this into two patches (one that strictly
*moves* the code without otherwise changing it, and another that makes
the actual fix), it would be easier to review the fix. It's a pain to
have to compare the code in the old location with that in the new
location.
Bjorn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
2024-03-26 23:24 ` Bjorn Helgaas
@ 2024-03-27 9:31 ` Siddharth Vadapalli
-1 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-27 9:31 UTC (permalink / raw
To: Bjorn Helgaas
Cc: Siddharth Vadapalli, lpieralisi, kw, robh, bhelgaas,
manivannan.sadhasivam, fancer.lancer, u.kleine-koenig, cassel,
dlemoal, yoshihiro.shimoda.uh, linux-pci, linux-kernel,
linux-arm-kernel, srk
On Tue, Mar 26, 2024 at 06:24:03PM -0500, Bjorn Helgaas wrote:
> On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> > In the process of converting .scan_bus() callbacks to .add_bus(), the
> > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> > The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> > to controller version 3.65a, while the .add_bus() method had been added
> > to ks_pcie_ops which is shared between the controller versions 3.65a and
> > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> > ks_pcie_v3_65_add_bus() method is applicable to the controller version
> > 4.90a which is present in AM654x SoCs.
> >
> > Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> > .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> > 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> > and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> > avoid forward declaration.
>
> If it's possible to split this into two patches (one that strictly
> *moves* the code without otherwise changing it, and another that makes
> the actual fix), it would be easier to review the fix. It's a pain to
> have to compare the code in the old location with that in the new
> location.
Sure. I will do so and post the v7 patch.
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
@ 2024-03-27 9:31 ` Siddharth Vadapalli
0 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-27 9:31 UTC (permalink / raw
To: Bjorn Helgaas
Cc: Siddharth Vadapalli, lpieralisi, kw, robh, bhelgaas,
manivannan.sadhasivam, fancer.lancer, u.kleine-koenig, cassel,
dlemoal, yoshihiro.shimoda.uh, linux-pci, linux-kernel,
linux-arm-kernel, srk
On Tue, Mar 26, 2024 at 06:24:03PM -0500, Bjorn Helgaas wrote:
> On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> > In the process of converting .scan_bus() callbacks to .add_bus(), the
> > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> > The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> > to controller version 3.65a, while the .add_bus() method had been added
> > to ks_pcie_ops which is shared between the controller versions 3.65a and
> > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> > ks_pcie_v3_65_add_bus() method is applicable to the controller version
> > 4.90a which is present in AM654x SoCs.
> >
> > Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> > .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> > 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> > and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> > avoid forward declaration.
>
> If it's possible to split this into two patches (one that strictly
> *moves* the code without otherwise changing it, and another that makes
> the actual fix), it would be easier to review the fix. It's a pain to
> have to compare the code in the old location with that in the new
> location.
Sure. I will do so and post the v7 patch.
Regards,
Siddharth.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
2024-03-27 9:31 ` Siddharth Vadapalli
@ 2024-03-28 8:55 ` Siddharth Vadapalli
-1 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-28 8:55 UTC (permalink / raw
To: Bjorn Helgaas
Cc: Siddharth Vadapalli, lpieralisi, kw, robh, bhelgaas,
manivannan.sadhasivam, fancer.lancer, u.kleine-koenig, cassel,
dlemoal, yoshihiro.shimoda.uh, linux-pci, linux-kernel,
linux-arm-kernel, srk
On Wed, Mar 27, 2024 at 03:01:08PM +0530, Siddharth Vadapalli wrote:
> On Tue, Mar 26, 2024 at 06:24:03PM -0500, Bjorn Helgaas wrote:
> > On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> > > In the process of converting .scan_bus() callbacks to .add_bus(), the
> > > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> > > The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> > > to controller version 3.65a, while the .add_bus() method had been added
> > > to ks_pcie_ops which is shared between the controller versions 3.65a and
> > > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> > > ks_pcie_v3_65_add_bus() method is applicable to the controller version
> > > 4.90a which is present in AM654x SoCs.
> > >
> > > Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> > > .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> > > 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> > > and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> > > avoid forward declaration.
> >
> > If it's possible to split this into two patches (one that strictly
> > *moves* the code without otherwise changing it, and another that makes
> > the actual fix), it would be easier to review the fix. It's a pain to
> > have to compare the code in the old location with that in the new
> > location.
>
> Sure. I will do so and post the v7 patch.
I have posted the v7 series at:
https://lore.kernel.org/r/20240328085041.2916899-1-s-vadapalli@ti.com/
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC
@ 2024-03-28 8:55 ` Siddharth Vadapalli
0 siblings, 0 replies; 8+ messages in thread
From: Siddharth Vadapalli @ 2024-03-28 8:55 UTC (permalink / raw
To: Bjorn Helgaas
Cc: Siddharth Vadapalli, lpieralisi, kw, robh, bhelgaas,
manivannan.sadhasivam, fancer.lancer, u.kleine-koenig, cassel,
dlemoal, yoshihiro.shimoda.uh, linux-pci, linux-kernel,
linux-arm-kernel, srk
On Wed, Mar 27, 2024 at 03:01:08PM +0530, Siddharth Vadapalli wrote:
> On Tue, Mar 26, 2024 at 06:24:03PM -0500, Bjorn Helgaas wrote:
> > On Tue, Mar 26, 2024 at 08:12:58PM +0530, Siddharth Vadapalli wrote:
> > > In the process of converting .scan_bus() callbacks to .add_bus(), the
> > > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus().
> > > The .scan_bus() method belonged to ks_pcie_host_ops which was specific
> > > to controller version 3.65a, while the .add_bus() method had been added
> > > to ks_pcie_ops which is shared between the controller versions 3.65a and
> > > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer
> > > ks_pcie_v3_65_add_bus() method is applicable to the controller version
> > > 4.90a which is present in AM654x SoCs.
> > >
> > > Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the
> > > .msi_init callback "ks_pcie_msi_host_init()" which is specific to the
> > > 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode()
> > > and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to
> > > avoid forward declaration.
> >
> > If it's possible to split this into two patches (one that strictly
> > *moves* the code without otherwise changing it, and another that makes
> > the actual fix), it would be easier to review the fix. It's a pain to
> > have to compare the code in the old location with that in the new
> > location.
>
> Sure. I will do so and post the v7 patch.
I have posted the v7 series at:
https://lore.kernel.org/r/20240328085041.2916899-1-s-vadapalli@ti.com/
Regards,
Siddharth.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-03-28 8:56 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-26 14:42 [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC Siddharth Vadapalli
2024-03-26 14:42 ` Siddharth Vadapalli
2024-03-26 23:24 ` Bjorn Helgaas
2024-03-26 23:24 ` Bjorn Helgaas
2024-03-27 9:31 ` Siddharth Vadapalli
2024-03-27 9:31 ` Siddharth Vadapalli
2024-03-28 8:55 ` Siddharth Vadapalli
2024-03-28 8:55 ` Siddharth Vadapalli
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