From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53A8A12D765; Sun, 24 Mar 2024 22:58:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321133; cv=none; b=h1jv9tQ0sGy9ugeMtRNPKCSG+OvVWH0RREd7s0ZL4n5zOf+GxzsnZ4kwqorSW7uWWLc681JdUZnlArWLKiCJRS6kFvmKfHDvFJyGWg72N5jz3nXEpJumYSYAhdzt2xM/q1kBZ+RT9FaQTL6kwJ+VZMAAo6is6i2WSSsXIuY60Go= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321133; c=relaxed/simple; bh=KBxM9YEfy6MN0Zj5FWWkO4w/8khireT469bIN4a8cqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=icHQdTPGWcDING8u9JhlgDyGpnTnrLGQe6kQ3Ys8shwLsZzmR1ALBEbCMUNDF2J9MkMRNXDdu89i1IeZuofSkpAUARUj6Qy1H0wSnZlxjrfJGdrz2GZ8i7PyCeUxWXZPWGIul/muCW+l7oxgkvh8wWdBq51qb7NUblkS+eLNi90= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FLxvn6mc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FLxvn6mc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 505D3C433A6; Sun, 24 Mar 2024 22:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711321132; bh=KBxM9YEfy6MN0Zj5FWWkO4w/8khireT469bIN4a8cqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FLxvn6mcSG4Wl6jkmSM2Hd4iyNlL7ARJSBgPONNqGkZKFBwl5vH8Y3ITat4rG6cpR kKQ1XqZwe3vNpmB1zNRefBZyEAAK2xF90UNsDe/V8rL1axF4a8jbc7hKTd/hLUJf5e Winnz2E1uo1bq+lV6xGO1zfEjaSNfMTgJmoqd+ZGbO29FFpm28xWi4Q+LMEAdEZR1y J/9qVjzJMJ231Ye2m9ipRscWj0EK9Xslncf9G47lTqDAByB+nzqc+Icw19Sac0Ncp0 G9Sw60jvvnseBrzvn+sgn5i40P73TsnpaO1Y+jEwFrEkgenEZIg4TGSGGTT3lmjyIN UT39dlvLsR+0w== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Subbaraya Sundeep , "David S . Miller" , Sasha Levin Subject: [PATCH 6.7 694/713] octeontx2-af: Use separate handlers for interrupts Date: Sun, 24 Mar 2024 18:47:00 -0400 Message-ID: <20240324224720.1345309-695-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324224720.1345309-1-sashal@kernel.org> References: <20240324224720.1345309-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Subbaraya Sundeep [ Upstream commit 50e60de381c342008c0956fd762e1c26408f372c ] For PF to AF interrupt vector and VF to AF vector same interrupt handler is registered which is causing race condition. When two interrupts are raised to two CPUs at same time then two cores serve same event corrupting the data. Fixes: 7304ac4567bc ("octeontx2-af: Add mailbox IRQ and msg handlers") Signed-off-by: Subbaraya Sundeep Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index d82aa6f12f114..32645aefd5934 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2528,10 +2528,9 @@ static void rvu_queue_work(struct mbox_wq_info *mw, int first, } } -static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) +static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) { struct rvu *rvu = (struct rvu *)rvu_irq; - int vfs = rvu->vfs; u64 intr; intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); @@ -2545,6 +2544,18 @@ static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); + return IRQ_HANDLED; +} + +static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) +{ + struct rvu *rvu = (struct rvu *)rvu_irq; + int vfs = rvu->vfs; + u64 intr; + + /* Sync with mbox memory region */ + rmb(); + /* Handle VF interrupts */ if (vfs > 64) { intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); @@ -2882,7 +2893,7 @@ static int rvu_register_interrupts(struct rvu *rvu) /* Register mailbox interrupt handler */ sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), - rvu_mbox_intr_handler, 0, + rvu_mbox_pf_intr_handler, 0, &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); if (ret) { dev_err(rvu->dev, -- 2.43.0