From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5362E13BC2B; Sun, 24 Mar 2024 22:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711320274; cv=none; b=gKD5elA1lt02Ad8cz+uanXwmsxggUaJiY8JJHv/VzZcn/zLmWTQ+yfmcqvO1j5Y9x/ThaUl9eZGOc2KG1fTwETyCd76ZvJzTgRoaZjDkl2bGBUm+QSYh5GkeiWGckzyWq+5bbVOTR9vjhnpsReL2sqapPPGvGanyrUVGAcrdmo0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711320274; c=relaxed/simple; bh=Vygp2TWkGLy0BzP36pH0XzONz44hyfZcDWMybmTjJT4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BDW/8OhmQns4nNbAyVvVXKO99sVS/h/nO0yLbSyvZ2pWjGADPWcNQtg8DeSwDjvTmVW17j90A6NGGPjtobPclSL/WyXOOcjL3GgSiUvsPNoH5v/9s7bJ9dstu/nmNwxcbHCh9iIic2vKmPuCxgRgIl267YF+kncnbq9W8SU2BWY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TelSwhp9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TelSwhp9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C0B0C433A6; Sun, 24 Mar 2024 22:44:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711320274; bh=Vygp2TWkGLy0BzP36pH0XzONz44hyfZcDWMybmTjJT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TelSwhp9v3kYyF7iBeIr6hD9vhTWcgr9YViBXu1PQGK3hI7Z8o44XuvTAXiWw5vjN TDOSBxV/tVEg5PbsIDnnQZpUgRHsic3l+mta0xpRgd1o/uXiawJpmVPnX2TRigGOdj Lv2kjtxx+LYW7mbxVoeyjbkmiqoav05A/fyi/nGRCo9FA0ilwGsf5nYp3Xfkc3xex/ csUqSIdhHankDmA1hWOg4zsCjR2IBvXk+2XB1YHU19nL0k/oCort6hQbXoVc3bvkbg 11TVTm1QMlVmvNbUNdOfLdTDF2tWSF7mENJmr6+gsaJRURV87tiXaSR6rGL6AMgKn2 YbjrjMPuKlA8w== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ben Wolsieffer , Guenter Roeck , Wim Van Sebroeck , Sasha Levin Subject: [PATCH 6.8 582/715] watchdog: stm32_iwdg: initialize default timeout Date: Sun, 24 Mar 2024 18:32:41 -0400 Message-ID: <20240324223455.1342824-583-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324223455.1342824-1-sashal@kernel.org> References: <20240324223455.1342824-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit From: Ben Wolsieffer [ Upstream commit dbd7c0088b7f44aa0b9276ed3449df075a7b5b54 ] The driver never sets a default timeout value, therefore it is initialized to zero. When CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is enabled, the watchdog is started during probe. The kernel is supposed to automatically ping the watchdog from this point until userspace takes over, but this does not happen if the configured timeout is zero. A zero timeout causes watchdog_need_worker() to return false, so the heartbeat worker does not run and the system therefore resets soon after the driver is probed. This patch fixes this by setting an arbitrary non-zero default timeout. The default could be read from the hardware instead, but I didn't see any reason to add this complexity. This has been tested on an STM32F746. Fixes: 85fdc63fe256 ("drivers: watchdog: stm32_iwdg: set WDOG_HW_RUNNING at probe") Signed-off-by: Ben Wolsieffer Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20240228182723.12855-1-ben.wolsieffer@hefring.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/stm32_iwdg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c index d9fd50df9802c..5404e03876202 100644 --- a/drivers/watchdog/stm32_iwdg.c +++ b/drivers/watchdog/stm32_iwdg.c @@ -20,6 +20,8 @@ #include #include +#define DEFAULT_TIMEOUT 10 + /* IWDG registers */ #define IWDG_KR 0x00 /* Key register */ #define IWDG_PR 0x04 /* Prescaler Register */ @@ -248,6 +250,7 @@ static int stm32_iwdg_probe(struct platform_device *pdev) wdd->parent = dev; wdd->info = &stm32_iwdg_info; wdd->ops = &stm32_iwdg_ops; + wdd->timeout = DEFAULT_TIMEOUT; wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate); wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler * 1000) / wdt->rate; -- 2.43.0