* [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
@ 2024-03-04 22:16 Matt Turner
2024-03-04 22:46 ` ✓ CI.xeBAT: success for " Patchwork
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Matt Turner @ 2024-03-04 22:16 UTC (permalink / raw
To: igt-dev; +Cc: Matt Turner
Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> immediately resolved at startup. In cases where an external function
> call depends needs to be made that may fail if such a call has not
> been initialized yet (PLT-based relocation which is processed later).
> For example calling strlen in an IFUNC resolver built with -Wl,z,now
> may lead to a segfault because the PLT is not yet resolved.
We cannot rely on function calls through the PLT in ifunc resolvers as
the PLT may not have been initialized yet.
In practice, this causes crashes when igt is linked with -Wl,-z,now or
when linked with the mold linker.
To avoid this problem, we do two things:
1. move igt_x86_features() to igt_x86.h so its definition is
available to compilation units that call the function.
2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
igt_x86_features() is inlined.
Bug: https://bugs.gentoo.org/788625
Bug: https://bugs.gentoo.org/925348
Signed-off-by: Matt Turner <mattst88@gmail.com>
---
lib/igt_halffloat.c | 2 +
lib/igt_x86.c | 116 +------------------------------------------
lib/igt_x86.h | 117 +++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 119 insertions(+), 116 deletions(-)
diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
index 5dbe08e01..67d26c225 100644
--- a/lib/igt_halffloat.c
+++ b/lib/igt_halffloat.c
@@ -194,6 +194,7 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num)
f[i] = _half_to_float(h[i]);
}
+__attribute__((flatten))
static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num)
{
if (igt_x86_features() & F16C)
@@ -205,6 +206,7 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned
void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
__attribute__((ifunc("resolve_float_to_half")));
+__attribute__((flatten))
static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num)
{
if (igt_x86_features() & F16C)
diff --git a/lib/igt_x86.c b/lib/igt_x86.c
index 8c102fd13..f103b9820 100644
--- a/lib/igt_x86.c
+++ b/lib/igt_x86.c
@@ -27,14 +27,6 @@
#include "config.h"
-#ifdef HAVE_CPUID_H
-#include <cpuid.h>
-#else
-#define __get_cpuid_max(x, y) 0
-#define __cpuid(level, a, b, c, d) a = b = c = d = 0
-#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
-#endif
-
#include "igt_x86.h"
#include "igt_aux.h"
@@ -49,114 +41,7 @@
* @include: igt_x86.h
*/
-#define BASIC_CPUID 0x0
-#define EXTENDED_CPUID 0x80000000
-
-#ifndef bit_MMX
-#define bit_MMX (1 << 23)
-#endif
-
-#ifndef bit_SSE
-#define bit_SSE (1 << 25)
-#endif
-
-#ifndef bit_SSE2
-#define bit_SSE2 (1 << 26)
-#endif
-
-#ifndef bit_SSE3
-#define bit_SSE3 (1 << 0)
-#endif
-
-#ifndef bit_SSSE3
-#define bit_SSSE3 (1 << 9)
-#endif
-
-#ifndef bit_SSE4_1
-#define bit_SSE4_1 (1 << 19)
-#endif
-
-#ifndef bit_SSE4_2
-#define bit_SSE4_2 (1 << 20)
-#endif
-
-#ifndef bit_OSXSAVE
-#define bit_OSXSAVE (1 << 27)
-#endif
-
-#ifndef bit_AVX
-#define bit_AVX (1 << 28)
-#endif
-
-#ifndef bit_F16C
-#define bit_F16C (1 << 29)
-#endif
-
-#ifndef bit_AVX2
-#define bit_AVX2 (1<<5)
-#endif
-
-#define xgetbv(index,eax,edx) \
- __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
-
-#define has_YMM 0x1
-
#if defined(__x86_64__) || defined(__i386__)
-unsigned igt_x86_features(void)
-{
- unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
- unsigned eax, ebx, ecx, edx;
- unsigned features = 0;
- unsigned extra = 0;
-
- if (max >= 1) {
- __cpuid(1, eax, ebx, ecx, edx);
-
- if (ecx & bit_SSE3)
- features |= SSE3;
-
- if (ecx & bit_SSSE3)
- features |= SSSE3;
-
- if (ecx & bit_SSE4_1)
- features |= SSE4_1;
-
- if (ecx & bit_SSE4_2)
- features |= SSE4_2;
-
- if (ecx & bit_OSXSAVE) {
- unsigned int bv_eax, bv_ecx;
- xgetbv(0, bv_eax, bv_ecx);
- if ((bv_eax & 6) == 6)
- extra |= has_YMM;
- }
-
- if ((extra & has_YMM) && (ecx & bit_AVX))
- features |= AVX;
-
- if (edx & bit_MMX)
- features |= MMX;
-
- if (edx & bit_SSE)
- features |= SSE;
-
- if (edx & bit_SSE2)
- features |= SSE2;
-
- if (ecx & bit_F16C)
- features |= F16C;
- }
-
- if (max >= 7) {
- __cpuid_count(7, 0, eax, ebx, ecx, edx);
-
- if ((extra & has_YMM) && (ebx & bit_AVX2))
- features |= AVX2;
- }
-
- return features;
-}
-
char *igt_x86_features_to_string(unsigned features, char *line)
{
char *ret = line;
@@ -284,6 +169,7 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len)
memcpy(dst, src, len);
}
+__attribute__((flatten))
static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long)
{
if (igt_x86_features() & SSE4_1)
diff --git a/lib/igt_x86.h b/lib/igt_x86.h
index c7b84dec2..1e0195c4b 100644
--- a/lib/igt_x86.h
+++ b/lib/igt_x86.h
@@ -30,6 +30,14 @@
#ifndef IGT_X86_H
#define IGT_X86_H
+#ifdef HAVE_CPUID_H
+#include <cpuid.h>
+#else
+#define __get_cpuid_max(x, y) 0
+#define __cpuid(level, a, b, c, d) a = b = c = d = 0
+#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
+#endif
+
#define MMX 0x1
#define SSE 0x2
#define SSE2 0x4
@@ -42,7 +50,114 @@
#define F16C 0x200
#if defined(__x86_64__) || defined(__i386__)
-unsigned igt_x86_features(void);
+
+#define BASIC_CPUID 0x0
+#define EXTENDED_CPUID 0x80000000
+
+#ifndef bit_MMX
+#define bit_MMX (1 << 23)
+#endif
+
+#ifndef bit_SSE
+#define bit_SSE (1 << 25)
+#endif
+
+#ifndef bit_SSE2
+#define bit_SSE2 (1 << 26)
+#endif
+
+#ifndef bit_SSE3
+#define bit_SSE3 (1 << 0)
+#endif
+
+#ifndef bit_SSSE3
+#define bit_SSSE3 (1 << 9)
+#endif
+
+#ifndef bit_SSE4_1
+#define bit_SSE4_1 (1 << 19)
+#endif
+
+#ifndef bit_SSE4_2
+#define bit_SSE4_2 (1 << 20)
+#endif
+
+#ifndef bit_OSXSAVE
+#define bit_OSXSAVE (1 << 27)
+#endif
+
+#ifndef bit_AVX
+#define bit_AVX (1 << 28)
+#endif
+
+#ifndef bit_F16C
+#define bit_F16C (1 << 29)
+#endif
+
+#ifndef bit_AVX2
+#define bit_AVX2 (1<<5)
+#endif
+
+#define xgetbv(index,eax,edx) \
+ __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
+
+#define has_YMM 0x1
+
+static inline unsigned igt_x86_features(void)
+{
+ unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
+ unsigned eax, ebx, ecx, edx;
+ unsigned features = 0;
+ unsigned extra = 0;
+
+ if (max >= 1) {
+ __cpuid(1, eax, ebx, ecx, edx);
+
+ if (ecx & bit_SSE3)
+ features |= SSE3;
+
+ if (ecx & bit_SSSE3)
+ features |= SSSE3;
+
+ if (ecx & bit_SSE4_1)
+ features |= SSE4_1;
+
+ if (ecx & bit_SSE4_2)
+ features |= SSE4_2;
+
+ if (ecx & bit_OSXSAVE) {
+ unsigned int bv_eax, bv_ecx;
+ xgetbv(0, bv_eax, bv_ecx);
+ if ((bv_eax & 6) == 6)
+ extra |= has_YMM;
+ }
+
+ if ((extra & has_YMM) && (ecx & bit_AVX))
+ features |= AVX;
+
+ if (edx & bit_MMX)
+ features |= MMX;
+
+ if (edx & bit_SSE)
+ features |= SSE;
+
+ if (edx & bit_SSE2)
+ features |= SSE2;
+
+ if (ecx & bit_F16C)
+ features |= F16C;
+ }
+
+ if (max >= 7) {
+ __cpuid_count(7, 0, eax, ebx, ecx, edx);
+
+ if ((extra & has_YMM) && (ebx & bit_AVX2))
+ features |= AVX2;
+ }
+
+ return features;
+}
+
char *igt_x86_features_to_string(unsigned features, char *line);
#else
static inline unsigned igt_x86_features(void)
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ CI.xeBAT: success for lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
@ 2024-03-04 22:46 ` Patchwork
2024-03-04 23:07 ` ✗ Fi.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-04 22:46 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1071 bytes --]
== Series Details ==
Series: lib: Inline igt_x86_features() into ifunc resolvers
URL : https://patchwork.freedesktop.org/series/130696/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7745_BAT -> XEIGTPW_10775_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_7745 -> IGTPW_10775
* Linux: xe-890-1636103d7fa7ca9dedb181d611cd214af79b04d1 -> xe-892-e8bc216572501440efb20e112bb5aa60599f1863
IGTPW_10775: 10775
IGT_7745: 838ad56bf511c1caf56851c661fb5828c0440e3b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-890-1636103d7fa7ca9dedb181d611cd214af79b04d1: 1636103d7fa7ca9dedb181d611cd214af79b04d1
xe-892-e8bc216572501440efb20e112bb5aa60599f1863: e8bc216572501440efb20e112bb5aa60599f1863
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10775/index.html
[-- Attachment #2: Type: text/html, Size: 1630 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.BAT: failure for lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
2024-03-04 22:46 ` ✓ CI.xeBAT: success for " Patchwork
@ 2024-03-04 23:07 ` Patchwork
2024-03-12 15:24 ` [PATCH i-g-t] " Matt Turner
` (6 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-04 23:07 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5172 bytes --]
== Series Details ==
Series: lib: Inline igt_x86_features() into ifunc resolvers
URL : https://patchwork.freedesktop.org/series/130696/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14382 -> IGTPW_10775
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_10775 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_10775, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): bat-kbl-2
Missing (2): fi-snb-2520m bat-arls-3
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10775:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@evict:
- bat-arls-2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-arls-2/igt@i915_selftest@live@evict.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/bat-arls-2/igt@i915_selftest@live@evict.html
Known issues
------------
Here are the changes found in IGTPW_10775 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/bat-kbl-2/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][6] ([fdo#109271]) +39 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#9812])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-sprite-plane-onoff:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#9732]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#3555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/intel/issues/9812
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7745 -> IGTPW_10775
CI-20190529: 20190529
CI_DRM_14382: e8bc216572501440efb20e112bb5aa60599f1863 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10775: 10775
IGT_7745: 838ad56bf511c1caf56851c661fb5828c0440e3b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10775/index.html
[-- Attachment #2: Type: text/html, Size: 6189 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
2024-03-04 22:46 ` ✓ CI.xeBAT: success for " Patchwork
2024-03-04 23:07 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-03-12 15:24 ` Matt Turner
2024-03-13 9:09 ` Zbigniew Kempczyński
` (5 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Matt Turner @ 2024-03-12 15:24 UTC (permalink / raw
To: igt-dev; +Cc: Kamil Konieczny
ping
On Mon, Mar 4, 2024 at 5:18 PM Matt Turner <mattst88@gmail.com> wrote:
>
> Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
>
> > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > immediately resolved at startup. In cases where an external function
> > call depends needs to be made that may fail if such a call has not
> > been initialized yet (PLT-based relocation which is processed later).
> > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > may lead to a segfault because the PLT is not yet resolved.
>
> We cannot rely on function calls through the PLT in ifunc resolvers as
> the PLT may not have been initialized yet.
>
> In practice, this causes crashes when igt is linked with -Wl,-z,now or
> when linked with the mold linker.
>
> To avoid this problem, we do two things:
> 1. move igt_x86_features() to igt_x86.h so its definition is
> available to compilation units that call the function.
> 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> igt_x86_features() is inlined.
>
> Bug: https://bugs.gentoo.org/788625
> Bug: https://bugs.gentoo.org/925348
> Signed-off-by: Matt Turner <mattst88@gmail.com>
> ---
> lib/igt_halffloat.c | 2 +
> lib/igt_x86.c | 116 +------------------------------------------
> lib/igt_x86.h | 117 +++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 119 insertions(+), 116 deletions(-)
>
> diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
> index 5dbe08e01..67d26c225 100644
> --- a/lib/igt_halffloat.c
> +++ b/lib/igt_halffloat.c
> @@ -194,6 +194,7 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num)
> f[i] = _half_to_float(h[i]);
> }
>
> +__attribute__((flatten))
> static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> @@ -205,6 +206,7 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned
> void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
> __attribute__((ifunc("resolve_float_to_half")));
>
> +__attribute__((flatten))
> static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> diff --git a/lib/igt_x86.c b/lib/igt_x86.c
> index 8c102fd13..f103b9820 100644
> --- a/lib/igt_x86.c
> +++ b/lib/igt_x86.c
> @@ -27,14 +27,6 @@
>
> #include "config.h"
>
> -#ifdef HAVE_CPUID_H
> -#include <cpuid.h>
> -#else
> -#define __get_cpuid_max(x, y) 0
> -#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> -#endif
> -
> #include "igt_x86.h"
> #include "igt_aux.h"
>
> @@ -49,114 +41,7 @@
> * @include: igt_x86.h
> */
>
> -#define BASIC_CPUID 0x0
> -#define EXTENDED_CPUID 0x80000000
> -
> -#ifndef bit_MMX
> -#define bit_MMX (1 << 23)
> -#endif
> -
> -#ifndef bit_SSE
> -#define bit_SSE (1 << 25)
> -#endif
> -
> -#ifndef bit_SSE2
> -#define bit_SSE2 (1 << 26)
> -#endif
> -
> -#ifndef bit_SSE3
> -#define bit_SSE3 (1 << 0)
> -#endif
> -
> -#ifndef bit_SSSE3
> -#define bit_SSSE3 (1 << 9)
> -#endif
> -
> -#ifndef bit_SSE4_1
> -#define bit_SSE4_1 (1 << 19)
> -#endif
> -
> -#ifndef bit_SSE4_2
> -#define bit_SSE4_2 (1 << 20)
> -#endif
> -
> -#ifndef bit_OSXSAVE
> -#define bit_OSXSAVE (1 << 27)
> -#endif
> -
> -#ifndef bit_AVX
> -#define bit_AVX (1 << 28)
> -#endif
> -
> -#ifndef bit_F16C
> -#define bit_F16C (1 << 29)
> -#endif
> -
> -#ifndef bit_AVX2
> -#define bit_AVX2 (1<<5)
> -#endif
> -
> -#define xgetbv(index,eax,edx) \
> - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> -
> -#define has_YMM 0x1
> -
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void)
> -{
> - unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> - unsigned eax, ebx, ecx, edx;
> - unsigned features = 0;
> - unsigned extra = 0;
> -
> - if (max >= 1) {
> - __cpuid(1, eax, ebx, ecx, edx);
> -
> - if (ecx & bit_SSE3)
> - features |= SSE3;
> -
> - if (ecx & bit_SSSE3)
> - features |= SSSE3;
> -
> - if (ecx & bit_SSE4_1)
> - features |= SSE4_1;
> -
> - if (ecx & bit_SSE4_2)
> - features |= SSE4_2;
> -
> - if (ecx & bit_OSXSAVE) {
> - unsigned int bv_eax, bv_ecx;
> - xgetbv(0, bv_eax, bv_ecx);
> - if ((bv_eax & 6) == 6)
> - extra |= has_YMM;
> - }
> -
> - if ((extra & has_YMM) && (ecx & bit_AVX))
> - features |= AVX;
> -
> - if (edx & bit_MMX)
> - features |= MMX;
> -
> - if (edx & bit_SSE)
> - features |= SSE;
> -
> - if (edx & bit_SSE2)
> - features |= SSE2;
> -
> - if (ecx & bit_F16C)
> - features |= F16C;
> - }
> -
> - if (max >= 7) {
> - __cpuid_count(7, 0, eax, ebx, ecx, edx);
> -
> - if ((extra & has_YMM) && (ebx & bit_AVX2))
> - features |= AVX2;
> - }
> -
> - return features;
> -}
> -
> char *igt_x86_features_to_string(unsigned features, char *line)
> {
> char *ret = line;
> @@ -284,6 +169,7 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len)
> memcpy(dst, src, len);
> }
>
> +__attribute__((flatten))
> static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long)
> {
> if (igt_x86_features() & SSE4_1)
> diff --git a/lib/igt_x86.h b/lib/igt_x86.h
> index c7b84dec2..1e0195c4b 100644
> --- a/lib/igt_x86.h
> +++ b/lib/igt_x86.h
> @@ -30,6 +30,14 @@
> #ifndef IGT_X86_H
> #define IGT_X86_H
>
> +#ifdef HAVE_CPUID_H
> +#include <cpuid.h>
> +#else
> +#define __get_cpuid_max(x, y) 0
> +#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> +#endif
> +
> #define MMX 0x1
> #define SSE 0x2
> #define SSE2 0x4
> @@ -42,7 +50,114 @@
> #define F16C 0x200
>
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void);
> +
> +#define BASIC_CPUID 0x0
> +#define EXTENDED_CPUID 0x80000000
> +
> +#ifndef bit_MMX
> +#define bit_MMX (1 << 23)
> +#endif
> +
> +#ifndef bit_SSE
> +#define bit_SSE (1 << 25)
> +#endif
> +
> +#ifndef bit_SSE2
> +#define bit_SSE2 (1 << 26)
> +#endif
> +
> +#ifndef bit_SSE3
> +#define bit_SSE3 (1 << 0)
> +#endif
> +
> +#ifndef bit_SSSE3
> +#define bit_SSSE3 (1 << 9)
> +#endif
> +
> +#ifndef bit_SSE4_1
> +#define bit_SSE4_1 (1 << 19)
> +#endif
> +
> +#ifndef bit_SSE4_2
> +#define bit_SSE4_2 (1 << 20)
> +#endif
> +
> +#ifndef bit_OSXSAVE
> +#define bit_OSXSAVE (1 << 27)
> +#endif
> +
> +#ifndef bit_AVX
> +#define bit_AVX (1 << 28)
> +#endif
> +
> +#ifndef bit_F16C
> +#define bit_F16C (1 << 29)
> +#endif
> +
> +#ifndef bit_AVX2
> +#define bit_AVX2 (1<<5)
> +#endif
> +
> +#define xgetbv(index,eax,edx) \
> + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> +
> +#define has_YMM 0x1
> +
> +static inline unsigned igt_x86_features(void)
> +{
> + unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> + unsigned eax, ebx, ecx, edx;
> + unsigned features = 0;
> + unsigned extra = 0;
> +
> + if (max >= 1) {
> + __cpuid(1, eax, ebx, ecx, edx);
> +
> + if (ecx & bit_SSE3)
> + features |= SSE3;
> +
> + if (ecx & bit_SSSE3)
> + features |= SSSE3;
> +
> + if (ecx & bit_SSE4_1)
> + features |= SSE4_1;
> +
> + if (ecx & bit_SSE4_2)
> + features |= SSE4_2;
> +
> + if (ecx & bit_OSXSAVE) {
> + unsigned int bv_eax, bv_ecx;
> + xgetbv(0, bv_eax, bv_ecx);
> + if ((bv_eax & 6) == 6)
> + extra |= has_YMM;
> + }
> +
> + if ((extra & has_YMM) && (ecx & bit_AVX))
> + features |= AVX;
> +
> + if (edx & bit_MMX)
> + features |= MMX;
> +
> + if (edx & bit_SSE)
> + features |= SSE;
> +
> + if (edx & bit_SSE2)
> + features |= SSE2;
> +
> + if (ecx & bit_F16C)
> + features |= F16C;
> + }
> +
> + if (max >= 7) {
> + __cpuid_count(7, 0, eax, ebx, ecx, edx);
> +
> + if ((extra & has_YMM) && (ebx & bit_AVX2))
> + features |= AVX2;
> + }
> +
> + return features;
> +}
> +
> char *igt_x86_features_to_string(unsigned features, char *line);
> #else
> static inline unsigned igt_x86_features(void)
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (2 preceding siblings ...)
2024-03-12 15:24 ` [PATCH i-g-t] " Matt Turner
@ 2024-03-13 9:09 ` Zbigniew Kempczyński
2024-03-21 3:09 ` Matt Turner
2024-03-21 18:17 ` Kamil Konieczny
` (4 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-03-13 9:09 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
>
> > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > immediately resolved at startup. In cases where an external function
> > call depends needs to be made that may fail if such a call has not
> > been initialized yet (PLT-based relocation which is processed later).
> > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > may lead to a segfault because the PLT is not yet resolved.
>
> We cannot rely on function calls through the PLT in ifunc resolvers as
> the PLT may not have been initialized yet.
>
> In practice, this causes crashes when igt is linked with -Wl,-z,now or
> when linked with the mold linker.
>
> To avoid this problem, we do two things:
> 1. move igt_x86_features() to igt_x86.h so its definition is
> available to compilation units that call the function.
> 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> igt_x86_features() is inlined.
>
> Bug: https://bugs.gentoo.org/788625
> Bug: https://bugs.gentoo.org/925348
> Signed-off-by: Matt Turner <mattst88@gmail.com>
Hi.
I started review of your code, but this this touches some linking intrisics
I'm not familiar with yet so I need more time to explore this. I hope
this is not a problem for you.
--
Zbigniew
> ---
> lib/igt_halffloat.c | 2 +
> lib/igt_x86.c | 116 +------------------------------------------
> lib/igt_x86.h | 117 +++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 119 insertions(+), 116 deletions(-)
>
> diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
> index 5dbe08e01..67d26c225 100644
> --- a/lib/igt_halffloat.c
> +++ b/lib/igt_halffloat.c
> @@ -194,6 +194,7 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num)
> f[i] = _half_to_float(h[i]);
> }
>
> +__attribute__((flatten))
> static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> @@ -205,6 +206,7 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned
> void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
> __attribute__((ifunc("resolve_float_to_half")));
>
> +__attribute__((flatten))
> static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> diff --git a/lib/igt_x86.c b/lib/igt_x86.c
> index 8c102fd13..f103b9820 100644
> --- a/lib/igt_x86.c
> +++ b/lib/igt_x86.c
> @@ -27,14 +27,6 @@
>
> #include "config.h"
>
> -#ifdef HAVE_CPUID_H
> -#include <cpuid.h>
> -#else
> -#define __get_cpuid_max(x, y) 0
> -#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> -#endif
> -
> #include "igt_x86.h"
> #include "igt_aux.h"
>
> @@ -49,114 +41,7 @@
> * @include: igt_x86.h
> */
>
> -#define BASIC_CPUID 0x0
> -#define EXTENDED_CPUID 0x80000000
> -
> -#ifndef bit_MMX
> -#define bit_MMX (1 << 23)
> -#endif
> -
> -#ifndef bit_SSE
> -#define bit_SSE (1 << 25)
> -#endif
> -
> -#ifndef bit_SSE2
> -#define bit_SSE2 (1 << 26)
> -#endif
> -
> -#ifndef bit_SSE3
> -#define bit_SSE3 (1 << 0)
> -#endif
> -
> -#ifndef bit_SSSE3
> -#define bit_SSSE3 (1 << 9)
> -#endif
> -
> -#ifndef bit_SSE4_1
> -#define bit_SSE4_1 (1 << 19)
> -#endif
> -
> -#ifndef bit_SSE4_2
> -#define bit_SSE4_2 (1 << 20)
> -#endif
> -
> -#ifndef bit_OSXSAVE
> -#define bit_OSXSAVE (1 << 27)
> -#endif
> -
> -#ifndef bit_AVX
> -#define bit_AVX (1 << 28)
> -#endif
> -
> -#ifndef bit_F16C
> -#define bit_F16C (1 << 29)
> -#endif
> -
> -#ifndef bit_AVX2
> -#define bit_AVX2 (1<<5)
> -#endif
> -
> -#define xgetbv(index,eax,edx) \
> - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> -
> -#define has_YMM 0x1
> -
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void)
> -{
> - unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> - unsigned eax, ebx, ecx, edx;
> - unsigned features = 0;
> - unsigned extra = 0;
> -
> - if (max >= 1) {
> - __cpuid(1, eax, ebx, ecx, edx);
> -
> - if (ecx & bit_SSE3)
> - features |= SSE3;
> -
> - if (ecx & bit_SSSE3)
> - features |= SSSE3;
> -
> - if (ecx & bit_SSE4_1)
> - features |= SSE4_1;
> -
> - if (ecx & bit_SSE4_2)
> - features |= SSE4_2;
> -
> - if (ecx & bit_OSXSAVE) {
> - unsigned int bv_eax, bv_ecx;
> - xgetbv(0, bv_eax, bv_ecx);
> - if ((bv_eax & 6) == 6)
> - extra |= has_YMM;
> - }
> -
> - if ((extra & has_YMM) && (ecx & bit_AVX))
> - features |= AVX;
> -
> - if (edx & bit_MMX)
> - features |= MMX;
> -
> - if (edx & bit_SSE)
> - features |= SSE;
> -
> - if (edx & bit_SSE2)
> - features |= SSE2;
> -
> - if (ecx & bit_F16C)
> - features |= F16C;
> - }
> -
> - if (max >= 7) {
> - __cpuid_count(7, 0, eax, ebx, ecx, edx);
> -
> - if ((extra & has_YMM) && (ebx & bit_AVX2))
> - features |= AVX2;
> - }
> -
> - return features;
> -}
> -
> char *igt_x86_features_to_string(unsigned features, char *line)
> {
> char *ret = line;
> @@ -284,6 +169,7 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len)
> memcpy(dst, src, len);
> }
>
> +__attribute__((flatten))
> static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long)
> {
> if (igt_x86_features() & SSE4_1)
> diff --git a/lib/igt_x86.h b/lib/igt_x86.h
> index c7b84dec2..1e0195c4b 100644
> --- a/lib/igt_x86.h
> +++ b/lib/igt_x86.h
> @@ -30,6 +30,14 @@
> #ifndef IGT_X86_H
> #define IGT_X86_H
>
> +#ifdef HAVE_CPUID_H
> +#include <cpuid.h>
> +#else
> +#define __get_cpuid_max(x, y) 0
> +#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> +#endif
> +
> #define MMX 0x1
> #define SSE 0x2
> #define SSE2 0x4
> @@ -42,7 +50,114 @@
> #define F16C 0x200
>
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void);
> +
> +#define BASIC_CPUID 0x0
> +#define EXTENDED_CPUID 0x80000000
> +
> +#ifndef bit_MMX
> +#define bit_MMX (1 << 23)
> +#endif
> +
> +#ifndef bit_SSE
> +#define bit_SSE (1 << 25)
> +#endif
> +
> +#ifndef bit_SSE2
> +#define bit_SSE2 (1 << 26)
> +#endif
> +
> +#ifndef bit_SSE3
> +#define bit_SSE3 (1 << 0)
> +#endif
> +
> +#ifndef bit_SSSE3
> +#define bit_SSSE3 (1 << 9)
> +#endif
> +
> +#ifndef bit_SSE4_1
> +#define bit_SSE4_1 (1 << 19)
> +#endif
> +
> +#ifndef bit_SSE4_2
> +#define bit_SSE4_2 (1 << 20)
> +#endif
> +
> +#ifndef bit_OSXSAVE
> +#define bit_OSXSAVE (1 << 27)
> +#endif
> +
> +#ifndef bit_AVX
> +#define bit_AVX (1 << 28)
> +#endif
> +
> +#ifndef bit_F16C
> +#define bit_F16C (1 << 29)
> +#endif
> +
> +#ifndef bit_AVX2
> +#define bit_AVX2 (1<<5)
> +#endif
> +
> +#define xgetbv(index,eax,edx) \
> + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> +
> +#define has_YMM 0x1
> +
> +static inline unsigned igt_x86_features(void)
> +{
> + unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> + unsigned eax, ebx, ecx, edx;
> + unsigned features = 0;
> + unsigned extra = 0;
> +
> + if (max >= 1) {
> + __cpuid(1, eax, ebx, ecx, edx);
> +
> + if (ecx & bit_SSE3)
> + features |= SSE3;
> +
> + if (ecx & bit_SSSE3)
> + features |= SSSE3;
> +
> + if (ecx & bit_SSE4_1)
> + features |= SSE4_1;
> +
> + if (ecx & bit_SSE4_2)
> + features |= SSE4_2;
> +
> + if (ecx & bit_OSXSAVE) {
> + unsigned int bv_eax, bv_ecx;
> + xgetbv(0, bv_eax, bv_ecx);
> + if ((bv_eax & 6) == 6)
> + extra |= has_YMM;
> + }
> +
> + if ((extra & has_YMM) && (ecx & bit_AVX))
> + features |= AVX;
> +
> + if (edx & bit_MMX)
> + features |= MMX;
> +
> + if (edx & bit_SSE)
> + features |= SSE;
> +
> + if (edx & bit_SSE2)
> + features |= SSE2;
> +
> + if (ecx & bit_F16C)
> + features |= F16C;
> + }
> +
> + if (max >= 7) {
> + __cpuid_count(7, 0, eax, ebx, ecx, edx);
> +
> + if ((extra & has_YMM) && (ebx & bit_AVX2))
> + features |= AVX2;
> + }
> +
> + return features;
> +}
> +
> char *igt_x86_features_to_string(unsigned features, char *line);
> #else
> static inline unsigned igt_x86_features(void)
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-13 9:09 ` Zbigniew Kempczyński
@ 2024-03-21 3:09 ` Matt Turner
2024-03-21 7:03 ` Zbigniew Kempczyński
0 siblings, 1 reply; 18+ messages in thread
From: Matt Turner @ 2024-03-21 3:09 UTC (permalink / raw
To: Zbigniew Kempczyński; +Cc: igt-dev
On Wed, Mar 13, 2024 at 5:09 AM Zbigniew Kempczyński
<zbigniew.kempczynski@intel.com> wrote:
>
> On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> >
> > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > immediately resolved at startup. In cases where an external function
> > > call depends needs to be made that may fail if such a call has not
> > > been initialized yet (PLT-based relocation which is processed later).
> > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > may lead to a segfault because the PLT is not yet resolved.
> >
> > We cannot rely on function calls through the PLT in ifunc resolvers as
> > the PLT may not have been initialized yet.
> >
> > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > when linked with the mold linker.
> >
> > To avoid this problem, we do two things:
> > 1. move igt_x86_features() to igt_x86.h so its definition is
> > available to compilation units that call the function.
> > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > igt_x86_features() is inlined.
> >
> > Bug: https://bugs.gentoo.org/788625
> > Bug: https://bugs.gentoo.org/925348
> > Signed-off-by: Matt Turner <mattst88@gmail.com>
>
> Hi.
>
> I started review of your code, but this this touches some linking intrisics
> I'm not familiar with yet so I need more time to explore this. I hope
> this is not a problem for you.
Do you have any questions I can answer? I tried my best to explain the
how and the why of the change in the commit message.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 3:09 ` Matt Turner
@ 2024-03-21 7:03 ` Zbigniew Kempczyński
2024-03-21 15:02 ` Matt Turner
0 siblings, 1 reply; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-03-21 7:03 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
On Wed, Mar 20, 2024 at 11:09:11PM -0400, Matt Turner wrote:
> On Wed, Mar 13, 2024 at 5:09 AM Zbigniew Kempczyński
> <zbigniew.kempczynski@intel.com> wrote:
> >
> > On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> > > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> > >
> > > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > > immediately resolved at startup. In cases where an external function
> > > > call depends needs to be made that may fail if such a call has not
> > > > been initialized yet (PLT-based relocation which is processed later).
> > > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > > may lead to a segfault because the PLT is not yet resolved.
> > >
> > > We cannot rely on function calls through the PLT in ifunc resolvers as
> > > the PLT may not have been initialized yet.
> > >
> > > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > > when linked with the mold linker.
> > >
> > > To avoid this problem, we do two things:
> > > 1. move igt_x86_features() to igt_x86.h so its definition is
> > > available to compilation units that call the function.
> > > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > > igt_x86_features() is inlined.
> > >
> > > Bug: https://bugs.gentoo.org/788625
> > > Bug: https://bugs.gentoo.org/925348
> > > Signed-off-by: Matt Turner <mattst88@gmail.com>
> >
> > Hi.
> >
> > I started review of your code, but this this touches some linking intrisics
> > I'm not familiar with yet so I need more time to explore this. I hope
> > this is not a problem for you.
>
> Do you have any questions I can answer? I tried my best to explain the
> how and the why of the change in the commit message.
I wanted to prepare better for the discussion - I extracted few
functions on which I'm reproducing segv issue when LD_BIND_NOW=1 is set.
I confirm, GOT doesn't contain valid function addresses so jump goes
to nowhere. I'm pretty sure intel_vbd_decode with LD_BIND_NOW=1 only
reveals the problem, but it lays within linker logic:
# LD_BIND_NOW=1 LD_PRELOAD=./build/lib/libigt.so.0 LD_DEBUG=all ps
ps definitely doesn't call igt_half_to_float() which in turn calls
unresolved igt_x86_features@plt. It looks linker first tries to
call all ifunc's to establish addresses, unfortunately it is doing
this before filling GOT. Backtrace shows we're still in _start
from /lib64/ld-linux-x86-64.so.2 so we even didn't get a chance
to get to the main().
Before I'll give you my ack (I still want to experiment with this
one more day) - may you explain what for you need to bind relocs
immediately? This is slower than lazy binding as it resolves all
PLTs instead resolving only required symbols.
I'm sorry this review takes so much time. Due to work duties other
tasks have higher prio.
--
Zbigniew
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 7:03 ` Zbigniew Kempczyński
@ 2024-03-21 15:02 ` Matt Turner
2024-03-21 15:33 ` Zbigniew Kempczyński
2024-03-21 18:11 ` Kamil Konieczny
0 siblings, 2 replies; 18+ messages in thread
From: Matt Turner @ 2024-03-21 15:02 UTC (permalink / raw
To: Zbigniew Kempczyński; +Cc: igt-dev
On Thu, Mar 21, 2024 at 3:03 AM Zbigniew Kempczyński
<zbigniew.kempczynski@intel.com> wrote:
>
> On Wed, Mar 20, 2024 at 11:09:11PM -0400, Matt Turner wrote:
> > On Wed, Mar 13, 2024 at 5:09 AM Zbigniew Kempczyński
> > <zbigniew.kempczynski@intel.com> wrote:
> > >
> > > On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> > > > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> > > >
> > > > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > > > immediately resolved at startup. In cases where an external function
> > > > > call depends needs to be made that may fail if such a call has not
> > > > > been initialized yet (PLT-based relocation which is processed later).
> > > > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > > > may lead to a segfault because the PLT is not yet resolved.
> > > >
> > > > We cannot rely on function calls through the PLT in ifunc resolvers as
> > > > the PLT may not have been initialized yet.
> > > >
> > > > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > > > when linked with the mold linker.
> > > >
> > > > To avoid this problem, we do two things:
> > > > 1. move igt_x86_features() to igt_x86.h so its definition is
> > > > available to compilation units that call the function.
> > > > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > > > igt_x86_features() is inlined.
> > > >
> > > > Bug: https://bugs.gentoo.org/788625
> > > > Bug: https://bugs.gentoo.org/925348
> > > > Signed-off-by: Matt Turner <mattst88@gmail.com>
> > >
> > > Hi.
> > >
> > > I started review of your code, but this this touches some linking intrisics
> > > I'm not familiar with yet so I need more time to explore this. I hope
> > > this is not a problem for you.
> >
> > Do you have any questions I can answer? I tried my best to explain the
> > how and the why of the change in the commit message.
>
> I wanted to prepare better for the discussion - I extracted few
> functions on which I'm reproducing segv issue when LD_BIND_NOW=1 is set.
> I confirm, GOT doesn't contain valid function addresses so jump goes
> to nowhere. I'm pretty sure intel_vbd_decode with LD_BIND_NOW=1 only
> reveals the problem, but it lays within linker logic:
>
> # LD_BIND_NOW=1 LD_PRELOAD=./build/lib/libigt.so.0 LD_DEBUG=all ps
>
> ps definitely doesn't call igt_half_to_float() which in turn calls
> unresolved igt_x86_features@plt. It looks linker first tries to
> call all ifunc's to establish addresses, unfortunately it is doing
> this before filling GOT. Backtrace shows we're still in _start
> from /lib64/ld-linux-x86-64.so.2 so we even didn't get a chance
> to get to the main().
Right, exactly. I believe ifuncs are resolved regardless of whether
they're used.
> Before I'll give you my ack (I still want to experiment with this
> one more day) - may you explain what for you need to bind relocs
> immediately? This is slower than lazy binding as it resolves all
> PLTs instead resolving only required symbols.
Gentoo/Hardened uses `-z now` to improve security. By binding upfront,
the loader can mark the GOT as read-only for a security enhancement.
See https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
Apparently (according to that page) `-z now` will become the default
in standard Gentoo profiles very soon.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 15:02 ` Matt Turner
@ 2024-03-21 15:33 ` Zbigniew Kempczyński
2024-03-21 18:11 ` Kamil Konieczny
1 sibling, 0 replies; 18+ messages in thread
From: Zbigniew Kempczyński @ 2024-03-21 15:33 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
On Thu, Mar 21, 2024 at 11:02:16AM -0400, Matt Turner wrote:
> On Thu, Mar 21, 2024 at 3:03 AM Zbigniew Kempczyński
> <zbigniew.kempczynski@intel.com> wrote:
> >
> > On Wed, Mar 20, 2024 at 11:09:11PM -0400, Matt Turner wrote:
> > > On Wed, Mar 13, 2024 at 5:09 AM Zbigniew Kempczyński
> > > <zbigniew.kempczynski@intel.com> wrote:
> > > >
> > > > On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> > > > > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> > > > >
> > > > > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > > > > immediately resolved at startup. In cases where an external function
> > > > > > call depends needs to be made that may fail if such a call has not
> > > > > > been initialized yet (PLT-based relocation which is processed later).
> > > > > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > > > > may lead to a segfault because the PLT is not yet resolved.
> > > > >
> > > > > We cannot rely on function calls through the PLT in ifunc resolvers as
> > > > > the PLT may not have been initialized yet.
> > > > >
> > > > > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > > > > when linked with the mold linker.
> > > > >
> > > > > To avoid this problem, we do two things:
> > > > > 1. move igt_x86_features() to igt_x86.h so its definition is
> > > > > available to compilation units that call the function.
> > > > > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > > > > igt_x86_features() is inlined.
> > > > >
> > > > > Bug: https://bugs.gentoo.org/788625
> > > > > Bug: https://bugs.gentoo.org/925348
> > > > > Signed-off-by: Matt Turner <mattst88@gmail.com>
> > > >
> > > > Hi.
> > > >
> > > > I started review of your code, but this this touches some linking intrisics
> > > > I'm not familiar with yet so I need more time to explore this. I hope
> > > > this is not a problem for you.
> > >
> > > Do you have any questions I can answer? I tried my best to explain the
> > > how and the why of the change in the commit message.
> >
> > I wanted to prepare better for the discussion - I extracted few
> > functions on which I'm reproducing segv issue when LD_BIND_NOW=1 is set.
> > I confirm, GOT doesn't contain valid function addresses so jump goes
> > to nowhere. I'm pretty sure intel_vbd_decode with LD_BIND_NOW=1 only
> > reveals the problem, but it lays within linker logic:
> >
> > # LD_BIND_NOW=1 LD_PRELOAD=./build/lib/libigt.so.0 LD_DEBUG=all ps
> >
> > ps definitely doesn't call igt_half_to_float() which in turn calls
> > unresolved igt_x86_features@plt. It looks linker first tries to
> > call all ifunc's to establish addresses, unfortunately it is doing
> > this before filling GOT. Backtrace shows we're still in _start
> > from /lib64/ld-linux-x86-64.so.2 so we even didn't get a chance
> > to get to the main().
>
> Right, exactly. I believe ifuncs are resolved regardless of whether
> they're used.
>
> > Before I'll give you my ack (I still want to experiment with this
> > one more day) - may you explain what for you need to bind relocs
> > immediately? This is slower than lazy binding as it resolves all
> > PLTs instead resolving only required symbols.
>
> Gentoo/Hardened uses `-z now` to improve security. By binding upfront,
> the loader can mark the GOT as read-only for a security enhancement.
> See https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
>
> Apparently (according to that page) `-z now` will become the default
> in standard Gentoo profiles very soon.
I'm not going to block this change. igt_x86_features() is used only in
few places so there's not a problem to flattenize it. So from me:
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 15:02 ` Matt Turner
2024-03-21 15:33 ` Zbigniew Kempczyński
@ 2024-03-21 18:11 ` Kamil Konieczny
1 sibling, 0 replies; 18+ messages in thread
From: Kamil Konieczny @ 2024-03-21 18:11 UTC (permalink / raw
To: igt-dev; +Cc: Matt Turner, Zbigniew Kempczyński
Hi Matt,
On 2024-03-21 at 11:02:16 -0400, Matt Turner wrote:
> On Thu, Mar 21, 2024 at 3:03 AM Zbigniew Kempczyński
> <zbigniew.kempczynski@intel.com> wrote:
> >
> > On Wed, Mar 20, 2024 at 11:09:11PM -0400, Matt Turner wrote:
> > > On Wed, Mar 13, 2024 at 5:09 AM Zbigniew Kempczyński
> > > <zbigniew.kempczynski@intel.com> wrote:
> > > >
> > > > On Mon, Mar 04, 2024 at 05:16:40PM -0500, Matt Turner wrote:
> > > > > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> > > > >
> > > > > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > > > > immediately resolved at startup. In cases where an external function
> > > > > > call depends needs to be made that may fail if such a call has not
> > > > > > been initialized yet (PLT-based relocation which is processed later).
> > > > > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > > > > may lead to a segfault because the PLT is not yet resolved.
> > > > >
> > > > > We cannot rely on function calls through the PLT in ifunc resolvers as
> > > > > the PLT may not have been initialized yet.
> > > > >
> > > > > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > > > > when linked with the mold linker.
> > > > >
> > > > > To avoid this problem, we do two things:
> > > > > 1. move igt_x86_features() to igt_x86.h so its definition is
> > > > > available to compilation units that call the function.
> > > > > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > > > > igt_x86_features() is inlined.
> > > > >
> > > > > Bug: https://bugs.gentoo.org/788625
> > > > > Bug: https://bugs.gentoo.org/925348
> > > > > Signed-off-by: Matt Turner <mattst88@gmail.com>
> > > >
> > > > Hi.
> > > >
> > > > I started review of your code, but this this touches some linking intrisics
> > > > I'm not familiar with yet so I need more time to explore this. I hope
> > > > this is not a problem for you.
> > >
> > > Do you have any questions I can answer? I tried my best to explain the
> > > how and the why of the change in the commit message.
> >
> > I wanted to prepare better for the discussion - I extracted few
> > functions on which I'm reproducing segv issue when LD_BIND_NOW=1 is set.
> > I confirm, GOT doesn't contain valid function addresses so jump goes
> > to nowhere. I'm pretty sure intel_vbd_decode with LD_BIND_NOW=1 only
> > reveals the problem, but it lays within linker logic:
> >
> > # LD_BIND_NOW=1 LD_PRELOAD=./build/lib/libigt.so.0 LD_DEBUG=all ps
> >
> > ps definitely doesn't call igt_half_to_float() which in turn calls
> > unresolved igt_x86_features@plt. It looks linker first tries to
> > call all ifunc's to establish addresses, unfortunately it is doing
> > this before filling GOT. Backtrace shows we're still in _start
> > from /lib64/ld-linux-x86-64.so.2 so we even didn't get a chance
> > to get to the main().
>
> Right, exactly. I believe ifuncs are resolved regardless of whether
> they're used.
>
> > Before I'll give you my ack (I still want to experiment with this
> > one more day) - may you explain what for you need to bind relocs
> > immediately? This is slower than lazy binding as it resolves all
> > PLTs instead resolving only required symbols.
>
> Gentoo/Hardened uses `-z now` to improve security. By binding upfront,
> the loader can mark the GOT as read-only for a security enhancement.
> See https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
Please add this to your commit description as 'why we need this'.
Also see my small nit for a patch.
Regards,
Kamil
>
> Apparently (according to that page) `-z now` will become the default
> in standard Gentoo profiles very soon.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (3 preceding siblings ...)
2024-03-13 9:09 ` Zbigniew Kempczyński
@ 2024-03-21 18:17 ` Kamil Konieczny
2024-03-21 18:31 ` Matt Turner
2024-03-21 18:41 ` [PATCH v2] " Matt Turner
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Kamil Konieczny @ 2024-03-21 18:17 UTC (permalink / raw
To: igt-dev; +Cc: Matt Turner, Zbigniew Kempczyński
Hi Matt,
On 2024-03-04 at 17:16:40 -0500, Matt Turner wrote:
> Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
>
> > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > immediately resolved at startup. In cases where an external function
> > call depends needs to be made that may fail if such a call has not
> > been initialized yet (PLT-based relocation which is processed later).
> > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > may lead to a segfault because the PLT is not yet resolved.
>
Add here (or at begin of patch?) that this is needed for Gentoo/Hardened
security improving.
> We cannot rely on function calls through the PLT in ifunc resolvers as
> the PLT may not have been initialized yet.
>
> In practice, this causes crashes when igt is linked with -Wl,-z,now or
> when linked with the mold linker.
>
> To avoid this problem, we do two things:
> 1. move igt_x86_features() to igt_x86.h so its definition is
> available to compilation units that call the function.
> 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> igt_x86_features() is inlined.
>
You could also mension that this is called from only a few places
so it should not cause big code grow.
> Bug: https://bugs.gentoo.org/788625
> Bug: https://bugs.gentoo.org/925348
> Signed-off-by: Matt Turner <mattst88@gmail.com>
> ---
> lib/igt_halffloat.c | 2 +
> lib/igt_x86.c | 116 +------------------------------------------
> lib/igt_x86.h | 117 +++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 119 insertions(+), 116 deletions(-)
>
> diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
> index 5dbe08e01..67d26c225 100644
> --- a/lib/igt_halffloat.c
> +++ b/lib/igt_halffloat.c
> @@ -194,6 +194,7 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num)
> f[i] = _half_to_float(h[i]);
> }
>
> +__attribute__((flatten))
> static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> @@ -205,6 +206,7 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned
> void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
> __attribute__((ifunc("resolve_float_to_half")));
>
Add comment here why this is needed.
With this I see no blockers as you already got r-b from Zbigniew.
Regards,
Kamil
> +__attribute__((flatten))
> static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num)
> {
> if (igt_x86_features() & F16C)
> diff --git a/lib/igt_x86.c b/lib/igt_x86.c
> index 8c102fd13..f103b9820 100644
> --- a/lib/igt_x86.c
> +++ b/lib/igt_x86.c
> @@ -27,14 +27,6 @@
>
> #include "config.h"
>
> -#ifdef HAVE_CPUID_H
> -#include <cpuid.h>
> -#else
> -#define __get_cpuid_max(x, y) 0
> -#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> -#endif
> -
> #include "igt_x86.h"
> #include "igt_aux.h"
>
> @@ -49,114 +41,7 @@
> * @include: igt_x86.h
> */
>
> -#define BASIC_CPUID 0x0
> -#define EXTENDED_CPUID 0x80000000
> -
> -#ifndef bit_MMX
> -#define bit_MMX (1 << 23)
> -#endif
> -
> -#ifndef bit_SSE
> -#define bit_SSE (1 << 25)
> -#endif
> -
> -#ifndef bit_SSE2
> -#define bit_SSE2 (1 << 26)
> -#endif
> -
> -#ifndef bit_SSE3
> -#define bit_SSE3 (1 << 0)
> -#endif
> -
> -#ifndef bit_SSSE3
> -#define bit_SSSE3 (1 << 9)
> -#endif
> -
> -#ifndef bit_SSE4_1
> -#define bit_SSE4_1 (1 << 19)
> -#endif
> -
> -#ifndef bit_SSE4_2
> -#define bit_SSE4_2 (1 << 20)
> -#endif
> -
> -#ifndef bit_OSXSAVE
> -#define bit_OSXSAVE (1 << 27)
> -#endif
> -
> -#ifndef bit_AVX
> -#define bit_AVX (1 << 28)
> -#endif
> -
> -#ifndef bit_F16C
> -#define bit_F16C (1 << 29)
> -#endif
> -
> -#ifndef bit_AVX2
> -#define bit_AVX2 (1<<5)
> -#endif
> -
> -#define xgetbv(index,eax,edx) \
> - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> -
> -#define has_YMM 0x1
> -
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void)
> -{
> - unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> - unsigned eax, ebx, ecx, edx;
> - unsigned features = 0;
> - unsigned extra = 0;
> -
> - if (max >= 1) {
> - __cpuid(1, eax, ebx, ecx, edx);
> -
> - if (ecx & bit_SSE3)
> - features |= SSE3;
> -
> - if (ecx & bit_SSSE3)
> - features |= SSSE3;
> -
> - if (ecx & bit_SSE4_1)
> - features |= SSE4_1;
> -
> - if (ecx & bit_SSE4_2)
> - features |= SSE4_2;
> -
> - if (ecx & bit_OSXSAVE) {
> - unsigned int bv_eax, bv_ecx;
> - xgetbv(0, bv_eax, bv_ecx);
> - if ((bv_eax & 6) == 6)
> - extra |= has_YMM;
> - }
> -
> - if ((extra & has_YMM) && (ecx & bit_AVX))
> - features |= AVX;
> -
> - if (edx & bit_MMX)
> - features |= MMX;
> -
> - if (edx & bit_SSE)
> - features |= SSE;
> -
> - if (edx & bit_SSE2)
> - features |= SSE2;
> -
> - if (ecx & bit_F16C)
> - features |= F16C;
> - }
> -
> - if (max >= 7) {
> - __cpuid_count(7, 0, eax, ebx, ecx, edx);
> -
> - if ((extra & has_YMM) && (ebx & bit_AVX2))
> - features |= AVX2;
> - }
> -
> - return features;
> -}
> -
> char *igt_x86_features_to_string(unsigned features, char *line)
> {
> char *ret = line;
> @@ -284,6 +169,7 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len)
> memcpy(dst, src, len);
> }
>
> +__attribute__((flatten))
> static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long)
> {
> if (igt_x86_features() & SSE4_1)
> diff --git a/lib/igt_x86.h b/lib/igt_x86.h
> index c7b84dec2..1e0195c4b 100644
> --- a/lib/igt_x86.h
> +++ b/lib/igt_x86.h
> @@ -30,6 +30,14 @@
> #ifndef IGT_X86_H
> #define IGT_X86_H
>
> +#ifdef HAVE_CPUID_H
> +#include <cpuid.h>
> +#else
> +#define __get_cpuid_max(x, y) 0
> +#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> +#endif
> +
> #define MMX 0x1
> #define SSE 0x2
> #define SSE2 0x4
> @@ -42,7 +50,114 @@
> #define F16C 0x200
>
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void);
> +
> +#define BASIC_CPUID 0x0
> +#define EXTENDED_CPUID 0x80000000
> +
> +#ifndef bit_MMX
> +#define bit_MMX (1 << 23)
> +#endif
> +
> +#ifndef bit_SSE
> +#define bit_SSE (1 << 25)
> +#endif
> +
> +#ifndef bit_SSE2
> +#define bit_SSE2 (1 << 26)
> +#endif
> +
> +#ifndef bit_SSE3
> +#define bit_SSE3 (1 << 0)
> +#endif
> +
> +#ifndef bit_SSSE3
> +#define bit_SSSE3 (1 << 9)
> +#endif
> +
> +#ifndef bit_SSE4_1
> +#define bit_SSE4_1 (1 << 19)
> +#endif
> +
> +#ifndef bit_SSE4_2
> +#define bit_SSE4_2 (1 << 20)
> +#endif
> +
> +#ifndef bit_OSXSAVE
> +#define bit_OSXSAVE (1 << 27)
> +#endif
> +
> +#ifndef bit_AVX
> +#define bit_AVX (1 << 28)
> +#endif
> +
> +#ifndef bit_F16C
> +#define bit_F16C (1 << 29)
> +#endif
> +
> +#ifndef bit_AVX2
> +#define bit_AVX2 (1<<5)
> +#endif
> +
> +#define xgetbv(index,eax,edx) \
> + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> +
> +#define has_YMM 0x1
> +
> +static inline unsigned igt_x86_features(void)
> +{
> + unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> + unsigned eax, ebx, ecx, edx;
> + unsigned features = 0;
> + unsigned extra = 0;
> +
> + if (max >= 1) {
> + __cpuid(1, eax, ebx, ecx, edx);
> +
> + if (ecx & bit_SSE3)
> + features |= SSE3;
> +
> + if (ecx & bit_SSSE3)
> + features |= SSSE3;
> +
> + if (ecx & bit_SSE4_1)
> + features |= SSE4_1;
> +
> + if (ecx & bit_SSE4_2)
> + features |= SSE4_2;
> +
> + if (ecx & bit_OSXSAVE) {
> + unsigned int bv_eax, bv_ecx;
> + xgetbv(0, bv_eax, bv_ecx);
> + if ((bv_eax & 6) == 6)
> + extra |= has_YMM;
> + }
> +
> + if ((extra & has_YMM) && (ecx & bit_AVX))
> + features |= AVX;
> +
> + if (edx & bit_MMX)
> + features |= MMX;
> +
> + if (edx & bit_SSE)
> + features |= SSE;
> +
> + if (edx & bit_SSE2)
> + features |= SSE2;
> +
> + if (ecx & bit_F16C)
> + features |= F16C;
> + }
> +
> + if (max >= 7) {
> + __cpuid_count(7, 0, eax, ebx, ecx, edx);
> +
> + if ((extra & has_YMM) && (ebx & bit_AVX2))
> + features |= AVX2;
> + }
> +
> + return features;
> +}
> +
> char *igt_x86_features_to_string(unsigned features, char *line);
> #else
> static inline unsigned igt_x86_features(void)
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 18:17 ` Kamil Konieczny
@ 2024-03-21 18:31 ` Matt Turner
0 siblings, 0 replies; 18+ messages in thread
From: Matt Turner @ 2024-03-21 18:31 UTC (permalink / raw
To: Kamil Konieczny, igt-dev, Matt Turner, Zbigniew Kempczyński
On Thu, Mar 21, 2024 at 2:18 PM Kamil Konieczny
<kamil.konieczny@linux.intel.com> wrote:
>
> Hi Matt,
> On 2024-03-04 at 17:16:40 -0500, Matt Turner wrote:
> > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> >
> > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > immediately resolved at startup. In cases where an external function
> > > call depends needs to be made that may fail if such a call has not
> > > been initialized yet (PLT-based relocation which is processed later).
> > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > may lead to a segfault because the PLT is not yet resolved.
> >
>
> Add here (or at begin of patch?) that this is needed for Gentoo/Hardened
> security improving.
Thanks. I'll address the comments and send a v2.
To be clear, it's not *just* Gentoo/Hardened that wants this. E.g.
Fedora switched to -z now by default ages ago (F23 according to
https://fedoraproject.org/wiki/Changes/Harden_All_Packages) and
they've been overriding it for igt specifically since then. See
https://src.fedoraproject.org/rpms/igt-gpu-tools/blob/rawhide/f/igt-gpu-tools.spec#_116
Aside: they also appear to have a script to make git snapshots, likely
indicating that they'd like to have more frequent releases of igt
(like Gentoo would as well).
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (4 preceding siblings ...)
2024-03-21 18:17 ` Kamil Konieczny
@ 2024-03-21 18:41 ` Matt Turner
2024-03-25 17:15 ` Matt Turner
2024-03-21 19:45 ` ✓ Fi.CI.BAT: success for lib: Inline igt_x86_features() into ifunc resolvers (rev2) Patchwork
` (2 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Matt Turner @ 2024-03-21 18:41 UTC (permalink / raw
To: igt-dev; +Cc: Zbigniew Kempczyński, Kamil Konieczny, Matt Turner
Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> immediately resolved at startup. In cases where an external function
> call depends needs to be made that may fail if such a call has not
> been initialized yet (PLT-based relocation which is processed later).
> For example calling strlen in an IFUNC resolver built with -Wl,z,now
> may lead to a segfault because the PLT is not yet resolved.
We cannot rely on function calls through the PLT in ifunc resolvers as
the PLT may not have been initialized yet.
In practice, this causes crashes when igt is linked with -Wl,-z,now or
when linked with the mold linker.
To avoid this problem, we do two things:
1. move igt_x86_features() to igt_x86.h so its definition is
available to compilation units that call the function.
2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
igt_x86_features() is inlined. Since this function is only called
from a few places it does not significantly increase binary size
to inline it.
Linux distros (at least Fedora since v23, Gentoo/Hardened, soon standard
Gentoo) use `-Wl,-z now` to improve security. By binding upfront, the
loader can mark the GOT as read-only for a security enhancement. See
https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
Bug: https://bugs.gentoo.org/788625
Bug: https://bugs.gentoo.org/925348
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
---
lib/igt_halffloat.c | 8 +++
lib/igt_x86.c | 119 ++------------------------------------------
lib/igt_x86.h | 117 ++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 128 insertions(+), 116 deletions(-)
diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
index 5dbe08e01..560952d20 100644
--- a/lib/igt_halffloat.c
+++ b/lib/igt_halffloat.c
@@ -194,6 +194,10 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num)
f[i] = _half_to_float(h[i]);
}
+/* The PLT is not initialized when ifunc resolvers run, so all external
+ * functions must be inlined with __attribute__((flatten)).
+ */
+__attribute__((flatten))
static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num)
{
if (igt_x86_features() & F16C)
@@ -205,6 +209,10 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned
void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
__attribute__((ifunc("resolve_float_to_half")));
+/* The PLT is not initialized when ifunc resolvers run, so all external
+ * functions must be inlined with __attribute__((flatten)).
+ */
+__attribute__((flatten))
static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num)
{
if (igt_x86_features() & F16C)
diff --git a/lib/igt_x86.c b/lib/igt_x86.c
index 8c102fd13..f60568be5 100644
--- a/lib/igt_x86.c
+++ b/lib/igt_x86.c
@@ -27,14 +27,6 @@
#include "config.h"
-#ifdef HAVE_CPUID_H
-#include <cpuid.h>
-#else
-#define __get_cpuid_max(x, y) 0
-#define __cpuid(level, a, b, c, d) a = b = c = d = 0
-#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
-#endif
-
#include "igt_x86.h"
#include "igt_aux.h"
@@ -49,114 +41,7 @@
* @include: igt_x86.h
*/
-#define BASIC_CPUID 0x0
-#define EXTENDED_CPUID 0x80000000
-
-#ifndef bit_MMX
-#define bit_MMX (1 << 23)
-#endif
-
-#ifndef bit_SSE
-#define bit_SSE (1 << 25)
-#endif
-
-#ifndef bit_SSE2
-#define bit_SSE2 (1 << 26)
-#endif
-
-#ifndef bit_SSE3
-#define bit_SSE3 (1 << 0)
-#endif
-
-#ifndef bit_SSSE3
-#define bit_SSSE3 (1 << 9)
-#endif
-
-#ifndef bit_SSE4_1
-#define bit_SSE4_1 (1 << 19)
-#endif
-
-#ifndef bit_SSE4_2
-#define bit_SSE4_2 (1 << 20)
-#endif
-
-#ifndef bit_OSXSAVE
-#define bit_OSXSAVE (1 << 27)
-#endif
-
-#ifndef bit_AVX
-#define bit_AVX (1 << 28)
-#endif
-
-#ifndef bit_F16C
-#define bit_F16C (1 << 29)
-#endif
-
-#ifndef bit_AVX2
-#define bit_AVX2 (1<<5)
-#endif
-
-#define xgetbv(index,eax,edx) \
- __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
-
-#define has_YMM 0x1
-
#if defined(__x86_64__) || defined(__i386__)
-unsigned igt_x86_features(void)
-{
- unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
- unsigned eax, ebx, ecx, edx;
- unsigned features = 0;
- unsigned extra = 0;
-
- if (max >= 1) {
- __cpuid(1, eax, ebx, ecx, edx);
-
- if (ecx & bit_SSE3)
- features |= SSE3;
-
- if (ecx & bit_SSSE3)
- features |= SSSE3;
-
- if (ecx & bit_SSE4_1)
- features |= SSE4_1;
-
- if (ecx & bit_SSE4_2)
- features |= SSE4_2;
-
- if (ecx & bit_OSXSAVE) {
- unsigned int bv_eax, bv_ecx;
- xgetbv(0, bv_eax, bv_ecx);
- if ((bv_eax & 6) == 6)
- extra |= has_YMM;
- }
-
- if ((extra & has_YMM) && (ecx & bit_AVX))
- features |= AVX;
-
- if (edx & bit_MMX)
- features |= MMX;
-
- if (edx & bit_SSE)
- features |= SSE;
-
- if (edx & bit_SSE2)
- features |= SSE2;
-
- if (ecx & bit_F16C)
- features |= F16C;
- }
-
- if (max >= 7) {
- __cpuid_count(7, 0, eax, ebx, ecx, edx);
-
- if ((extra & has_YMM) && (ebx & bit_AVX2))
- features |= AVX2;
- }
-
- return features;
-}
-
char *igt_x86_features_to_string(unsigned features, char *line)
{
char *ret = line;
@@ -284,6 +169,10 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len)
memcpy(dst, src, len);
}
+/* The PLT is not initialized when ifunc resolvers run, so all external
+ * functions must be inlined with __attribute__((flatten)).
+ */
+__attribute__((flatten))
static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long)
{
if (igt_x86_features() & SSE4_1)
diff --git a/lib/igt_x86.h b/lib/igt_x86.h
index c7b84dec2..1e0195c4b 100644
--- a/lib/igt_x86.h
+++ b/lib/igt_x86.h
@@ -30,6 +30,14 @@
#ifndef IGT_X86_H
#define IGT_X86_H
+#ifdef HAVE_CPUID_H
+#include <cpuid.h>
+#else
+#define __get_cpuid_max(x, y) 0
+#define __cpuid(level, a, b, c, d) a = b = c = d = 0
+#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
+#endif
+
#define MMX 0x1
#define SSE 0x2
#define SSE2 0x4
@@ -42,7 +50,114 @@
#define F16C 0x200
#if defined(__x86_64__) || defined(__i386__)
-unsigned igt_x86_features(void);
+
+#define BASIC_CPUID 0x0
+#define EXTENDED_CPUID 0x80000000
+
+#ifndef bit_MMX
+#define bit_MMX (1 << 23)
+#endif
+
+#ifndef bit_SSE
+#define bit_SSE (1 << 25)
+#endif
+
+#ifndef bit_SSE2
+#define bit_SSE2 (1 << 26)
+#endif
+
+#ifndef bit_SSE3
+#define bit_SSE3 (1 << 0)
+#endif
+
+#ifndef bit_SSSE3
+#define bit_SSSE3 (1 << 9)
+#endif
+
+#ifndef bit_SSE4_1
+#define bit_SSE4_1 (1 << 19)
+#endif
+
+#ifndef bit_SSE4_2
+#define bit_SSE4_2 (1 << 20)
+#endif
+
+#ifndef bit_OSXSAVE
+#define bit_OSXSAVE (1 << 27)
+#endif
+
+#ifndef bit_AVX
+#define bit_AVX (1 << 28)
+#endif
+
+#ifndef bit_F16C
+#define bit_F16C (1 << 29)
+#endif
+
+#ifndef bit_AVX2
+#define bit_AVX2 (1<<5)
+#endif
+
+#define xgetbv(index,eax,edx) \
+ __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
+
+#define has_YMM 0x1
+
+static inline unsigned igt_x86_features(void)
+{
+ unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
+ unsigned eax, ebx, ecx, edx;
+ unsigned features = 0;
+ unsigned extra = 0;
+
+ if (max >= 1) {
+ __cpuid(1, eax, ebx, ecx, edx);
+
+ if (ecx & bit_SSE3)
+ features |= SSE3;
+
+ if (ecx & bit_SSSE3)
+ features |= SSSE3;
+
+ if (ecx & bit_SSE4_1)
+ features |= SSE4_1;
+
+ if (ecx & bit_SSE4_2)
+ features |= SSE4_2;
+
+ if (ecx & bit_OSXSAVE) {
+ unsigned int bv_eax, bv_ecx;
+ xgetbv(0, bv_eax, bv_ecx);
+ if ((bv_eax & 6) == 6)
+ extra |= has_YMM;
+ }
+
+ if ((extra & has_YMM) && (ecx & bit_AVX))
+ features |= AVX;
+
+ if (edx & bit_MMX)
+ features |= MMX;
+
+ if (edx & bit_SSE)
+ features |= SSE;
+
+ if (edx & bit_SSE2)
+ features |= SSE2;
+
+ if (ecx & bit_F16C)
+ features |= F16C;
+ }
+
+ if (max >= 7) {
+ __cpuid_count(7, 0, eax, ebx, ecx, edx);
+
+ if ((extra & has_YMM) && (ebx & bit_AVX2))
+ features |= AVX2;
+ }
+
+ return features;
+}
+
char *igt_x86_features_to_string(unsigned features, char *line);
#else
static inline unsigned igt_x86_features(void)
--
2.43.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for lib: Inline igt_x86_features() into ifunc resolvers (rev2)
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (5 preceding siblings ...)
2024-03-21 18:41 ` [PATCH v2] " Matt Turner
@ 2024-03-21 19:45 ` Patchwork
2024-03-21 19:51 ` ✓ CI.xeBAT: " Patchwork
2024-03-22 12:20 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-21 19:45 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2776 bytes --]
== Series Details ==
Series: lib: Inline igt_x86_features() into ifunc resolvers (rev2)
URL : https://patchwork.freedesktop.org/series/130696/
State : success
== Summary ==
CI Bug Log - changes from IGT_7775 -> IGTPW_10876
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
Participating hosts (40 -> 35)
------------------------------
Missing (5): fi-tgl-1115g4 fi-apl-guc fi-snb-2520m fi-kbl-8809g bat-jsl-1
Known issues
------------
Here are the changes found in IGTPW_10876 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- bat-rpls-3: [PASS][1] -> [DMESG-WARN][2] ([i915#5591])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [FAIL][3] ([i915#10378]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
- bat-dg2-14: [FAIL][5] ([i915#10378]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/bat-dg2-14/igt@gem_lmem_swapping@basic@lmem0.html
* igt@i915_selftest@live@hangcheck:
- bat-adlm-1: [ABORT][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/bat-adlm-1/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/bat-adlm-1/igt@i915_selftest@live@hangcheck.html
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7775 -> IGTPW_10876
CI-20190529: 20190529
CI_DRM_14463: 0cd99ca612f004f19c35f4966a584f0a729bbc31 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10876: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
IGT_7775: 0ee4074685c1e184f2d3612ea6eb4d126f9a2e23 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@kms_big_joiner@2x-modeset
-igt@kms_big_joiner@basic-force-joiner
-igt@kms_big_joiner@invalid-modeset-force-joiner
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
[-- Attachment #2: Type: text/html, Size: 3511 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ CI.xeBAT: success for lib: Inline igt_x86_features() into ifunc resolvers (rev2)
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (6 preceding siblings ...)
2024-03-21 19:45 ` ✓ Fi.CI.BAT: success for lib: Inline igt_x86_features() into ifunc resolvers (rev2) Patchwork
@ 2024-03-21 19:51 ` Patchwork
2024-03-22 12:20 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-21 19:51 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
== Series Details ==
Series: lib: Inline igt_x86_features() into ifunc resolvers (rev2)
URL : https://patchwork.freedesktop.org/series/130696/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7775_BAT -> XEIGTPW_10876_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_7775 -> IGTPW_10876
IGTPW_10876: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
IGT_7775: 0ee4074685c1e184f2d3612ea6eb4d126f9a2e23 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-972-0cd99ca612f004f19c35f4966a584f0a729bbc31: 0cd99ca612f004f19c35f4966a584f0a729bbc31
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10876/index.html
[-- Attachment #2: Type: text/html, Size: 1479 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for lib: Inline igt_x86_features() into ifunc resolvers (rev2)
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
` (7 preceding siblings ...)
2024-03-21 19:51 ` ✓ CI.xeBAT: " Patchwork
@ 2024-03-22 12:20 ` Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-03-22 12:20 UTC (permalink / raw
To: Matt Turner; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 89615 bytes --]
== Series Details ==
Series: lib: Inline igt_x86_features() into ifunc resolvers (rev2)
URL : https://patchwork.freedesktop.org/series/130696/
State : failure
== Summary ==
CI Bug Log - changes from IGT_7775_full -> IGTPW_10876_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_10876_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_10876_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_10876_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_gttfill@engines@bcs0:
- shard-dg2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-7/igt@gem_exec_gttfill@engines@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@gem_exec_gttfill@engines@bcs0.html
* igt@gem_userptr_blits@coherency-sync:
- shard-snb: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb7/igt@gem_userptr_blits@coherency-sync.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb7/igt@gem_userptr_blits@coherency-sync.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html
* igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4:
- shard-dg1: [PASS][6] -> [FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-15/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-15/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4.html
Known issues
------------
Here are the changes found in IGTPW_10876_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8411])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#6230])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@api_intel_bb@crc32.html
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#8411])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-mtlp: NOTRUN -> [SKIP][11] ([i915#9318])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@cold-reset-bound:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#7701])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#7701])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#8414])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@drm_fdinfo@all-busy-idle-check-all.html
* igt@drm_fdinfo@isolation@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#8414]) +6 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@drm_fdinfo@isolation@rcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#8414]) +10 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][17] -> [FAIL][18] ([i915#7742])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: NOTRUN -> [FAIL][19] ([i915#7742])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#3281]) +14 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#3936])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@gem_busy@semaphore.html
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#3936])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@gem_busy@semaphore.html
* igt@gem_ccs@block-copy-compressed:
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#3555] / [i915#9323])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#9323])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#3555] / [i915#9323])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu: NOTRUN -> [SKIP][26] ([i915#9323])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#6335])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: NOTRUN -> [FAIL][28] ([i915#6268])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#8555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][30] ([i915#8555])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#5882]) +9 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#280])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: [PASS][33] -> [FAIL][34] ([i915#5784]) +1 other test fail
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-13/igt@gem_eio@unwedge-stress.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4771])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@hog:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#4812]) +2 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@gem_exec_balancer@hog.html
* igt@gem_exec_balancer@sliced:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4812])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#6334])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4473] / [i915#4771])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][40] ([i915#2842]) +1 other test fail
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#3539] / [i915#4852]) +4 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_exec_fair@basic-none-share.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [PASS][42] -> [FAIL][43] ([i915#2842]) +1 other test fail
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][44] ([i915#2842]) +6 other tests fail
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: NOTRUN -> [FAIL][45] ([i915#2876])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@submit67:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4812])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#3711])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#3539] / [i915#4852]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#7697])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_reloc@basic-cpu-wc:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#3281]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@gem_exec_reloc@basic-cpu-wc.html
* igt@gem_exec_reloc@basic-gtt-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#3281]) +5 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-wc-active.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#3281]) +7 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4537] / [i915#4812])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-10/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#4860])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4860]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#4613] / [i915#7582])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-4/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@basic:
- shard-tglu: NOTRUN -> [SKIP][57] ([i915#4613]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-4/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#4613]) +4 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-4/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][59] ([i915#4613]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk5/igt@gem_lmem_swapping@random-engines.html
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4613]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_mmap@bad-size:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4083]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@gem_mmap@bad-size.html
* igt@gem_mmap@short-mmap:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4083]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@gem_mmap@short-mmap.html
* igt@gem_mmap_gtt@big-bo-tiledy:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#4077]) +5 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@gem_mmap_gtt@big-bo-tiledy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#4077]) +4 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_gtt@hang:
- shard-dg1: NOTRUN -> [SKIP][65] ([i915#4077]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_wc@invalid-flags:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#4083]) +4 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gem_mmap_wc@invalid-flags.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#3282]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#3282]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@gem_partial_pwrite_pread@write.html
* igt@gem_pread@bench:
- shard-rkl: NOTRUN -> [SKIP][69] ([i915#3282]) +6 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_pread@bench.html
* igt@gem_pxp@display-protected-crc:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@gem_pxp@display-protected-crc.html
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4270]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#4270]) +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#4270]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_readwrite@read-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#3282]) +6 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@gem_readwrite@read-bad-handle.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#8428]) +4 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#5190] / [i915#8428]) +7 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-10/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4079])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@gem_set_tiling_vs_gtt.html
* igt@gem_softpin@evict-snoop:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#4885])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@gem_softpin@evict-snoop.html
* igt@gem_unfence_active_buffers:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#4879])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@gem_unfence_active_buffers.html
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#4879])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-glk: NOTRUN -> [SKIP][81] ([i915#3323])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk8/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglu: NOTRUN -> [SKIP][82] ([i915#3297])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-9/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#3297]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3297]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-5/igt@gem_userptr_blits@unsync-unmap.html
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#3297])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen9_exec_parse@batch-without-end:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#2856]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglu: NOTRUN -> [SKIP][87] ([i915#2527] / [i915#2856]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-out:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#2527]) +3 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#2856]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@gen9_exec_parse@secure-batches.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#2527]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@resize-bar:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#6412])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#8399])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#6621])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds@gt0:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#8925])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@i915_pm_rps@thresholds@gt0.html
* igt@i915_pm_sseu@full-enable:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#8437])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@i915_pm_sseu@full-enable.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][96] -> [FAIL][97] ([i915#10031])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4212])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#4212])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#8709]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#8709]) +11 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html
* igt@kms_async_flips@invalid-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6228])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#9531])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#9531])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#1769] / [i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][106] ([i915#1769])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#4538] / [i915#5286]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#5286]) +5 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#5286])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#5286]) +2 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#3638]) +2 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][112] +15 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-3/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#4538] / [i915#5190]) +8 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: [PASS][114] -> [FAIL][115] ([i915#3743]) +2 other tests fail
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#6187]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][117] +11 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#4538]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#10307] / [i915#10434]) +2 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#10278])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
- shard-tglu: NOTRUN -> [SKIP][121] ([i915#10278])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#10278])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#6095]) +73 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#10307]) +152 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][125] ([i915#6095]) +19 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-8/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#6095]) +39 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#6095]) +59 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#3742])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#3742])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-6/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_audio@dp-audio:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#7828]) +5 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][131] +21 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#7828]) +9 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#7828]) +1 other test skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#7828]) +9 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#7828]) +2 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_color@deep-color:
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#3555]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#7118] / [i915#9424])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_content_protection@atomic.html
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#7118] / [i915#9424])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content-type-change:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#9424])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_content_protection@content-type-change.html
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#9424])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#3299])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#3299])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@uevent:
- shard-tglu: NOTRUN -> [SKIP][143] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#3359])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3555]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#8814]) +3 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#3359]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu: NOTRUN -> [SKIP][148] ([i915#3359])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-6/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#3555]) +5 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#9809]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#4213])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#9067])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-6/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#4103] / [i915#4213])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#4103])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#4103] / [i915#4213])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_cursor_legacy@torture-move@pipe-a:
- shard-dg1: [PASS][156] -> [DMESG-WARN][157] ([i915#10166])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-16/igt@kms_cursor_legacy@torture-move@pipe-a.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@kms_cursor_legacy@torture-move@pipe-a.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#9833])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#9227])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#9723])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][161] ([i915#3555] / [i915#8827])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#8588])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@kms_display_modes@mst-extended-mode-negative.html
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#8588])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#1257])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3840] / [i915#9688])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-3/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc:
- shard-mtlp: NOTRUN -> [SKIP][166] ([i915#3555] / [i915#3840])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_dsc@dsc-with-bpc.html
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3840])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#3840])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#3840] / [i915#9053])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][170] ([i915#3955]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#1839]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_feature_discovery@display-3x.html
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#1839]) +1 other test skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@psr2:
- shard-tglu: NOTRUN -> [SKIP][173] ([i915#658])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@kms_feature_discovery@psr2.html
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#658])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3637]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
- shard-snb: [PASS][176] -> [FAIL][177] ([i915#2122]) +1 other test fail
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-rkl: NOTRUN -> [SKIP][178] +47 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-tglu: NOTRUN -> [SKIP][179] ([i915#3637]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#9934]) +2 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@plain-flip-ts-check@b-hdmi-a1:
- shard-rkl: NOTRUN -> [FAIL][181] ([i915#2122])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_flip@plain-flip-ts-check@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][182] ([i915#2587] / [i915#2672]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#2672]) +1 other test skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#2587] / [i915#2672]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#2672]) +4 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#3555] / [i915#8810])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#2672]) +4 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#2672] / [i915#3555]) +2 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#5274])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#1825]) +19 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: [PASS][191] -> [SKIP][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
- shard-tglu: NOTRUN -> [SKIP][193] +44 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][194] ([i915#8708]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-dg2: NOTRUN -> [FAIL][195] ([i915#6880])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][196] ([i915#8708]) +2 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][197] ([i915#5439])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#10055])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3458])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#3023]) +22 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#3458]) +18 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][202] +286 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#8708]) +16 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#1825]) +41 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#5354]) +35 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg1: NOTRUN -> [SKIP][206] ([i915#3555] / [i915#8228])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-15/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8228]) +3 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@legacy:
- shard-tglu: NOTRUN -> [SKIP][208] ([i915#6301])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-6/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][209] ([i915#7862]) +1 other test fail
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk8/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][210] ([i915#4573]) +1 other test fail
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk8/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#3555] / [i915#8821])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-10/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#5354] / [i915#9423])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#9423]) +3 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#9423]) +7 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#5176]) +3 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][216] ([i915#9423]) +3 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c-hdmi-a-3.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][217] ([i915#9423]) +7 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-4/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#5235]) +5 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#5235]) +3 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][220] ([i915#3555] / [i915#5235]) +1 other test skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#5235]) +3 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#5235] / [i915#9423]) +15 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][223] ([i915#5354])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#9685]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#5978])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#9685])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#4281])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][228] ([i915#9340])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: NOTRUN -> [SKIP][229] ([i915#8430])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#9519]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][231] -> [SKIP][232] ([i915#9519]) +3 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
- shard-rkl: [PASS][233] -> [SKIP][234] ([i915#9519])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#6524] / [i915#6805])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg1: NOTRUN -> [SKIP][236] ([i915#6524])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-15/igt@kms_prime@basic-crc-vgem.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#9808]) +3 other tests skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf@psr2-pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area:
- shard-snb: NOTRUN -> [SKIP][238] +76 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb1/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][239] ([i915#9683])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-tglu: NOTRUN -> [SKIP][240] ([i915#9683])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#9683])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-5/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#9673] / [i915#9732]) +2 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@pr-primary-render:
- shard-mtlp: NOTRUN -> [SKIP][243] ([i915#9688]) +8 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@kms_psr@pr-primary-render.html
* igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#4077] / [i915#9688])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-6/igt@kms_psr@psr-primary-mmap-gtt@edp-1.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][245] ([i915#9732]) +5 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr2-primary-blt:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#9732]) +16 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@kms_psr@psr2-primary-blt.html
* igt@kms_psr@psr2-primary-render:
- shard-tglu: NOTRUN -> [SKIP][247] ([i915#9732]) +9 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-2/igt@kms_psr@psr2-primary-render.html
* igt@kms_psr@psr2-sprite-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#9732]) +20 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_psr@psr2-sprite-mmap-cpu.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#4235])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-5/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][250] ([i915#5289])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#5190]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][252] ([i915#4235]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#4235] / [i915#5190])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-mtlp: NOTRUN -> [SKIP][254] ([i915#3555] / [i915#8809]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][255] -> [FAIL][256] ([IGT#2])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#8623])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][258] ([i915#9196])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: NOTRUN -> [SKIP][259] ([i915#9906]) +1 other test skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-rkl: NOTRUN -> [SKIP][260] ([i915#2437])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][261] ([i915#2437] / [i915#9412])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#2437] / [i915#9412])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#2437] / [i915#9412])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-5/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@global-sseu-config-invalid:
- shard-mtlp: NOTRUN -> [SKIP][264] ([i915#7387])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@perf@global-sseu-config-invalid.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][265] ([i915#2435])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: NOTRUN -> [FAIL][266] ([i915#4349]) +3 other tests fail
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@cpu-hotplug:
- shard-rkl: NOTRUN -> [SKIP][267] ([i915#8850])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-7/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-tglu: NOTRUN -> [SKIP][268] ([i915#8516])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@perf_pmu@rc6-all-gts.html
- shard-rkl: NOTRUN -> [SKIP][269] ([i915#8516])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-2/igt@perf_pmu@rc6-all-gts.html
* igt@prime_vgem@basic-fence-read:
- shard-mtlp: NOTRUN -> [SKIP][270] ([i915#3708])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-1/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][271] ([i915#3708])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-4/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: NOTRUN -> [SKIP][272] ([i915#9917])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][273] ([i915#9779])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_job_submission@array-job-submission:
- shard-dg2: NOTRUN -> [SKIP][274] ([i915#2575]) +8 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-2/igt@v3d/v3d_job_submission@array-job-submission.html
* igt@v3d/v3d_job_submission@multiple-singlesync-to-multisync:
- shard-mtlp: NOTRUN -> [SKIP][275] ([i915#2575]) +8 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-7/igt@v3d/v3d_job_submission@multiple-singlesync-to-multisync.html
* igt@v3d/v3d_submit_csd@job-perfmon:
- shard-dg1: NOTRUN -> [SKIP][276] ([i915#2575]) +2 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@v3d/v3d_submit_csd@job-perfmon.html
* igt@vc4/vc4_perfmon@create-perfmon-0:
- shard-tglu: NOTRUN -> [SKIP][277] ([i915#2575]) +11 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-8/igt@vc4/vc4_perfmon@create-perfmon-0.html
* igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem:
- shard-mtlp: NOTRUN -> [SKIP][278] ([i915#7711]) +2 other tests skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-8/igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-dg2: NOTRUN -> [SKIP][279] ([i915#7711]) +8 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-8/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
- shard-rkl: NOTRUN -> [SKIP][280] ([i915#7711]) +6 other tests skip
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
* igt@vc4/vc4_tiling@get-bad-flags:
- shard-dg1: NOTRUN -> [SKIP][281] ([i915#7711]) +1 other test skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-16/igt@vc4/vc4_tiling@get-bad-flags.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][282] ([i915#7742]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][284] ([i915#2842]) -> [PASS][285] +1 other test pass
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-tglu-3/igt@gem_exec_fair@basic-pace@rcs0.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-dg1: [DMESG-WARN][286] ([i915#4391] / [i915#4423]) -> [PASS][287] +1 other test pass
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-15/igt@gem_lmem_evict@dontneed-evict-race.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg2: [FAIL][288] ([i915#10378]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-3/igt@gem_lmem_swapping@heavy-random@lmem0.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [INCOMPLETE][290] ([i915#9820]) -> [PASS][291]
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0:
- shard-dg1: [FAIL][292] ([i915#3591]) -> [PASS][293] +2 other tests pass
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [FAIL][294] ([i915#5138]) -> [PASS][295]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][296] ([i915#2122]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-dg2: [FAIL][298] ([i915#6880]) -> [PASS][299] +1 other test pass
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-snb: [SKIP][300] -> [PASS][301] +6 other tests pass
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][302] ([i915#9519]) -> [PASS][303] +3 other tests pass
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-rkl: [INCOMPLETE][304] ([i915#8875] / [i915#9569]) -> [PASS][305]
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [FAIL][306] ([i915#9196]) -> [PASS][307]
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][308] ([i915#9196]) -> [PASS][309]
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-tglu-4/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
#### Warnings ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: [INCOMPLETE][310] ([i915#9408] / [i915#9618]) -> [ABORT][311] ([i915#9618])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-17/igt@device_reset@unbind-reset-rebind.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@device_reset@unbind-reset-rebind.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][312] ([i915#10131] / [i915#9697]) -> [ABORT][313] ([i915#10131] / [i915#9820])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [INCOMPLETE][314] ([i915#9820] / [i915#9849]) -> [ABORT][315] ([i915#9820])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-5/igt@i915_module_load@reload-with-fault-injection.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-dg1: [SKIP][316] ([i915#2587] / [i915#2672] / [i915#4423]) -> [SKIP][317] ([i915#2587] / [i915#2672])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][318] ([i915#4070] / [i915#4816]) -> [SKIP][319] ([i915#4816])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][320] ([i915#3361]) -> [FAIL][321] ([i915#9295])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_psr@fbc-psr-primary-mmap-gtt:
- shard-dg2: [SKIP][322] ([i915#9732]) -> [SKIP][323] ([i915#9673] / [i915#9732]) +10 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-5/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-11/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
- shard-dg2: [SKIP][324] ([i915#9673] / [i915#9732]) -> [SKIP][325] ([i915#9732]) +4 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-6/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg1: [SKIP][326] ([i915#4423] / [i915#9732]) -> [SKIP][327] ([i915#9732]) +1 other test skip
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg1-15/igt@kms_psr@psr-cursor-mmap-cpu.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg1-18/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][328] ([i915#9100]) -> [FAIL][329] ([i915#7484])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
* igt@runner@aborted:
- shard-glk: [FAIL][330] -> [FAIL][331] ([i915#10291])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7775/shard-glk9/igt@runner@aborted.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/shard-glk2/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10031]: https://gitlab.freedesktop.org/drm/intel/issues/10031
[i915#10055]: https://gitlab.freedesktop.org/drm/intel/issues/10055
[i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
[i915#10166]: https://gitlab.freedesktop.org/drm/intel/issues/10166
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10291]: https://gitlab.freedesktop.org/drm/intel/issues/10291
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3711]: https://gitlab.freedesktop.org/drm/intel/issues/3711
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
[i915#8437]: https://gitlab.freedesktop.org/drm/intel/issues/8437
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8827]: https://gitlab.freedesktop.org/drm/intel/issues/8827
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
[i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
[i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
[i915#9408]: https://gitlab.freedesktop.org/drm/intel/issues/9408
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
[i915#9569]: https://gitlab.freedesktop.org/drm/intel/issues/9569
[i915#9618]: https://gitlab.freedesktop.org/drm/intel/issues/9618
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9697]: https://gitlab.freedesktop.org/drm/intel/issues/9697
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
[i915#9808]: https://gitlab.freedesktop.org/drm/intel/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7775 -> IGTPW_10876
CI-20190529: 20190529
CI_DRM_14463: 0cd99ca612f004f19c35f4966a584f0a729bbc31 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_10876: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
IGT_7775: 0ee4074685c1e184f2d3612ea6eb4d126f9a2e23 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_10876/index.html
[-- Attachment #2: Type: text/html, Size: 109145 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-21 18:41 ` [PATCH v2] " Matt Turner
@ 2024-03-25 17:15 ` Matt Turner
2024-03-26 17:36 ` Kamil Konieczny
0 siblings, 1 reply; 18+ messages in thread
From: Matt Turner @ 2024-03-25 17:15 UTC (permalink / raw
To: Development mailing list for IGT GPU Tools
Cc: Zbigniew Kempczyński, Kamil Konieczny
[-- Attachment #1: Type: text/plain, Size: 10586 bytes --]
Please commit me :)
On Thu, Mar 21, 2024, 2:42 PM Matt Turner <mattst88@gmail.com> wrote:
> Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
>
> > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > immediately resolved at startup. In cases where an external function
> > call depends needs to be made that may fail if such a call has not
> > been initialized yet (PLT-based relocation which is processed later).
> > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > may lead to a segfault because the PLT is not yet resolved.
>
> We cannot rely on function calls through the PLT in ifunc resolvers as
> the PLT may not have been initialized yet.
>
> In practice, this causes crashes when igt is linked with -Wl,-z,now or
> when linked with the mold linker.
>
> To avoid this problem, we do two things:
> 1. move igt_x86_features() to igt_x86.h so its definition is
> available to compilation units that call the function.
> 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> igt_x86_features() is inlined. Since this function is only called
> from a few places it does not significantly increase binary size
> to inline it.
>
> Linux distros (at least Fedora since v23, Gentoo/Hardened, soon standard
> Gentoo) use `-Wl,-z now` to improve security. By binding upfront, the
> loader can mark the GOT as read-only for a security enhancement. See
> https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
>
> Bug: https://bugs.gentoo.org/788625
> Bug: https://bugs.gentoo.org/925348
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Matt Turner <mattst88@gmail.com>
> ---
> lib/igt_halffloat.c | 8 +++
> lib/igt_x86.c | 119 ++------------------------------------------
> lib/igt_x86.h | 117 ++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 128 insertions(+), 116 deletions(-)
>
> diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
> index 5dbe08e01..560952d20 100644
> --- a/lib/igt_halffloat.c
> +++ b/lib/igt_halffloat.c
> @@ -194,6 +194,10 @@ static void half_to_float(const uint16_t *h, float
> *f, unsigned int num)
> f[i] = _half_to_float(h[i]);
> }
>
> +/* The PLT is not initialized when ifunc resolvers run, so all external
> + * functions must be inlined with __attribute__((flatten)).
> + */
> +__attribute__((flatten))
> static void (*resolve_float_to_half(void))(const float *f, uint16_t *h,
> unsigned int num)
> {
> if (igt_x86_features() & F16C)
> @@ -205,6 +209,10 @@ static void (*resolve_float_to_half(void))(const
> float *f, uint16_t *h, unsigned
> void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
> __attribute__((ifunc("resolve_float_to_half")));
>
> +/* The PLT is not initialized when ifunc resolvers run, so all external
> + * functions must be inlined with __attribute__((flatten)).
> + */
> +__attribute__((flatten))
> static void (*resolve_half_to_float(void))(const uint16_t *h, float *f,
> unsigned int num)
> {
> if (igt_x86_features() & F16C)
> diff --git a/lib/igt_x86.c b/lib/igt_x86.c
> index 8c102fd13..f60568be5 100644
> --- a/lib/igt_x86.c
> +++ b/lib/igt_x86.c
> @@ -27,14 +27,6 @@
>
> #include "config.h"
>
> -#ifdef HAVE_CPUID_H
> -#include <cpuid.h>
> -#else
> -#define __get_cpuid_max(x, y) 0
> -#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> -#endif
> -
> #include "igt_x86.h"
> #include "igt_aux.h"
>
> @@ -49,114 +41,7 @@
> * @include: igt_x86.h
> */
>
> -#define BASIC_CPUID 0x0
> -#define EXTENDED_CPUID 0x80000000
> -
> -#ifndef bit_MMX
> -#define bit_MMX (1 << 23)
> -#endif
> -
> -#ifndef bit_SSE
> -#define bit_SSE (1 << 25)
> -#endif
> -
> -#ifndef bit_SSE2
> -#define bit_SSE2 (1 << 26)
> -#endif
> -
> -#ifndef bit_SSE3
> -#define bit_SSE3 (1 << 0)
> -#endif
> -
> -#ifndef bit_SSSE3
> -#define bit_SSSE3 (1 << 9)
> -#endif
> -
> -#ifndef bit_SSE4_1
> -#define bit_SSE4_1 (1 << 19)
> -#endif
> -
> -#ifndef bit_SSE4_2
> -#define bit_SSE4_2 (1 << 20)
> -#endif
> -
> -#ifndef bit_OSXSAVE
> -#define bit_OSXSAVE (1 << 27)
> -#endif
> -
> -#ifndef bit_AVX
> -#define bit_AVX (1 << 28)
> -#endif
> -
> -#ifndef bit_F16C
> -#define bit_F16C (1 << 29)
> -#endif
> -
> -#ifndef bit_AVX2
> -#define bit_AVX2 (1<<5)
> -#endif
> -
> -#define xgetbv(index,eax,edx) \
> - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> -
> -#define has_YMM 0x1
> -
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void)
> -{
> - unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> - unsigned eax, ebx, ecx, edx;
> - unsigned features = 0;
> - unsigned extra = 0;
> -
> - if (max >= 1) {
> - __cpuid(1, eax, ebx, ecx, edx);
> -
> - if (ecx & bit_SSE3)
> - features |= SSE3;
> -
> - if (ecx & bit_SSSE3)
> - features |= SSSE3;
> -
> - if (ecx & bit_SSE4_1)
> - features |= SSE4_1;
> -
> - if (ecx & bit_SSE4_2)
> - features |= SSE4_2;
> -
> - if (ecx & bit_OSXSAVE) {
> - unsigned int bv_eax, bv_ecx;
> - xgetbv(0, bv_eax, bv_ecx);
> - if ((bv_eax & 6) == 6)
> - extra |= has_YMM;
> - }
> -
> - if ((extra & has_YMM) && (ecx & bit_AVX))
> - features |= AVX;
> -
> - if (edx & bit_MMX)
> - features |= MMX;
> -
> - if (edx & bit_SSE)
> - features |= SSE;
> -
> - if (edx & bit_SSE2)
> - features |= SSE2;
> -
> - if (ecx & bit_F16C)
> - features |= F16C;
> - }
> -
> - if (max >= 7) {
> - __cpuid_count(7, 0, eax, ebx, ecx, edx);
> -
> - if ((extra & has_YMM) && (ebx & bit_AVX2))
> - features |= AVX2;
> - }
> -
> - return features;
> -}
> -
> char *igt_x86_features_to_string(unsigned features, char *line)
> {
> char *ret = line;
> @@ -284,6 +169,10 @@ static void memcpy_from_wc(void *dst, const void
> *src, unsigned long len)
> memcpy(dst, src, len);
> }
>
> +/* The PLT is not initialized when ifunc resolvers run, so all external
> + * functions must be inlined with __attribute__((flatten)).
> + */
> +__attribute__((flatten))
> static void (*resolve_memcpy_from_wc(void))(void *, const void *,
> unsigned long)
> {
> if (igt_x86_features() & SSE4_1)
> diff --git a/lib/igt_x86.h b/lib/igt_x86.h
> index c7b84dec2..1e0195c4b 100644
> --- a/lib/igt_x86.h
> +++ b/lib/igt_x86.h
> @@ -30,6 +30,14 @@
> #ifndef IGT_X86_H
> #define IGT_X86_H
>
> +#ifdef HAVE_CPUID_H
> +#include <cpuid.h>
> +#else
> +#define __get_cpuid_max(x, y) 0
> +#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> +#endif
> +
> #define MMX 0x1
> #define SSE 0x2
> #define SSE2 0x4
> @@ -42,7 +50,114 @@
> #define F16C 0x200
>
> #if defined(__x86_64__) || defined(__i386__)
> -unsigned igt_x86_features(void);
> +
> +#define BASIC_CPUID 0x0
> +#define EXTENDED_CPUID 0x80000000
> +
> +#ifndef bit_MMX
> +#define bit_MMX (1 << 23)
> +#endif
> +
> +#ifndef bit_SSE
> +#define bit_SSE (1 << 25)
> +#endif
> +
> +#ifndef bit_SSE2
> +#define bit_SSE2 (1 << 26)
> +#endif
> +
> +#ifndef bit_SSE3
> +#define bit_SSE3 (1 << 0)
> +#endif
> +
> +#ifndef bit_SSSE3
> +#define bit_SSSE3 (1 << 9)
> +#endif
> +
> +#ifndef bit_SSE4_1
> +#define bit_SSE4_1 (1 << 19)
> +#endif
> +
> +#ifndef bit_SSE4_2
> +#define bit_SSE4_2 (1 << 20)
> +#endif
> +
> +#ifndef bit_OSXSAVE
> +#define bit_OSXSAVE (1 << 27)
> +#endif
> +
> +#ifndef bit_AVX
> +#define bit_AVX (1 << 28)
> +#endif
> +
> +#ifndef bit_F16C
> +#define bit_F16C (1 << 29)
> +#endif
> +
> +#ifndef bit_AVX2
> +#define bit_AVX2 (1<<5)
> +#endif
> +
> +#define xgetbv(index,eax,edx) \
> + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> +
> +#define has_YMM 0x1
> +
> +static inline unsigned igt_x86_features(void)
> +{
> + unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> + unsigned eax, ebx, ecx, edx;
> + unsigned features = 0;
> + unsigned extra = 0;
> +
> + if (max >= 1) {
> + __cpuid(1, eax, ebx, ecx, edx);
> +
> + if (ecx & bit_SSE3)
> + features |= SSE3;
> +
> + if (ecx & bit_SSSE3)
> + features |= SSSE3;
> +
> + if (ecx & bit_SSE4_1)
> + features |= SSE4_1;
> +
> + if (ecx & bit_SSE4_2)
> + features |= SSE4_2;
> +
> + if (ecx & bit_OSXSAVE) {
> + unsigned int bv_eax, bv_ecx;
> + xgetbv(0, bv_eax, bv_ecx);
> + if ((bv_eax & 6) == 6)
> + extra |= has_YMM;
> + }
> +
> + if ((extra & has_YMM) && (ecx & bit_AVX))
> + features |= AVX;
> +
> + if (edx & bit_MMX)
> + features |= MMX;
> +
> + if (edx & bit_SSE)
> + features |= SSE;
> +
> + if (edx & bit_SSE2)
> + features |= SSE2;
> +
> + if (ecx & bit_F16C)
> + features |= F16C;
> + }
> +
> + if (max >= 7) {
> + __cpuid_count(7, 0, eax, ebx, ecx, edx);
> +
> + if ((extra & has_YMM) && (ebx & bit_AVX2))
> + features |= AVX2;
> + }
> +
> + return features;
> +}
> +
> char *igt_x86_features_to_string(unsigned features, char *line);
> #else
> static inline unsigned igt_x86_features(void)
> --
> 2.43.2
>
>
[-- Attachment #2: Type: text/html, Size: 13391 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2] lib: Inline igt_x86_features() into ifunc resolvers
2024-03-25 17:15 ` Matt Turner
@ 2024-03-26 17:36 ` Kamil Konieczny
0 siblings, 0 replies; 18+ messages in thread
From: Kamil Konieczny @ 2024-03-26 17:36 UTC (permalink / raw
To: Development mailing list for IGT GPU Tools
Cc: Matt Turner, Zbigniew Kempczyński
Hi Matt,
On 2024-03-25 at 13:15:17 -0400, Matt Turner wrote:
> Please commit me :)
>
I merged your commit with some whitespaces corrected.
Thank you for your contribution!
Regards,
Kamil
> On Thu, Mar 21, 2024, 2:42 PM Matt Turner <mattst88@gmail.com> wrote:
>
> > Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC
> >
> > > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be
> > > immediately resolved at startup. In cases where an external function
> > > call depends needs to be made that may fail if such a call has not
> > > been initialized yet (PLT-based relocation which is processed later).
> > > For example calling strlen in an IFUNC resolver built with -Wl,z,now
> > > may lead to a segfault because the PLT is not yet resolved.
> >
> > We cannot rely on function calls through the PLT in ifunc resolvers as
> > the PLT may not have been initialized yet.
> >
> > In practice, this causes crashes when igt is linked with -Wl,-z,now or
> > when linked with the mold linker.
> >
> > To avoid this problem, we do two things:
> > 1. move igt_x86_features() to igt_x86.h so its definition is
> > available to compilation units that call the function.
> > 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure
> > igt_x86_features() is inlined. Since this function is only called
> > from a few places it does not significantly increase binary size
> > to inline it.
> >
> > Linux distros (at least Fedora since v23, Gentoo/Hardened, soon standard
> > Gentoo) use `-Wl,-z now` to improve security. By binding upfront, the
> > loader can mark the GOT as read-only for a security enhancement. See
> > https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details.
> >
> > Bug: https://bugs.gentoo.org/788625
> > Bug: https://bugs.gentoo.org/925348
> > Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Matt Turner <mattst88@gmail.com>
> > ---
> > lib/igt_halffloat.c | 8 +++
> > lib/igt_x86.c | 119 ++------------------------------------------
> > lib/igt_x86.h | 117 ++++++++++++++++++++++++++++++++++++++++++-
> > 3 files changed, 128 insertions(+), 116 deletions(-)
> >
> > diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c
> > index 5dbe08e01..560952d20 100644
> > --- a/lib/igt_halffloat.c
> > +++ b/lib/igt_halffloat.c
> > @@ -194,6 +194,10 @@ static void half_to_float(const uint16_t *h, float
> > *f, unsigned int num)
> > f[i] = _half_to_float(h[i]);
> > }
> >
> > +/* The PLT is not initialized when ifunc resolvers run, so all external
> > + * functions must be inlined with __attribute__((flatten)).
> > + */
> > +__attribute__((flatten))
> > static void (*resolve_float_to_half(void))(const float *f, uint16_t *h,
> > unsigned int num)
> > {
> > if (igt_x86_features() & F16C)
> > @@ -205,6 +209,10 @@ static void (*resolve_float_to_half(void))(const
> > float *f, uint16_t *h, unsigned
> > void igt_float_to_half(const float *f, uint16_t *h, unsigned int num)
> > __attribute__((ifunc("resolve_float_to_half")));
> >
> > +/* The PLT is not initialized when ifunc resolvers run, so all external
> > + * functions must be inlined with __attribute__((flatten)).
> > + */
> > +__attribute__((flatten))
> > static void (*resolve_half_to_float(void))(const uint16_t *h, float *f,
> > unsigned int num)
> > {
> > if (igt_x86_features() & F16C)
> > diff --git a/lib/igt_x86.c b/lib/igt_x86.c
> > index 8c102fd13..f60568be5 100644
> > --- a/lib/igt_x86.c
> > +++ b/lib/igt_x86.c
> > @@ -27,14 +27,6 @@
> >
> > #include "config.h"
> >
> > -#ifdef HAVE_CPUID_H
> > -#include <cpuid.h>
> > -#else
> > -#define __get_cpuid_max(x, y) 0
> > -#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> > -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> > -#endif
> > -
> > #include "igt_x86.h"
> > #include "igt_aux.h"
> >
> > @@ -49,114 +41,7 @@
> > * @include: igt_x86.h
> > */
> >
> > -#define BASIC_CPUID 0x0
> > -#define EXTENDED_CPUID 0x80000000
> > -
> > -#ifndef bit_MMX
> > -#define bit_MMX (1 << 23)
> > -#endif
> > -
> > -#ifndef bit_SSE
> > -#define bit_SSE (1 << 25)
> > -#endif
> > -
> > -#ifndef bit_SSE2
> > -#define bit_SSE2 (1 << 26)
> > -#endif
> > -
> > -#ifndef bit_SSE3
> > -#define bit_SSE3 (1 << 0)
> > -#endif
> > -
> > -#ifndef bit_SSSE3
> > -#define bit_SSSE3 (1 << 9)
> > -#endif
> > -
> > -#ifndef bit_SSE4_1
> > -#define bit_SSE4_1 (1 << 19)
> > -#endif
> > -
> > -#ifndef bit_SSE4_2
> > -#define bit_SSE4_2 (1 << 20)
> > -#endif
> > -
> > -#ifndef bit_OSXSAVE
> > -#define bit_OSXSAVE (1 << 27)
> > -#endif
> > -
> > -#ifndef bit_AVX
> > -#define bit_AVX (1 << 28)
> > -#endif
> > -
> > -#ifndef bit_F16C
> > -#define bit_F16C (1 << 29)
> > -#endif
> > -
> > -#ifndef bit_AVX2
> > -#define bit_AVX2 (1<<5)
> > -#endif
> > -
> > -#define xgetbv(index,eax,edx) \
> > - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> > -
> > -#define has_YMM 0x1
> > -
> > #if defined(__x86_64__) || defined(__i386__)
> > -unsigned igt_x86_features(void)
> > -{
> > - unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> > - unsigned eax, ebx, ecx, edx;
> > - unsigned features = 0;
> > - unsigned extra = 0;
> > -
> > - if (max >= 1) {
> > - __cpuid(1, eax, ebx, ecx, edx);
> > -
> > - if (ecx & bit_SSE3)
> > - features |= SSE3;
> > -
> > - if (ecx & bit_SSSE3)
> > - features |= SSSE3;
> > -
> > - if (ecx & bit_SSE4_1)
> > - features |= SSE4_1;
> > -
> > - if (ecx & bit_SSE4_2)
> > - features |= SSE4_2;
> > -
> > - if (ecx & bit_OSXSAVE) {
> > - unsigned int bv_eax, bv_ecx;
> > - xgetbv(0, bv_eax, bv_ecx);
> > - if ((bv_eax & 6) == 6)
> > - extra |= has_YMM;
> > - }
> > -
> > - if ((extra & has_YMM) && (ecx & bit_AVX))
> > - features |= AVX;
> > -
> > - if (edx & bit_MMX)
> > - features |= MMX;
> > -
> > - if (edx & bit_SSE)
> > - features |= SSE;
> > -
> > - if (edx & bit_SSE2)
> > - features |= SSE2;
> > -
> > - if (ecx & bit_F16C)
> > - features |= F16C;
> > - }
> > -
> > - if (max >= 7) {
> > - __cpuid_count(7, 0, eax, ebx, ecx, edx);
> > -
> > - if ((extra & has_YMM) && (ebx & bit_AVX2))
> > - features |= AVX2;
> > - }
> > -
> > - return features;
> > -}
> > -
> > char *igt_x86_features_to_string(unsigned features, char *line)
> > {
> > char *ret = line;
> > @@ -284,6 +169,10 @@ static void memcpy_from_wc(void *dst, const void
> > *src, unsigned long len)
> > memcpy(dst, src, len);
> > }
> >
> > +/* The PLT is not initialized when ifunc resolvers run, so all external
> > + * functions must be inlined with __attribute__((flatten)).
> > + */
> > +__attribute__((flatten))
> > static void (*resolve_memcpy_from_wc(void))(void *, const void *,
> > unsigned long)
> > {
> > if (igt_x86_features() & SSE4_1)
> > diff --git a/lib/igt_x86.h b/lib/igt_x86.h
> > index c7b84dec2..1e0195c4b 100644
> > --- a/lib/igt_x86.h
> > +++ b/lib/igt_x86.h
> > @@ -30,6 +30,14 @@
> > #ifndef IGT_X86_H
> > #define IGT_X86_H
> >
> > +#ifdef HAVE_CPUID_H
> > +#include <cpuid.h>
> > +#else
> > +#define __get_cpuid_max(x, y) 0
> > +#define __cpuid(level, a, b, c, d) a = b = c = d = 0
> > +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0
> > +#endif
> > +
> > #define MMX 0x1
> > #define SSE 0x2
> > #define SSE2 0x4
> > @@ -42,7 +50,114 @@
> > #define F16C 0x200
> >
> > #if defined(__x86_64__) || defined(__i386__)
> > -unsigned igt_x86_features(void);
> > +
> > +#define BASIC_CPUID 0x0
> > +#define EXTENDED_CPUID 0x80000000
> > +
> > +#ifndef bit_MMX
> > +#define bit_MMX (1 << 23)
> > +#endif
> > +
> > +#ifndef bit_SSE
> > +#define bit_SSE (1 << 25)
> > +#endif
> > +
> > +#ifndef bit_SSE2
> > +#define bit_SSE2 (1 << 26)
> > +#endif
> > +
> > +#ifndef bit_SSE3
> > +#define bit_SSE3 (1 << 0)
> > +#endif
> > +
> > +#ifndef bit_SSSE3
> > +#define bit_SSSE3 (1 << 9)
> > +#endif
> > +
> > +#ifndef bit_SSE4_1
> > +#define bit_SSE4_1 (1 << 19)
> > +#endif
> > +
> > +#ifndef bit_SSE4_2
> > +#define bit_SSE4_2 (1 << 20)
> > +#endif
> > +
> > +#ifndef bit_OSXSAVE
> > +#define bit_OSXSAVE (1 << 27)
> > +#endif
> > +
> > +#ifndef bit_AVX
> > +#define bit_AVX (1 << 28)
> > +#endif
> > +
> > +#ifndef bit_F16C
> > +#define bit_F16C (1 << 29)
> > +#endif
> > +
> > +#ifndef bit_AVX2
> > +#define bit_AVX2 (1<<5)
> > +#endif
> > +
> > +#define xgetbv(index,eax,edx) \
> > + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index))
> > +
> > +#define has_YMM 0x1
> > +
> > +static inline unsigned igt_x86_features(void)
> > +{
> > + unsigned max = __get_cpuid_max(BASIC_CPUID, 0);
> > + unsigned eax, ebx, ecx, edx;
> > + unsigned features = 0;
> > + unsigned extra = 0;
> > +
> > + if (max >= 1) {
> > + __cpuid(1, eax, ebx, ecx, edx);
> > +
> > + if (ecx & bit_SSE3)
> > + features |= SSE3;
> > +
> > + if (ecx & bit_SSSE3)
> > + features |= SSSE3;
> > +
> > + if (ecx & bit_SSE4_1)
> > + features |= SSE4_1;
> > +
> > + if (ecx & bit_SSE4_2)
> > + features |= SSE4_2;
> > +
> > + if (ecx & bit_OSXSAVE) {
> > + unsigned int bv_eax, bv_ecx;
> > + xgetbv(0, bv_eax, bv_ecx);
> > + if ((bv_eax & 6) == 6)
> > + extra |= has_YMM;
> > + }
> > +
> > + if ((extra & has_YMM) && (ecx & bit_AVX))
> > + features |= AVX;
> > +
> > + if (edx & bit_MMX)
> > + features |= MMX;
> > +
> > + if (edx & bit_SSE)
> > + features |= SSE;
> > +
> > + if (edx & bit_SSE2)
> > + features |= SSE2;
> > +
> > + if (ecx & bit_F16C)
> > + features |= F16C;
> > + }
> > +
> > + if (max >= 7) {
> > + __cpuid_count(7, 0, eax, ebx, ecx, edx);
> > +
> > + if ((extra & has_YMM) && (ebx & bit_AVX2))
> > + features |= AVX2;
> > + }
> > +
> > + return features;
> > +}
> > +
> > char *igt_x86_features_to_string(unsigned features, char *line);
> > #else
> > static inline unsigned igt_x86_features(void)
> > --
> > 2.43.2
> >
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-03-26 17:36 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-04 22:16 [PATCH i-g-t] lib: Inline igt_x86_features() into ifunc resolvers Matt Turner
2024-03-04 22:46 ` ✓ CI.xeBAT: success for " Patchwork
2024-03-04 23:07 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-03-12 15:24 ` [PATCH i-g-t] " Matt Turner
2024-03-13 9:09 ` Zbigniew Kempczyński
2024-03-21 3:09 ` Matt Turner
2024-03-21 7:03 ` Zbigniew Kempczyński
2024-03-21 15:02 ` Matt Turner
2024-03-21 15:33 ` Zbigniew Kempczyński
2024-03-21 18:11 ` Kamil Konieczny
2024-03-21 18:17 ` Kamil Konieczny
2024-03-21 18:31 ` Matt Turner
2024-03-21 18:41 ` [PATCH v2] " Matt Turner
2024-03-25 17:15 ` Matt Turner
2024-03-26 17:36 ` Kamil Konieczny
2024-03-21 19:45 ` ✓ Fi.CI.BAT: success for lib: Inline igt_x86_features() into ifunc resolvers (rev2) Patchwork
2024-03-21 19:51 ` ✓ CI.xeBAT: " Patchwork
2024-03-22 12:20 ` ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.