* [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty
@ 2024-03-06 17:19 Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
` (9 more replies)
0 siblings, 10 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza
Hi,
This version is rebased on top of alistair/riscv-to-apply.next, fixing
onflicts with the Ztso changes in ldst_us_trans().
No other changes made. All patches acked.
v6 link: https://lore.kernel.org/qemu-riscv/20240221213140.365232-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (8):
trans_rvv.c.inc: mark_vs_dirty() before loads and stores
trans_rvv.c.inc: remove 'is_store' bool from load/store fns
target/riscv: remove 'over' brconds from vector trans
target/riscv/translate.c: remove 'cpu_vstart' global
target/riscv: remove 'cpu_vl' global
target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
target/riscv/vector_helper.c: optimize loops in ldst helpers
Ivan Klokov (1):
target/riscv: Clear vstart_qe_zero flag
target/riscv/insn_trans/trans_rvbf16.c.inc | 18 +-
target/riscv/insn_trans/trans_rvv.c.inc | 283 ++++++---------------
target/riscv/insn_trans/trans_rvvk.c.inc | 30 +--
target/riscv/translate.c | 11 +-
target/riscv/vector_helper.c | 7 +-
5 files changed, 99 insertions(+), 250 deletions(-)
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v7 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 2/9] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
` (8 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson
While discussing a problem with how we're (not) setting vstart_eq_zero
Richard had the following to say w.r.t the conditional mark_vs_dirty()
calls on load/store functions [1]:
"I think it's required to have stores set dirty unconditionally, before
the operation.
Consider a store that traps on the 2nd element, leaving vstart = 2, and
exiting to the main loop via exception. The exception enters the kernel
page fault handler. The kernel may need to fault in the page for the
process, and in the meantime task switch.
If vs dirty is not already set, the kernel won't know to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 742008f58b..b838b8ea5b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -652,16 +652,14 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ mark_vs_dirty(s);
+
fn(dest, mask, base, tcg_env, desc);
if (!is_store && s->ztso) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
- if (!is_store) {
- mark_vs_dirty(s);
- }
-
gen_set_label(over);
return true;
}
@@ -817,11 +815,9 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, stride, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, stride, tcg_env, desc);
gen_set_label(over);
return true;
@@ -924,11 +920,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, index, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, index, tcg_env, desc);
gen_set_label(over);
return true;
@@ -1122,11 +1116,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ mark_vs_dirty(s);
+
fn(dest, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
gen_set_label(over);
return true;
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 2/9] trans_rvv.c.inc: remove 'is_store' bool from load/store fns
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson,
Philippe Mathieu-Daudé
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in some load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 58 ++++++++++++-------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b838b8ea5b..e42728990e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -796,7 +796,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base, stride;
@@ -843,7 +843,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -877,7 +877,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
return false;
}
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -900,7 +900,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask, index;
TCGv base;
@@ -967,7 +967,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1019,7 +1019,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1098,7 +1098,7 @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
uint32_t evl = s->cfg_ptr->vlenb * nf / width;
TCGLabel *over = gen_new_label();
@@ -1129,42 +1129,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
* load and store whole register instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 7.9)
*/
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
- gen_helper_##NAME, s, IS_STORE); \
+ gen_helper_##NAME, s); \
} \
return false; \
}
-GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
-GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
-GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
/*
* The vector whole register store instructions are encoded similar to
* unmasked unit-stride store of elements with EEW=8.
*/
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
/*
*** Vector Integer Arithmetic Instructions
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 2/9] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-08 3:34 ` LIU Zhiwei
2024-03-06 17:19 ` [PATCH v7 4/9] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson
Most of the vector translations has this following pattern at the start:
TCGLabel *over = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
And then right at the end:
gen_set_label(over);
return true;
This means that if vstart >= vl we'll not set vstart = 0 at the end of
the insns - this is done inside the helper that is being skipped. The
reason why this pattern hasn't been a bigger problem is because the
conditional vstart >= vl is very rare.
Checking all the helpers in vector_helper.c we see all of them with a
pattern like this:
for (i = env->vstart; i < vl; i++) {
(...)
}
env->vstart = 0;
Thus they can handle vstart >= vl case gracefully, with the benefit of
setting env->vstart = 0 during the process.
Remove all 'over' conditionals and let the helper set env->vstart = 0
every time.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
3 files changed, 147 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 8ee99df3f3..a842e76a6b 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfncvtbf16_f_f_w);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
@@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwcvtbf16_f_f_v);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
@@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwmaccbf16_vv);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index e42728990e..0114a132b3 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
- gen_set_label(over);
return true;
}
@@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
TCGv base, stride;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
fn(dest, mask, base, stride, tcg_env, desc);
- gen_set_label(over);
return true;
}
@@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
@@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, base, index, tcg_env, desc);
- gen_set_label(over);
return true;
}
@@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1100,10 +1084,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
DisasContext *s)
{
- uint32_t evl = s->cfg_ptr->vlenb * nf / width;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
-
TCGv_ptr dest;
TCGv base;
TCGv_i32 desc;
@@ -1120,8 +1100,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
fn(dest, base, tcg_env, desc);
- gen_set_label(over);
-
return true;
}
@@ -1195,10 +1173,6 @@ static inline bool
do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
gen_helper_gvec_4_ptr *fn)
{
- TCGLabel *over = gen_new_label();
-
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd),
vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
@@ -1216,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
s->cfg_ptr->vlenb, data, fn);
}
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1248,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
TCGv_i32 desc;
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -1271,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1410,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
TCGv_i32 desc;
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -1433,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1495,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
{
if (checkfn(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1509,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
s->cfg_ptr->vlenb,
data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -1571,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
{
if (opiwv_widen_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1584,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -1643,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
gen_helper_gvec_4_ptr *fn, DisasContext *s)
{
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1655,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1834,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -1848,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2045,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data,
fns[s->sew]);
- gen_set_label(over);
}
mark_vs_dirty(s);
return true;
@@ -2068,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
/* vmv.v.x has rs2 = 0 and vm = 1 */
vext_check_ss(s, a->rd, 0, 1)) {
TCGv s1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
s1 = get_gpr(s, a->rs1, EXT_SIGN);
@@ -2102,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
}
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -2129,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
s1 = tcg_constant_i64(simm);
dest = tcg_temp_new_ptr();
@@ -2140,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
fns[s->sew](dest, s1, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
}
return true;
}
@@ -2275,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2292,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2310,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
TCGv_i32 desc;
TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2330,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, t1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -2393,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_gvec_4_ptr * const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2408,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2467,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_gvec_4_ptr * const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2482,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2584,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
{
if (checkfn(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(s, rm);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2597,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -2696,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
gen_helper_vmv_v_x_w,
gen_helper_vmv_v_x_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
t1 = tcg_temp_new_i64();
/* NaN-box f[rs1] */
@@ -2711,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
fns[s->sew - 1](dest, t1, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
}
return true;
}
@@ -2773,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2787,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2824,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2838,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2891,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2905,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2940,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2954,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3031,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = \
@@ -3043,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, fn); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3131,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->vstart_eq_zero) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -3145,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
data, fn); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3171,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
require_align(a->rd, s->lmul) &&
s->vstart_eq_zero) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -3187,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3201,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
require_align(a->rd, s->lmul) &&
require_vm(a->vm, a->rd)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -3217,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
s->cfg_ptr->vlenb,
data, fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3386,9 +3287,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
TCGv_i64 t1;
TCGv s1;
- TCGLabel *over = gen_new_label();
-
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
t1 = tcg_temp_new_i64();
@@ -3400,7 +3298,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3442,10 +3339,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
/* The instructions ignore LMUL and vector register group. */
TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
-
- /* if vstart >= vl, skip vector register write back */
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
/* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
@@ -3453,7 +3346,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
vec_element_storei(s, a->rd, 0, t1);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3624,8 +3516,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
@@ -3635,7 +3525,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
s->cfg_ptr->vlenb, data,
fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3658,12 +3547,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
mark_vs_dirty(s); \
} else { \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \
- gen_set_label(over); \
} \
return true; \
} \
@@ -3692,8 +3578,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_gvec_3_ptr *fn;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
static gen_helper_gvec_3_ptr * const fns[6][4] = {
{
@@ -3738,7 +3622,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index a5cdd1b67f..6d640e4596 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
TCGv_ptr rd_v, rs2_v; \
TCGv_i32 desc, egs; \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
TCGv_ptr rd_v, rs2_v; \
TCGv_i32 uimm_v, desc, egs; \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
{ \
if (CHECK(s, a)) { \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
TCGv_i32 egs; \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
@@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
data, gen_helper_##NAME); \
\
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
{
if (vsha_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
TCGv_i32 egs;
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
@@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, tcg_env);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
{
if (vsha_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
TCGv_i32 egs;
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
@@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, tcg_env);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 4/9] target/riscv/translate.c: remove 'cpu_vstart' global
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (2 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 5/9] target/riscv: remove 'cpu_vl' global Daniel Henrique Barboza
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson,
Philippe Mathieu-Daudé
The global is unused after recent changes.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ea5d52b2ef..3e12371887 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -38,7 +38,7 @@
#undef HELPER_H
/* global register indices */
-static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -1324,8 +1324,6 @@ void riscv_translate_init(void)
cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
- cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
- "vstart");
load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 5/9] target/riscv: remove 'cpu_vl' global
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (3 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 4/9] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 6/9] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson,
Philippe Mathieu-Daudé
At this moment the global is used only in do_vsetvl(). Do a direct env
load in do_vsetvl() to read 'vl' and remove the global.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
target/riscv/translate.c | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 0114a132b3..279740f147 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -157,7 +157,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
if (rd == 0 && rs1 == 0) {
s1 = tcg_temp_new();
- tcg_gen_mov_tl(s1, cpu_vl);
+ tcg_gen_ld_tl(s1, tcg_env, offsetof(CPURISCVState, vl));
} else if (rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_constant_tl(RV_VLEN_MAX);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3e12371887..002808895c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -38,7 +38,7 @@
#undef HELPER_H
/* global register indices */
-static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -1323,7 +1323,6 @@ void riscv_translate_init(void)
}
cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
- cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 6/9] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (4 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 5/9] target/riscv: remove 'cpu_vl' global Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb2..cc7290a1bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4782,6 +4782,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
+ env->vstart = 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (5 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 6/9] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 20:42 ` Philippe Mathieu-Daudé
2024-03-06 17:19 ` [PATCH v7 8/9] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
` (2 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 279740f147..5018bb5a62 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2065,7 +2065,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), simm);
- mark_vs_dirty(s);
} else {
TCGv_i32 desc;
TCGv_i64 s1;
@@ -2083,9 +2082,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, tcg_env, desc);
-
- mark_vs_dirty(s);
}
+ mark_vs_dirty(s);
return true;
}
return false;
@@ -2612,7 +2610,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), t1);
- mark_vs_dirty(s);
} else {
TCGv_ptr dest;
TCGv_i32 desc;
@@ -2635,9 +2632,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, t1, tcg_env, desc);
-
- mark_vs_dirty(s);
}
+ mark_vs_dirty(s);
return true;
}
return false;
@@ -3545,12 +3541,11 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
if (s->vstart_eq_zero) { \
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
- mark_vs_dirty(s); \
} else { \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
- mark_vs_dirty(s); \
} \
+ mark_vs_dirty(s); \
return true; \
} \
return false; \
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 8/9] target/riscv: Clear vstart_qe_zero flag
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (6 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 9/9] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza
2024-03-07 0:37 ` [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Alistair Francis
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Ivan Klokov, Daniel Henrique Barboza, Richard Henderson
From: Ivan Klokov <ivan.klokov@syntacore.com>
The vstart_qe_zero flag is set at the beginning of the translation
phase from the env->vstart variable. During the execution phase all
functions will set env->vstart = 0 after a successful execution,
but the vstart_eq_zero flag remains the same as at the start of the
block. This will wrongly cause SIGILLs in translations that requires
env->vstart = 0 and might be reading vstart_eq_zero = false.
This patch adds a new finalize_rvv_inst() helper that is called at the
end of each vector instruction that will both update vstart_eq_zero and
do a mark_vs_dirty().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc | 78 ++++++++++++----------
target/riscv/insn_trans/trans_rvvk.c.inc | 12 ++--
target/riscv/translate.c | 6 ++
4 files changed, 56 insertions(+), 46 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index a842e76a6b..0a9cd1ec31 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -83,7 +83,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfncvtbf16_f_f_w);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
@@ -108,7 +108,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwcvtbf16_f_f_v);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
@@ -135,7 +135,7 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwmaccbf16_vv);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5018bb5a62..85ef48eb87 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -167,7 +167,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
@@ -187,7 +187,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
@@ -657,6 +657,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
+ finalize_rvv_inst(s);
return true;
}
@@ -812,6 +813,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
fn(dest, mask, base, stride, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -913,6 +915,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, base, index, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -1043,7 +1046,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1100,6 +1103,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
fn(dest, base, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -1189,7 +1193,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1240,7 +1244,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1265,7 +1269,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1398,7 +1402,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1412,7 +1416,7 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode);
@@ -1471,7 +1475,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb,
data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -1543,7 +1547,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs2),
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -1611,7 +1615,7 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1744,7 +1748,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1801,7 +1805,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2004,7 +2008,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
s->cfg_ptr->vlenb, data,
fns[s->sew]);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2049,7 +2053,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
fns[s->sew](dest, s1_i64, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2083,7 +2087,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2231,7 +2235,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2265,7 +2269,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, t1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -2340,7 +2344,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2411,7 +2415,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2523,7 +2527,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2633,7 +2637,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
fns[s->sew - 1](dest, t1, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2705,7 +2709,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2753,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2817,7 +2821,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2863,7 +2867,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2949,7 +2953,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, fn); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3048,7 +3052,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_env, s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, \
data, fn); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3087,7 +3091,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3114,7 +3118,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb,
data, fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3293,7 +3297,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
s1 = get_gpr(s, a->rs1, EXT_NONE);
tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3341,7 +3345,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
do_nanbox(s, t1, cpu_fpr[a->rs1]);
vec_element_storei(s, a->rd, 0, t1);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3447,7 +3451,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -3475,7 +3479,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
endian_ofs(s, a->rs2, a->rs1),
MAXSZ(s), MAXSZ(s));
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -3520,7 +3524,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data,
fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3545,7 +3549,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
} \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3616,7 +3620,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 6d640e4596..ae1f40174a 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -266,7 +266,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -341,7 +341,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -405,7 +405,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, gen_helper_##NAME); \
\
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -457,7 +457,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
s->sew == MO_32 ?
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -488,7 +488,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
s->sew == MO_32 ?
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 002808895c..9ed9de8b95 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -676,6 +676,12 @@ static void mark_vs_dirty(DisasContext *ctx)
static inline void mark_vs_dirty(DisasContext *ctx) { }
#endif
+static void finalize_rvv_inst(DisasContext *ctx)
+{
+ mark_vs_dirty(ctx);
+ ctx->vstart_eq_zero = true;
+}
+
static void gen_set_rm(DisasContext *ctx, int rm)
{
if (ctx->frm == rm) {
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v7 9/9] target/riscv/vector_helper.c: optimize loops in ldst helpers
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (7 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 8/9] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
@ 2024-03-06 17:19 ` Daniel Henrique Barboza
2024-03-07 0:37 ` [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Alistair Francis
9 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-06 17:19 UTC (permalink / raw
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Daniel Henrique Barboza, Richard Henderson
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cc7290a1bb..1ab386830a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -208,7 +208,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t vma = vext_vma(desc);
- for (i = env->vstart; i < env->vl; i++, env->vstart++) {
+ for (i = env->vstart; i < env->vl; env->vstart = ++i) {
k = 0;
while (k < nf) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -274,7 +274,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
uint32_t esz = 1 << log2_esz;
/* load bytes from guest memory */
- for (i = env->vstart; i < evl; i++, env->vstart++) {
+ for (i = env->vstart; i < evl; env->vstart = ++i) {
k = 0;
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << log2_esz);
@@ -388,7 +388,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
- for (i = env->vstart; i < env->vl; i++, env->vstart++) {
+ for (i = env->vstart; i < env->vl; env->vstart = ++i) {
k = 0;
while (k < nf) {
if (!vm && !vext_elem_mask(v0, i)) {
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
2024-03-06 17:19 ` [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
@ 2024-03-06 20:42 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-03-06 20:42 UTC (permalink / raw
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, Richard Henderson
On 6/3/24 18:19, Daniel Henrique Barboza wrote:
> trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
> GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
> their 'ifs'. conditionals.
>
> Call it just once in the end like other functions are doing.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (8 preceding siblings ...)
2024-03-06 17:19 ` [PATCH v7 9/9] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza
@ 2024-03-07 0:37 ` Alistair Francis
9 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2024-03-07 0:37 UTC (permalink / raw
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer
On Thu, Mar 7, 2024 at 3:20 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This version is rebased on top of alistair/riscv-to-apply.next, fixing
> onflicts with the Ztso changes in ldst_us_trans().
>
> No other changes made. All patches acked.
>
> v6 link: https://lore.kernel.org/qemu-riscv/20240221213140.365232-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (8):
> trans_rvv.c.inc: mark_vs_dirty() before loads and stores
> trans_rvv.c.inc: remove 'is_store' bool from load/store fns
> target/riscv: remove 'over' brconds from vector trans
> target/riscv/translate.c: remove 'cpu_vstart' global
> target/riscv: remove 'cpu_vl' global
> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
> target/riscv/vector_helper.c: optimize loops in ldst helpers
>
> Ivan Klokov (1):
> target/riscv: Clear vstart_qe_zero flag
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/insn_trans/trans_rvbf16.c.inc | 18 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 283 ++++++---------------
> target/riscv/insn_trans/trans_rvvk.c.inc | 30 +--
> target/riscv/translate.c | 11 +-
> target/riscv/vector_helper.c | 7 +-
> 5 files changed, 99 insertions(+), 250 deletions(-)
>
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
2024-03-06 17:19 ` [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
@ 2024-03-08 3:34 ` LIU Zhiwei
2024-03-08 10:39 ` Daniel Henrique Barboza
0 siblings, 1 reply; 16+ messages in thread
From: LIU Zhiwei @ 2024-03-08 3:34 UTC (permalink / raw
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, palmer,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 44649 bytes --]
Hi Daniel and Alistair,
Hope it is not too late. I think there are two bugs in this patch.
1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper
function. If we remove the over check, it will set the first element of
destination vector register, which is against the specification.
According to the riscv-v-specification, 16.2. Floating-Point Scalar Move
Instructions,
"If vstart ≥ vl, no operation is performed and the destination register is not updated".
2) The second is for vector instruction with helper functions. we should
not change any elements including the tail elements when vstart >=vl.
But this patch break this behavior. According to the
riscv-v-specification, 5.4. Prestart, Active, Inactive, Body, and Tail
Element Denitions,
"When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group,
including that no tail elements are updated with agnostic values."
I will review this patch set in more details later.
Thanks,
Zhiwei
On 2024/3/7 1:19, Daniel Henrique Barboza wrote:
> Most of the vector translations has this following pattern at the start:
>
> TCGLabel *over = gen_new_label();
> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> And then right at the end:
>
> gen_set_label(over);
> return true;
>
> This means that if vstart >= vl we'll not set vstart = 0 at the end of
> the insns - this is done inside the helper that is being skipped. The
> reason why this pattern hasn't been a bigger problem is because the
> conditional vstart >= vl is very rare.
>
> Checking all the helpers in vector_helper.c we see all of them with a
> pattern like this:
>
> for (i = env->vstart; i < vl; i++) {
> (...)
> }
> env->vstart = 0;
>
> Thus they can handle vstart >= vl case gracefully, with the benefit of
> setting env->vstart = 0 during the process.
>
> Remove all 'over' conditionals and let the helper set env->vstart = 0
> every time.
>
> While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
> too since they're unneeded.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
> target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
> target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
> 3 files changed, 147 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
> index 8ee99df3f3..a842e76a6b 100644
> --- a/target/riscv/insn_trans/trans_rvbf16.c.inc
> +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
> @@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
>
> if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
>
> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> @@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
> ctx->cfg_ptr->vlenb, data,
> gen_helper_vfncvtbf16_f_f_w);
> mark_vs_dirty(ctx);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
>
> if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
>
> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> @@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
> ctx->cfg_ptr->vlenb, data,
> gen_helper_vfwcvtbf16_f_f_v);
> mark_vs_dirty(ctx);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
> if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
> vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
>
> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> @@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
> ctx->cfg_ptr->vlenb, data,
> gen_helper_vfwmaccbf16_vv);
> mark_vs_dirty(ctx);
> - gen_set_label(over);
> return true;
> }
> return false;
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index e42728990e..0114a132b3 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> TCGv base;
> TCGv_i32 desc;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> @@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> }
>
> - gen_set_label(over);
> return true;
> }
>
> @@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
> TCGv base, stride;
> TCGv_i32 desc;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> @@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>
> fn(dest, mask, base, stride, tcg_env, desc);
>
> - gen_set_label(over);
> return true;
> }
>
> @@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> TCGv base;
> TCGv_i32 desc;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> index = tcg_temp_new_ptr();
> @@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>
> fn(dest, mask, base, index, tcg_env, desc);
>
> - gen_set_label(over);
> return true;
> }
>
> @@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> TCGv base;
> TCGv_i32 desc;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> @@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> fn(dest, mask, base, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -1100,10 +1084,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> uint32_t width, gen_helper_ldst_whole *fn,
> DisasContext *s)
> {
> - uint32_t evl = s->cfg_ptr->vlenb * nf / width;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> -
> TCGv_ptr dest;
> TCGv base;
> TCGv_i32 desc;
> @@ -1120,8 +1100,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
>
> fn(dest, base, tcg_env, desc);
>
> - gen_set_label(over);
> -
> return true;
> }
>
> @@ -1195,10 +1173,6 @@ static inline bool
> do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> gen_helper_gvec_4_ptr *fn)
> {
> - TCGLabel *over = gen_new_label();
> -
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
> gvec_fn(s->sew, vreg_ofs(s, a->rd),
> vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
> @@ -1216,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> s->cfg_ptr->vlenb, data, fn);
> }
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -1248,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> TCGv_i32 desc;
> uint32_t data = 0;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> @@ -1271,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> fn(dest, mask, src1, src2, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -1410,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> TCGv_i32 desc;
> uint32_t data = 0;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> @@ -1433,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> fn(dest, mask, src1, src2, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -1495,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> {
> if (checkfn(s, a)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -1509,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> s->cfg_ptr->vlenb,
> data, fn);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -1571,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> {
> if (opiwv_widen_check(s, a)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -1584,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> tcg_env, s->cfg_ptr->vlenb,
> s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -1643,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
> gen_helper_gvec_4_ptr *fn, DisasContext *s)
> {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -1655,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
> vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
> s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -1834,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> gen_helper_##NAME##_h, \
> gen_helper_##NAME##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -1848,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2045,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
> gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
> };
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> tcg_env, s->cfg_ptr->vlenb,
> s->cfg_ptr->vlenb, data,
> fns[s->sew]);
> - gen_set_label(over);
> }
> mark_vs_dirty(s);
> return true;
> @@ -2068,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> /* vmv.v.x has rs2 = 0 and vm = 1 */
> vext_check_ss(s, a->rd, 0, 1)) {
> TCGv s1;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> s1 = get_gpr(s, a->rs1, EXT_SIGN);
>
> @@ -2102,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> }
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -2129,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
> gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
> gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
> };
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> s1 = tcg_constant_i64(simm);
> dest = tcg_temp_new_ptr();
> @@ -2140,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
> fns[s->sew](dest, s1, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> }
> return true;
> }
> @@ -2275,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> gen_helper_##NAME##_w, \
> gen_helper_##NAME##_d, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm(s, RISCV_FRM_DYN); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2292,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2310,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> TCGv_i32 desc;
> TCGv_i64 t1;
>
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> -
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> @@ -2330,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> fn(dest, mask, t1, src2, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> @@ -2393,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> static gen_helper_gvec_4_ptr * const fns[2] = { \
> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm(s, RISCV_FRM_DYN); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2408,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2467,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> static gen_helper_gvec_4_ptr * const fns[2] = { \
> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm(s, RISCV_FRM_DYN); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2482,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2584,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> {
> if (checkfn(s, a)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> gen_set_rm_chkfrm(s, rm);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -2597,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> s->cfg_ptr->vlenb,
> s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -2696,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> gen_helper_vmv_v_x_w,
> gen_helper_vmv_v_x_d,
> };
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> t1 = tcg_temp_new_i64();
> /* NaN-box f[rs1] */
> @@ -2711,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> fns[s->sew - 1](dest, t1, tcg_env, desc);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> }
> return true;
> }
> @@ -2773,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> gen_helper_##HELPER##_h, \
> gen_helper_##HELPER##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm_chkfrm(s, FRM); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2787,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2824,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> gen_helper_##NAME##_h, \
> gen_helper_##NAME##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm(s, RISCV_FRM_DYN); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2838,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2891,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> gen_helper_##HELPER##_h, \
> gen_helper_##HELPER##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm_chkfrm(s, FRM); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2905,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -2940,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> gen_helper_##HELPER##_h, \
> gen_helper_##HELPER##_w, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> gen_set_rm_chkfrm(s, FRM); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -2954,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -3031,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> vext_check_isa_ill(s)) { \
> uint32_t data = 0; \
> gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = \
> @@ -3043,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> s->cfg_ptr->vlenb, \
> s->cfg_ptr->vlenb, data, fn); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -3131,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->vstart_eq_zero) { \
> uint32_t data = 0; \
> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -3145,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> s->cfg_ptr->vlenb, \
> data, fn); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -3171,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> require_align(a->rd, s->lmul) &&
> s->vstart_eq_zero) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -3187,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> s->cfg_ptr->vlenb,
> s->cfg_ptr->vlenb, data, fns[s->sew]);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -3201,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> require_align(a->rd, s->lmul) &&
> require_vm(a->vm, a->rd)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> @@ -3217,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> s->cfg_ptr->vlenb,
> data, fns[s->sew]);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -3386,9 +3287,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> TCGv_i64 t1;
> TCGv s1;
> - TCGLabel *over = gen_new_label();
> -
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> t1 = tcg_temp_new_i64();
>
> @@ -3400,7 +3298,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> tcg_gen_ext_tl_i64(t1, s1);
> vec_element_storei(s, a->rd, 0, t1);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -3442,10 +3339,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>
> /* The instructions ignore LMUL and vector register group. */
> TCGv_i64 t1;
> - TCGLabel *over = gen_new_label();
> -
> - /* if vstart >= vl, skip vector register write back */
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> /* NaN-box f[rs1] */
> t1 = tcg_temp_new_i64();
> @@ -3453,7 +3346,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>
> vec_element_storei(s, a->rd, 0, t1);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -3624,8 +3516,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
> gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
> };
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> @@ -3635,7 +3525,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> s->cfg_ptr->vlenb, data,
> fns[s->sew]);
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -3658,12 +3547,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> vreg_ofs(s, a->rs2), maxsz, maxsz); \
> mark_vs_dirty(s); \
> } else { \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
> tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> } \
> return true; \
> } \
> @@ -3692,8 +3578,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> {
> uint32_t data = 0;
> gen_helper_gvec_3_ptr *fn;
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> static gen_helper_gvec_3_ptr * const fns[6][4] = {
> {
> @@ -3738,7 +3622,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> s->cfg_ptr->vlenb, data, fn);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
> index a5cdd1b67f..6d640e4596 100644
> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
> @@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
> gen_helper_##NAME##_w, \
> gen_helper_##NAME##_d, \
> }; \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> @@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
> s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
> data, fns[s->sew]); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
> TCGv_ptr rd_v, rs2_v; \
> TCGv_i32 desc, egs; \
> uint32_t data = 0; \
> - TCGLabel *over = gen_new_label(); \
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> /* save opcode for unwinding in case we throw an exception */ \
> decode_save_opc(s); \
> egs = tcg_constant_i32(EGS); \
> gen_helper_egs_check(egs, tcg_env); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> } \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> @@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
> gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
> TCGv_ptr rd_v, rs2_v; \
> TCGv_i32 uimm_v, desc, egs; \
> uint32_t data = 0; \
> - TCGLabel *over = gen_new_label(); \
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> /* save opcode for unwinding in case we throw an exception */ \
> decode_save_opc(s); \
> egs = tcg_constant_i32(EGS); \
> gen_helper_egs_check(egs, tcg_env); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> } \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> @@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
> gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> { \
> if (CHECK(s, a)) { \
> uint32_t data = 0; \
> - TCGLabel *over = gen_new_label(); \
> TCGv_i32 egs; \
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> @@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> decode_save_opc(s); \
> egs = tcg_constant_i32(EGS); \
> gen_helper_egs_check(egs, tcg_env); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> } \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> @@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> data, gen_helper_##NAME); \
> \
> mark_vs_dirty(s); \
> - gen_set_label(over); \
> return true; \
> } \
> return false; \
> @@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> {
> if (vsha_check(s, a)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> TCGv_i32 egs;
>
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> @@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> decode_save_opc(s);
> egs = tcg_constant_i32(ZVKNH_EGS);
> gen_helper_egs_check(egs, tcg_env);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> }
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> @@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
> @@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> {
> if (vsha_check(s, a)) {
> uint32_t data = 0;
> - TCGLabel *over = gen_new_label();
> TCGv_i32 egs;
>
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> @@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> decode_save_opc(s);
> egs = tcg_constant_i32(ZVKNH_EGS);
> gen_helper_egs_check(egs, tcg_env);
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> }
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> @@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
>
> mark_vs_dirty(s);
> - gen_set_label(over);
> return true;
> }
> return false;
[-- Attachment #2: Type: text/html, Size: 43894 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
2024-03-08 3:34 ` LIU Zhiwei
@ 2024-03-08 10:39 ` Daniel Henrique Barboza
2024-03-08 11:13 ` Alistair Francis
0 siblings, 1 reply; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-08 10:39 UTC (permalink / raw
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, palmer,
Richard Henderson
On 3/8/24 00:34, LIU Zhiwei wrote:
> Hi Daniel and Alistair,
>
> Hope it is not too late. I think there are two bugs in this patch.
>
> 1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper function. If we remove the over check, it will set the first element of destination vector register, which is against the specification. According to the riscv-v-specification, 16.2. Floating-Point Scalar Move Instructions,
>
> "If vstart ≥ vl, no operation is performed and the destination register is not updated".
vfmv.s.f seems to have biggers problems: it's not setting env->vstart at any
point. In fact, in a quick look, there's a handful of cases where this is happening:
trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f.
I'll need an extra patch to fix them. We'll probably need to keep the cpu_vstart
and cpu_vl globals, and use brconds, to be able to handle the vstart >= vl
scenario that happens with them (since they don't use helpers).
>
> 2) The second is for vector instruction with helper functions. we should not change any elements including the tail elements when vstart >=vl. But this patch break this behavior. According to the riscv-v-specification, 5.4. Prestart, Active, Inactive, Body, and Tail Element Denitions,
>
> "When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group,
> including that no tail elements are updated with agnostic values."
Every helper in vector_helper.c has a pattern like:
(--- set variables ---)
for (i = env->vstart; i < vl; i++) {
/* do things */
}
env->vstart = 0;
vext_set_elems_1s() /*set tail */
When vstart >= vl there is no body elements and no tail, but I'm not sure about
vext_set_elems_1s() being able to handle that. In particular because we're setting
vstart=0 before calling it.
I'll add an additional patch to only call vext_set_elems_1s() to set the tail if
start < vl.
All this work with these changes is to put the 'vstart' management in a single place,
i.e. the helper (when available). Then the translations can freely set
vstart_eq_zero in the end (i.e. no exceptions/faults) knowing that the execution
code zeroed vstart. It's clearer than having the helper make assumptions (i.e.
vstart < vl) that were made during the translation. If the helper is setting
vstart = 0 the helper must also deal with any invalid value of vstart accordingly.
Thanks,
Daniel
>
> I will review this patch set in more details later.
>
> Thanks,
> Zhiwei
>
> On 2024/3/7 1:19, Daniel Henrique Barboza wrote:
>> Most of the vector translations has this following pattern at the start:
>>
>> TCGLabel *over = gen_new_label();
>> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> And then right at the end:
>>
>> gen_set_label(over);
>> return true;
>>
>> This means that if vstart >= vl we'll not set vstart = 0 at the end of
>> the insns - this is done inside the helper that is being skipped. The
>> reason why this pattern hasn't been a bigger problem is because the
>> conditional vstart >= vl is very rare.
>>
>> Checking all the helpers in vector_helper.c we see all of them with a
>> pattern like this:
>>
>> for (i = env->vstart; i < vl; i++) {
>> (...)
>> }
>> env->vstart = 0;
>>
>> Thus they can handle vstart >= vl case gracefully, with the benefit of
>> setting env->vstart = 0 during the process.
>>
>> Remove all 'over' conditionals and let the helper set env->vstart = 0
>> every time.
>>
>> While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
>> too since they're unneeded.
>>
>> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
>> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
>> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
>> ---
>> target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
>> target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
>> target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
>> 3 files changed, 147 deletions(-)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
>> index 8ee99df3f3..a842e76a6b 100644
>> --- a/target/riscv/insn_trans/trans_rvbf16.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
>> @@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
>>
>> if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>>
>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>> @@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
>> ctx->cfg_ptr->vlenb, data,
>> gen_helper_vfncvtbf16_f_f_w);
>> mark_vs_dirty(ctx);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
>>
>> if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>>
>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>> @@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
>> ctx->cfg_ptr->vlenb, data,
>> gen_helper_vfwcvtbf16_f_f_v);
>> mark_vs_dirty(ctx);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
>> if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
>> vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>>
>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>> @@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
>> ctx->cfg_ptr->vlenb, data,
>> gen_helper_vfwmaccbf16_vv);
>> mark_vs_dirty(ctx);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
>> index e42728990e..0114a132b3 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>> TCGv base;
>> TCGv_i32 desc;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> base = get_gpr(s, rs1, EXT_NONE);
>> @@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
>> }
>>
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>> TCGv base, stride;
>> TCGv_i32 desc;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> base = get_gpr(s, rs1, EXT_NONE);
>> @@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>>
>> fn(dest, mask, base, stride, tcg_env, desc);
>>
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>> TCGv base;
>> TCGv_i32 desc;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> index = tcg_temp_new_ptr();
>> @@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>>
>> fn(dest, mask, base, index, tcg_env, desc);
>>
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>> TCGv base;
>> TCGv_i32 desc;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> base = get_gpr(s, rs1, EXT_NONE);
>> @@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>> fn(dest, mask, base, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1100,10 +1084,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
>> uint32_t width, gen_helper_ldst_whole *fn,
>> DisasContext *s)
>> {
>> - uint32_t evl = s->cfg_ptr->vlenb * nf / width;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
>> -
>> TCGv_ptr dest;
>> TCGv base;
>> TCGv_i32 desc;
>> @@ -1120,8 +1100,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
>>
>> fn(dest, base, tcg_env, desc);
>>
>> - gen_set_label(over);
>> -
>> return true;
>> }
>>
>> @@ -1195,10 +1173,6 @@ static inline bool
>> do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
>> gen_helper_gvec_4_ptr *fn)
>> {
>> - TCGLabel *over = gen_new_label();
>> -
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
>> gvec_fn(s->sew, vreg_ofs(s, a->rd),
>> vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
>> @@ -1216,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
>> s->cfg_ptr->vlenb, data, fn);
>> }
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1248,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
>> TCGv_i32 desc;
>> uint32_t data = 0;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> src2 = tcg_temp_new_ptr();
>> @@ -1271,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
>> fn(dest, mask, src1, src2, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1410,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
>> TCGv_i32 desc;
>> uint32_t data = 0;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> src2 = tcg_temp_new_ptr();
>> @@ -1433,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
>> fn(dest, mask, src1, src2, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1495,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
>> {
>> if (checkfn(s, a)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -1509,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
>> s->cfg_ptr->vlenb,
>> data, fn);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -1571,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
>> {
>> if (opiwv_widen_check(s, a)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -1584,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
>> tcg_env, s->cfg_ptr->vlenb,
>> s->cfg_ptr->vlenb, data, fn);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -1643,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
>> gen_helper_gvec_4_ptr *fn, DisasContext *s)
>> {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -1655,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
>> vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
>> s->cfg_ptr->vlenb, data, fn);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -1834,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> gen_helper_##NAME##_h, \
>> gen_helper_##NAME##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -1848,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2045,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
>> gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
>> gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
>> };
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
>> tcg_env, s->cfg_ptr->vlenb,
>> s->cfg_ptr->vlenb, data,
>> fns[s->sew]);
>> - gen_set_label(over);
>> }
>> mark_vs_dirty(s);
>> return true;
>> @@ -2068,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
>> /* vmv.v.x has rs2 = 0 and vm = 1 */
>> vext_check_ss(s, a->rd, 0, 1)) {
>> TCGv s1;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> s1 = get_gpr(s, a->rs1, EXT_SIGN);
>>
>> @@ -2102,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
>> }
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -2129,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
>> gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
>> gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
>> };
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> s1 = tcg_constant_i64(simm);
>> dest = tcg_temp_new_ptr();
>> @@ -2140,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
>> fns[s->sew](dest, s1, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> }
>> return true;
>> }
>> @@ -2275,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> gen_helper_##NAME##_w, \
>> gen_helper_##NAME##_d, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm(s, RISCV_FRM_DYN); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2292,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew - 1]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2310,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>> TCGv_i32 desc;
>> TCGv_i64 t1;
>>
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> -
>> dest = tcg_temp_new_ptr();
>> mask = tcg_temp_new_ptr();
>> src2 = tcg_temp_new_ptr();
>> @@ -2330,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>> fn(dest, mask, t1, src2, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> @@ -2393,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> static gen_helper_gvec_4_ptr * const fns[2] = { \
>> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm(s, RISCV_FRM_DYN); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2408,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew - 1]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2467,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> static gen_helper_gvec_4_ptr * const fns[2] = { \
>> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm(s, RISCV_FRM_DYN); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2482,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew - 1]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2584,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
>> {
>> if (checkfn(s, a)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> gen_set_rm_chkfrm(s, rm);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -2597,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
>> s->cfg_ptr->vlenb,
>> s->cfg_ptr->vlenb, data, fn);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -2696,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>> gen_helper_vmv_v_x_w,
>> gen_helper_vmv_v_x_d,
>> };
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> t1 = tcg_temp_new_i64();
>> /* NaN-box f[rs1] */
>> @@ -2711,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>> fns[s->sew - 1](dest, t1, tcg_env, desc);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> }
>> return true;
>> }
>> @@ -2773,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> gen_helper_##HELPER##_h, \
>> gen_helper_##HELPER##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm_chkfrm(s, FRM); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2787,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew - 1]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2824,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> gen_helper_##NAME##_h, \
>> gen_helper_##NAME##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm(s, RISCV_FRM_DYN); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2838,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2891,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> gen_helper_##HELPER##_h, \
>> gen_helper_##HELPER##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm_chkfrm(s, FRM); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2905,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew - 1]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -2940,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> gen_helper_##HELPER##_h, \
>> gen_helper_##HELPER##_w, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> gen_set_rm_chkfrm(s, FRM); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -2954,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->cfg_ptr->vlenb, data, \
>> fns[s->sew]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -3031,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
>> vext_check_isa_ill(s)) { \
>> uint32_t data = 0; \
>> gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
>> - TCGLabel *over = gen_new_label(); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> data = \
>> @@ -3043,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
>> s->cfg_ptr->vlenb, \
>> s->cfg_ptr->vlenb, data, fn); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -3131,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->vstart_eq_zero) { \
>> uint32_t data = 0; \
>> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
>> - TCGLabel *over = gen_new_label(); \
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -3145,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>> s->cfg_ptr->vlenb, \
>> data, fn); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -3171,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
>> require_align(a->rd, s->lmul) &&
>> s->vstart_eq_zero) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -3187,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
>> s->cfg_ptr->vlenb,
>> s->cfg_ptr->vlenb, data, fns[s->sew]);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -3201,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
>> require_align(a->rd, s->lmul) &&
>> require_vm(a->vm, a->rd)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> @@ -3217,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
>> s->cfg_ptr->vlenb,
>> data, fns[s->sew]);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -3386,9 +3287,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
>> /* This instruction ignores LMUL and vector register groups */
>> TCGv_i64 t1;
>> TCGv s1;
>> - TCGLabel *over = gen_new_label();
>> -
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> t1 = tcg_temp_new_i64();
>>
>> @@ -3400,7 +3298,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
>> tcg_gen_ext_tl_i64(t1, s1);
>> vec_element_storei(s, a->rd, 0, t1);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -3442,10 +3339,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>>
>> /* The instructions ignore LMUL and vector register group. */
>> TCGv_i64 t1;
>> - TCGLabel *over = gen_new_label();
>> -
>> - /* if vstart >= vl, skip vector register write back */
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> /* NaN-box f[rs1] */
>> t1 = tcg_temp_new_i64();
>> @@ -3453,7 +3346,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>>
>> vec_element_storei(s, a->rd, 0, t1);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -3624,8 +3516,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
>> gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
>> gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
>> };
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>> data = FIELD_DP32(data, VDATA, VTA, s->vta);
>> @@ -3635,7 +3525,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
>> s->cfg_ptr->vlenb, data,
>> fns[s->sew]);
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -3658,12 +3547,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
>> vreg_ofs(s, a->rs2), maxsz, maxsz); \
>> mark_vs_dirty(s); \
>> } else { \
>> - TCGLabel *over = gen_new_label(); \
>> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
>> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
>> tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> } \
>> return true; \
>> } \
>> @@ -3692,8 +3578,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
>> {
>> uint32_t data = 0;
>> gen_helper_gvec_3_ptr *fn;
>> - TCGLabel *over = gen_new_label();
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>
>> static gen_helper_gvec_3_ptr * const fns[6][4] = {
>> {
>> @@ -3738,7 +3622,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
>> s->cfg_ptr->vlenb, data, fn);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>>
>> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
>> index a5cdd1b67f..6d640e4596 100644
>> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
>> @@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
>> gen_helper_##NAME##_w, \
>> gen_helper_##NAME##_d, \
>> }; \
>> - TCGLabel *over = gen_new_label(); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>> @@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
>> s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
>> data, fns[s->sew]); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
>> TCGv_ptr rd_v, rs2_v; \
>> TCGv_i32 desc, egs; \
>> uint32_t data = 0; \
>> - TCGLabel *over = gen_new_label(); \
>> \
>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>> /* save opcode for unwinding in case we throw an exception */ \
>> decode_save_opc(s); \
>> egs = tcg_constant_i32(EGS); \
>> gen_helper_egs_check(egs, tcg_env); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> } \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> @@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
>> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
>> gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>> TCGv_ptr rd_v, rs2_v; \
>> TCGv_i32 uimm_v, desc, egs; \
>> uint32_t data = 0; \
>> - TCGLabel *over = gen_new_label(); \
>> \
>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>> /* save opcode for unwinding in case we throw an exception */ \
>> decode_save_opc(s); \
>> egs = tcg_constant_i32(EGS); \
>> gen_helper_egs_check(egs, tcg_env); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> } \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> @@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
>> gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>> { \
>> if (CHECK(s, a)) { \
>> uint32_t data = 0; \
>> - TCGLabel *over = gen_new_label(); \
>> TCGv_i32 egs; \
>> \
>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>> @@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>> decode_save_opc(s); \
>> egs = tcg_constant_i32(EGS); \
>> gen_helper_egs_check(egs, tcg_env); \
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>> } \
>> \
>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>> @@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>> data, gen_helper_##NAME); \
>> \
>> mark_vs_dirty(s); \
>> - gen_set_label(over); \
>> return true; \
>> } \
>> return false; \
>> @@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>> {
>> if (vsha_check(s, a)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> TCGv_i32 egs;
>>
>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
>> @@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>> decode_save_opc(s);
>> egs = tcg_constant_i32(ZVKNH_EGS);
>> gen_helper_egs_check(egs, tcg_env);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> }
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> @@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>> gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
>> @@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>> {
>> if (vsha_check(s, a)) {
>> uint32_t data = 0;
>> - TCGLabel *over = gen_new_label();
>> TCGv_i32 egs;
>>
>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
>> @@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>> decode_save_opc(s);
>> egs = tcg_constant_i32(ZVKNH_EGS);
>> gen_helper_egs_check(egs, tcg_env);
>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>> }
>>
>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>> @@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>> gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
>>
>> mark_vs_dirty(s);
>> - gen_set_label(over);
>> return true;
>> }
>> return false;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
2024-03-08 10:39 ` Daniel Henrique Barboza
@ 2024-03-08 11:13 ` Alistair Francis
2024-03-08 11:23 ` Daniel Henrique Barboza
0 siblings, 1 reply; 16+ messages in thread
From: Alistair Francis @ 2024-03-08 11:13 UTC (permalink / raw
To: Daniel Henrique Barboza
Cc: LIU Zhiwei, qemu-devel, qemu-riscv, alistair.francis, bmeng,
liwei1518, palmer, Richard Henderson
On Fri, Mar 8, 2024 at 8:40 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 3/8/24 00:34, LIU Zhiwei wrote:
> > Hi Daniel and Alistair,
> >
> > Hope it is not too late. I think there are two bugs in this patch.
> >
> > 1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper function. If we remove the over check, it will set the first element of destination vector register, which is against the specification. According to the riscv-v-specification, 16.2. Floating-Point Scalar Move Instructions,
> >
> > "If vstart ≥ vl, no operation is performed and the destination register is not updated".
>
> vfmv.s.f seems to have biggers problems: it's not setting env->vstart at any
> point. In fact, in a quick look, there's a handful of cases where this is happening:
> trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f.
>
> I'll need an extra patch to fix them. We'll probably need to keep the cpu_vstart
> and cpu_vl globals, and use brconds, to be able to handle the vstart >= vl
> scenario that happens with them (since they don't use helpers).
>
> >
> > 2) The second is for vector instruction with helper functions. we should not change any elements including the tail elements when vstart >=vl. But this patch break this behavior. According to the riscv-v-specification, 5.4. Prestart, Active, Inactive, Body, and Tail Element Denitions,
> >
> > "When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group,
> > including that no tail elements are updated with agnostic values."
>
> Every helper in vector_helper.c has a pattern like:
>
> (--- set variables ---)
>
> for (i = env->vstart; i < vl; i++) {
> /* do things */
> }
> env->vstart = 0;
> vext_set_elems_1s() /*set tail */
>
>
> When vstart >= vl there is no body elements and no tail, but I'm not sure about
> vext_set_elems_1s() being able to handle that. In particular because we're setting
> vstart=0 before calling it.
>
> I'll add an additional patch to only call vext_set_elems_1s() to set the tail if
> start < vl.
I dropped this and later patches from my latest PR (which is sending
now). I was trying to get it ready today so when I saw the concern I
dropped it to be safe.
It's Friday night here, so I'll have a look at this next week. Should
still be able to get it in for 9.0
Alistair
>
> All this work with these changes is to put the 'vstart' management in a single place,
> i.e. the helper (when available). Then the translations can freely set
> vstart_eq_zero in the end (i.e. no exceptions/faults) knowing that the execution
> code zeroed vstart. It's clearer than having the helper make assumptions (i.e.
> vstart < vl) that were made during the translation. If the helper is setting
> vstart = 0 the helper must also deal with any invalid value of vstart accordingly.
>
>
> Thanks,
>
>
> Daniel
>
>
> >
> > I will review this patch set in more details later.
> >
> > Thanks,
> > Zhiwei
> >
> > On 2024/3/7 1:19, Daniel Henrique Barboza wrote:
> >> Most of the vector translations has this following pattern at the start:
> >>
> >> TCGLabel *over = gen_new_label();
> >> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> And then right at the end:
> >>
> >> gen_set_label(over);
> >> return true;
> >>
> >> This means that if vstart >= vl we'll not set vstart = 0 at the end of
> >> the insns - this is done inside the helper that is being skipped. The
> >> reason why this pattern hasn't been a bigger problem is because the
> >> conditional vstart >= vl is very rare.
> >>
> >> Checking all the helpers in vector_helper.c we see all of them with a
> >> pattern like this:
> >>
> >> for (i = env->vstart; i < vl; i++) {
> >> (...)
> >> }
> >> env->vstart = 0;
> >>
> >> Thus they can handle vstart >= vl case gracefully, with the benefit of
> >> setting env->vstart = 0 during the process.
> >>
> >> Remove all 'over' conditionals and let the helper set env->vstart = 0
> >> every time.
> >>
> >> While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
> >> too since they're unneeded.
> >>
> >> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> >> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> >> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
> >> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> >> ---
> >> target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
> >> target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
> >> target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
> >> 3 files changed, 147 deletions(-)
> >>
> >> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
> >> index 8ee99df3f3..a842e76a6b 100644
> >> --- a/target/riscv/insn_trans/trans_rvbf16.c.inc
> >> +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
> >> @@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
> >>
> >> if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >>
> >> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> >> @@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
> >> ctx->cfg_ptr->vlenb, data,
> >> gen_helper_vfncvtbf16_f_f_w);
> >> mark_vs_dirty(ctx);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
> >>
> >> if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >>
> >> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> >> @@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
> >> ctx->cfg_ptr->vlenb, data,
> >> gen_helper_vfwcvtbf16_f_f_v);
> >> mark_vs_dirty(ctx);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
> >> if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
> >> vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >>
> >> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
> >> @@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
> >> ctx->cfg_ptr->vlenb, data,
> >> gen_helper_vfwmaccbf16_vv);
> >> mark_vs_dirty(ctx);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> >> index e42728990e..0114a132b3 100644
> >> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> >> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> >> @@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> >> TCGv base;
> >> TCGv_i32 desc;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> base = get_gpr(s, rs1, EXT_NONE);
> >> @@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> >> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> >> }
> >>
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
> >> TCGv base, stride;
> >> TCGv_i32 desc;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> base = get_gpr(s, rs1, EXT_NONE);
> >> @@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
> >>
> >> fn(dest, mask, base, stride, tcg_env, desc);
> >>
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> >> TCGv base;
> >> TCGv_i32 desc;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> index = tcg_temp_new_ptr();
> >> @@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> >>
> >> fn(dest, mask, base, index, tcg_env, desc);
> >>
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> >> TCGv base;
> >> TCGv_i32 desc;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> base = get_gpr(s, rs1, EXT_NONE);
> >> @@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> >> fn(dest, mask, base, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1100,10 +1084,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> >> uint32_t width, gen_helper_ldst_whole *fn,
> >> DisasContext *s)
> >> {
> >> - uint32_t evl = s->cfg_ptr->vlenb * nf / width;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> >> -
> >> TCGv_ptr dest;
> >> TCGv base;
> >> TCGv_i32 desc;
> >> @@ -1120,8 +1100,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> >>
> >> fn(dest, base, tcg_env, desc);
> >>
> >> - gen_set_label(over);
> >> -
> >> return true;
> >> }
> >>
> >> @@ -1195,10 +1173,6 @@ static inline bool
> >> do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> >> gen_helper_gvec_4_ptr *fn)
> >> {
> >> - TCGLabel *over = gen_new_label();
> >> -
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
> >> gvec_fn(s->sew, vreg_ofs(s, a->rd),
> >> vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
> >> @@ -1216,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
> >> s->cfg_ptr->vlenb, data, fn);
> >> }
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1248,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> >> TCGv_i32 desc;
> >> uint32_t data = 0;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> src2 = tcg_temp_new_ptr();
> >> @@ -1271,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> >> fn(dest, mask, src1, src2, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1410,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> >> TCGv_i32 desc;
> >> uint32_t data = 0;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> src2 = tcg_temp_new_ptr();
> >> @@ -1433,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> >> fn(dest, mask, src1, src2, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1495,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> >> {
> >> if (checkfn(s, a)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -1509,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> >> s->cfg_ptr->vlenb,
> >> data, fn);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -1571,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> >> {
> >> if (opiwv_widen_check(s, a)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -1584,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> >> tcg_env, s->cfg_ptr->vlenb,
> >> s->cfg_ptr->vlenb, data, fn);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -1643,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
> >> gen_helper_gvec_4_ptr *fn, DisasContext *s)
> >> {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -1655,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
> >> vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
> >> s->cfg_ptr->vlenb, data, fn);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -1834,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> gen_helper_##NAME##_h, \
> >> gen_helper_##NAME##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -1848,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2045,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> >> gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
> >> gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
> >> };
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> >> tcg_env, s->cfg_ptr->vlenb,
> >> s->cfg_ptr->vlenb, data,
> >> fns[s->sew]);
> >> - gen_set_label(over);
> >> }
> >> mark_vs_dirty(s);
> >> return true;
> >> @@ -2068,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> >> /* vmv.v.x has rs2 = 0 and vm = 1 */
> >> vext_check_ss(s, a->rd, 0, 1)) {
> >> TCGv s1;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> s1 = get_gpr(s, a->rs1, EXT_SIGN);
> >>
> >> @@ -2102,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> >> }
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -2129,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
> >> gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
> >> gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
> >> };
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> s1 = tcg_constant_i64(simm);
> >> dest = tcg_temp_new_ptr();
> >> @@ -2140,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
> >> fns[s->sew](dest, s1, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> }
> >> return true;
> >> }
> >> @@ -2275,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> gen_helper_##NAME##_w, \
> >> gen_helper_##NAME##_d, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm(s, RISCV_FRM_DYN); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2292,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew - 1]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2310,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> >> TCGv_i32 desc;
> >> TCGv_i64 t1;
> >>
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> -
> >> dest = tcg_temp_new_ptr();
> >> mask = tcg_temp_new_ptr();
> >> src2 = tcg_temp_new_ptr();
> >> @@ -2330,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> >> fn(dest, mask, t1, src2, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> @@ -2393,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> static gen_helper_gvec_4_ptr * const fns[2] = { \
> >> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm(s, RISCV_FRM_DYN); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2408,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew - 1]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2467,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> static gen_helper_gvec_4_ptr * const fns[2] = { \
> >> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm(s, RISCV_FRM_DYN); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2482,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew - 1]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2584,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> >> {
> >> if (checkfn(s, a)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> gen_set_rm_chkfrm(s, rm);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -2597,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> >> s->cfg_ptr->vlenb,
> >> s->cfg_ptr->vlenb, data, fn);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -2696,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> >> gen_helper_vmv_v_x_w,
> >> gen_helper_vmv_v_x_d,
> >> };
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> t1 = tcg_temp_new_i64();
> >> /* NaN-box f[rs1] */
> >> @@ -2711,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> >> fns[s->sew - 1](dest, t1, tcg_env, desc);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> }
> >> return true;
> >> }
> >> @@ -2773,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> gen_helper_##HELPER##_h, \
> >> gen_helper_##HELPER##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm_chkfrm(s, FRM); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2787,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew - 1]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2824,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> gen_helper_##NAME##_h, \
> >> gen_helper_##NAME##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm(s, RISCV_FRM_DYN); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2838,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2891,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> gen_helper_##HELPER##_h, \
> >> gen_helper_##HELPER##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm_chkfrm(s, FRM); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2905,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew - 1]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -2940,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> gen_helper_##HELPER##_h, \
> >> gen_helper_##HELPER##_w, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> gen_set_rm_chkfrm(s, FRM); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -2954,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->cfg_ptr->vlenb, data, \
> >> fns[s->sew]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -3031,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> >> vext_check_isa_ill(s)) { \
> >> uint32_t data = 0; \
> >> gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
> >> - TCGLabel *over = gen_new_label(); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> data = \
> >> @@ -3043,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> >> s->cfg_ptr->vlenb, \
> >> s->cfg_ptr->vlenb, data, fn); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -3131,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->vstart_eq_zero) { \
> >> uint32_t data = 0; \
> >> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
> >> - TCGLabel *over = gen_new_label(); \
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -3145,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> >> s->cfg_ptr->vlenb, \
> >> data, fn); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -3171,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> >> require_align(a->rd, s->lmul) &&
> >> s->vstart_eq_zero) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -3187,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
> >> s->cfg_ptr->vlenb,
> >> s->cfg_ptr->vlenb, data, fns[s->sew]);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -3201,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> >> require_align(a->rd, s->lmul) &&
> >> require_vm(a->vm, a->rd)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> @@ -3217,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> >> s->cfg_ptr->vlenb,
> >> data, fns[s->sew]);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -3386,9 +3287,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> >> /* This instruction ignores LMUL and vector register groups */
> >> TCGv_i64 t1;
> >> TCGv s1;
> >> - TCGLabel *over = gen_new_label();
> >> -
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> t1 = tcg_temp_new_i64();
> >>
> >> @@ -3400,7 +3298,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> >> tcg_gen_ext_tl_i64(t1, s1);
> >> vec_element_storei(s, a->rd, 0, t1);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -3442,10 +3339,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
> >>
> >> /* The instructions ignore LMUL and vector register group. */
> >> TCGv_i64 t1;
> >> - TCGLabel *over = gen_new_label();
> >> -
> >> - /* if vstart >= vl, skip vector register write back */
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> /* NaN-box f[rs1] */
> >> t1 = tcg_temp_new_i64();
> >> @@ -3453,7 +3346,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
> >>
> >> vec_element_storei(s, a->rd, 0, t1);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -3624,8 +3516,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> >> gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
> >> gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
> >> };
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> >>
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> >> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> >> @@ -3635,7 +3525,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> >> s->cfg_ptr->vlenb, data,
> >> fns[s->sew]);
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -3658,12 +3547,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> >> vreg_ofs(s, a->rs2), maxsz, maxsz); \
> >> mark_vs_dirty(s); \
> >> } else { \
> >> - TCGLabel *over = gen_new_label(); \
> >> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
> >> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
> >> tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> } \
> >> return true; \
> >> } \
> >> @@ -3692,8 +3578,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> >> {
> >> uint32_t data = 0;
> >> gen_helper_gvec_3_ptr *fn;
> >> - TCGLabel *over = gen_new_label();
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >>
> >> static gen_helper_gvec_3_ptr * const fns[6][4] = {
> >> {
> >> @@ -3738,7 +3622,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> >> s->cfg_ptr->vlenb, data, fn);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >>
> >> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
> >> index a5cdd1b67f..6d640e4596 100644
> >> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
> >> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
> >> @@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
> >> gen_helper_##NAME##_w, \
> >> gen_helper_##NAME##_d, \
> >> }; \
> >> - TCGLabel *over = gen_new_label(); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> >> @@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
> >> s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
> >> data, fns[s->sew]); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
> >> TCGv_ptr rd_v, rs2_v; \
> >> TCGv_i32 desc, egs; \
> >> uint32_t data = 0; \
> >> - TCGLabel *over = gen_new_label(); \
> >> \
> >> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> >> /* save opcode for unwinding in case we throw an exception */ \
> >> decode_save_opc(s); \
> >> egs = tcg_constant_i32(EGS); \
> >> gen_helper_egs_check(egs, tcg_env); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> } \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> @@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
> >> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
> >> gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
> >> TCGv_ptr rd_v, rs2_v; \
> >> TCGv_i32 uimm_v, desc, egs; \
> >> uint32_t data = 0; \
> >> - TCGLabel *over = gen_new_label(); \
> >> \
> >> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> >> /* save opcode for unwinding in case we throw an exception */ \
> >> decode_save_opc(s); \
> >> egs = tcg_constant_i32(EGS); \
> >> gen_helper_egs_check(egs, tcg_env); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> } \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> @@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
> >> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
> >> gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> >> { \
> >> if (CHECK(s, a)) { \
> >> uint32_t data = 0; \
> >> - TCGLabel *over = gen_new_label(); \
> >> TCGv_i32 egs; \
> >> \
> >> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
> >> @@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> >> decode_save_opc(s); \
> >> egs = tcg_constant_i32(EGS); \
> >> gen_helper_egs_check(egs, tcg_env); \
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> >> } \
> >> \
> >> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> >> @@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
> >> data, gen_helper_##NAME); \
> >> \
> >> mark_vs_dirty(s); \
> >> - gen_set_label(over); \
> >> return true; \
> >> } \
> >> return false; \
> >> @@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> >> {
> >> if (vsha_check(s, a)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> TCGv_i32 egs;
> >>
> >> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> >> @@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> >> decode_save_opc(s);
> >> egs = tcg_constant_i32(ZVKNH_EGS);
> >> gen_helper_egs_check(egs, tcg_env);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> }
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> @@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
> >> gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
> >> @@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> >> {
> >> if (vsha_check(s, a)) {
> >> uint32_t data = 0;
> >> - TCGLabel *over = gen_new_label();
> >> TCGv_i32 egs;
> >>
> >> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> >> @@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> >> decode_save_opc(s);
> >> egs = tcg_constant_i32(ZVKNH_EGS);
> >> gen_helper_egs_check(egs, tcg_env);
> >> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> >> }
> >>
> >> data = FIELD_DP32(data, VDATA, VM, a->vm);
> >> @@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
> >> gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
> >>
> >> mark_vs_dirty(s);
> >> - gen_set_label(over);
> >> return true;
> >> }
> >> return false;
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
2024-03-08 11:13 ` Alistair Francis
@ 2024-03-08 11:23 ` Daniel Henrique Barboza
0 siblings, 0 replies; 16+ messages in thread
From: Daniel Henrique Barboza @ 2024-03-08 11:23 UTC (permalink / raw
To: Alistair Francis
Cc: LIU Zhiwei, qemu-devel, qemu-riscv, alistair.francis, bmeng,
liwei1518, palmer, Richard Henderson
On 3/8/24 08:13, Alistair Francis wrote:
> On Fri, Mar 8, 2024 at 8:40 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>>
>>
>> On 3/8/24 00:34, LIU Zhiwei wrote:
>>> Hi Daniel and Alistair,
>>>
>>> Hope it is not too late. I think there are two bugs in this patch.
>>>
>>> 1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper function. If we remove the over check, it will set the first element of destination vector register, which is against the specification. According to the riscv-v-specification, 16.2. Floating-Point Scalar Move Instructions,
>>>
>>> "If vstart ≥ vl, no operation is performed and the destination register is not updated".
>>
>> vfmv.s.f seems to have biggers problems: it's not setting env->vstart at any
>> point. In fact, in a quick look, there's a handful of cases where this is happening:
>> trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f.
>>
>> I'll need an extra patch to fix them. We'll probably need to keep the cpu_vstart
>> and cpu_vl globals, and use brconds, to be able to handle the vstart >= vl
>> scenario that happens with them (since they don't use helpers).
>>
>>>
>>> 2) The second is for vector instruction with helper functions. we should not change any elements including the tail elements when vstart >=vl. But this patch break this behavior. According to the riscv-v-specification, 5.4. Prestart, Active, Inactive, Body, and Tail Element Denitions,
>>>
>>> "When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group,
>>> including that no tail elements are updated with agnostic values."
>>
>> Every helper in vector_helper.c has a pattern like:
>>
>> (--- set variables ---)
>>
>> for (i = env->vstart; i < vl; i++) {
>> /* do things */
>> }
>> env->vstart = 0;
>> vext_set_elems_1s() /*set tail */
>>
>>
>> When vstart >= vl there is no body elements and no tail, but I'm not sure about
>> vext_set_elems_1s() being able to handle that. In particular because we're setting
>> vstart=0 before calling it.
>>
>> I'll add an additional patch to only call vext_set_elems_1s() to set the tail if
>> start < vl.
>
> I dropped this and later patches from my latest PR (which is sending
> now). I was trying to get it ready today so when I saw the concern I
> dropped it to be safe.
I think it's the right call.
>
> It's Friday night here, so I'll have a look at this next week. Should
> still be able to get it in for 9.0
I'll see if I can send a new version today but, given than these are cleanups
needed for bug fixes, I'd say they are ok to be merged after the soft freeze.
Thanks,
Daniel
>
> Alistair
>
>>
>> All this work with these changes is to put the 'vstart' management in a single place,
>> i.e. the helper (when available). Then the translations can freely set
>> vstart_eq_zero in the end (i.e. no exceptions/faults) knowing that the execution
>> code zeroed vstart. It's clearer than having the helper make assumptions (i.e.
>> vstart < vl) that were made during the translation. If the helper is setting
>> vstart = 0 the helper must also deal with any invalid value of vstart accordingly.
>>
>>
>> Thanks,
>>
>>
>> Daniel
>>
>>
>>>
>>> I will review this patch set in more details later.
>>>
>>> Thanks,
>>> Zhiwei
>>>
>>> On 2024/3/7 1:19, Daniel Henrique Barboza wrote:
>>>> Most of the vector translations has this following pattern at the start:
>>>>
>>>> TCGLabel *over = gen_new_label();
>>>> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> And then right at the end:
>>>>
>>>> gen_set_label(over);
>>>> return true;
>>>>
>>>> This means that if vstart >= vl we'll not set vstart = 0 at the end of
>>>> the insns - this is done inside the helper that is being skipped. The
>>>> reason why this pattern hasn't been a bigger problem is because the
>>>> conditional vstart >= vl is very rare.
>>>>
>>>> Checking all the helpers in vector_helper.c we see all of them with a
>>>> pattern like this:
>>>>
>>>> for (i = env->vstart; i < vl; i++) {
>>>> (...)
>>>> }
>>>> env->vstart = 0;
>>>>
>>>> Thus they can handle vstart >= vl case gracefully, with the benefit of
>>>> setting env->vstart = 0 during the process.
>>>>
>>>> Remove all 'over' conditionals and let the helper set env->vstart = 0
>>>> every time.
>>>>
>>>> While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
>>>> too since they're unneeded.
>>>>
>>>> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>>>> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
>>>> Reviewed-by: Richard Henderson<richard.henderson@linaro.org>
>>>> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
>>>> ---
>>>> target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
>>>> target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
>>>> target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
>>>> 3 files changed, 147 deletions(-)
>>>>
>>>> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
>>>> index 8ee99df3f3..a842e76a6b 100644
>>>> --- a/target/riscv/insn_trans/trans_rvbf16.c.inc
>>>> +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
>>>> @@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
>>>>
>>>> if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>>
>>>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>>>> @@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
>>>> ctx->cfg_ptr->vlenb, data,
>>>> gen_helper_vfncvtbf16_f_f_w);
>>>> mark_vs_dirty(ctx);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
>>>>
>>>> if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>>
>>>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>>>> @@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
>>>> ctx->cfg_ptr->vlenb, data,
>>>> gen_helper_vfwcvtbf16_f_f_v);
>>>> mark_vs_dirty(ctx);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
>>>> if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
>>>> vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>>
>>>> gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
>>>> @@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
>>>> ctx->cfg_ptr->vlenb, data,
>>>> gen_helper_vfwmaccbf16_vv);
>>>> mark_vs_dirty(ctx);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
>>>> index e42728990e..0114a132b3 100644
>>>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>>>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>>>> @@ -616,9 +616,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>>>> TCGv base;
>>>> TCGv_i32 desc;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> base = get_gpr(s, rs1, EXT_NONE);
>>>> @@ -660,7 +657,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>>>> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
>>>> }
>>>>
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -802,9 +798,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>>>> TCGv base, stride;
>>>> TCGv_i32 desc;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> base = get_gpr(s, rs1, EXT_NONE);
>>>> @@ -819,7 +812,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>>>>
>>>> fn(dest, mask, base, stride, tcg_env, desc);
>>>>
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -906,9 +898,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>>>> TCGv base;
>>>> TCGv_i32 desc;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> index = tcg_temp_new_ptr();
>>>> @@ -924,7 +913,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>>>>
>>>> fn(dest, mask, base, index, tcg_env, desc);
>>>>
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1044,9 +1032,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>>>> TCGv base;
>>>> TCGv_i32 desc;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> base = get_gpr(s, rs1, EXT_NONE);
>>>> @@ -1059,7 +1044,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>>>> fn(dest, mask, base, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1100,10 +1084,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
>>>> uint32_t width, gen_helper_ldst_whole *fn,
>>>> DisasContext *s)
>>>> {
>>>> - uint32_t evl = s->cfg_ptr->vlenb * nf / width;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
>>>> -
>>>> TCGv_ptr dest;
>>>> TCGv base;
>>>> TCGv_i32 desc;
>>>> @@ -1120,8 +1100,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
>>>>
>>>> fn(dest, base, tcg_env, desc);
>>>>
>>>> - gen_set_label(over);
>>>> -
>>>> return true;
>>>> }
>>>>
>>>> @@ -1195,10 +1173,6 @@ static inline bool
>>>> do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
>>>> gen_helper_gvec_4_ptr *fn)
>>>> {
>>>> - TCGLabel *over = gen_new_label();
>>>> -
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
>>>> gvec_fn(s->sew, vreg_ofs(s, a->rd),
>>>> vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
>>>> @@ -1216,7 +1190,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
>>>> s->cfg_ptr->vlenb, data, fn);
>>>> }
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1248,9 +1221,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
>>>> TCGv_i32 desc;
>>>> uint32_t data = 0;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> src2 = tcg_temp_new_ptr();
>>>> @@ -1271,7 +1241,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
>>>> fn(dest, mask, src1, src2, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1410,9 +1379,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
>>>> TCGv_i32 desc;
>>>> uint32_t data = 0;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> src2 = tcg_temp_new_ptr();
>>>> @@ -1433,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
>>>> fn(dest, mask, src1, src2, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1495,8 +1460,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
>>>> {
>>>> if (checkfn(s, a)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -1509,7 +1472,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
>>>> s->cfg_ptr->vlenb,
>>>> data, fn);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -1571,8 +1533,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
>>>> {
>>>> if (opiwv_widen_check(s, a)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -1584,7 +1544,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
>>>> tcg_env, s->cfg_ptr->vlenb,
>>>> s->cfg_ptr->vlenb, data, fn);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -1643,8 +1602,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
>>>> gen_helper_gvec_4_ptr *fn, DisasContext *s)
>>>> {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -1655,7 +1612,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
>>>> vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
>>>> s->cfg_ptr->vlenb, data, fn);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -1834,8 +1790,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> gen_helper_##NAME##_h, \
>>>> gen_helper_##NAME##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -1848,7 +1802,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2045,14 +1998,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
>>>> gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
>>>> gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
>>>> };
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
>>>> tcg_env, s->cfg_ptr->vlenb,
>>>> s->cfg_ptr->vlenb, data,
>>>> fns[s->sew]);
>>>> - gen_set_label(over);
>>>> }
>>>> mark_vs_dirty(s);
>>>> return true;
>>>> @@ -2068,8 +2018,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
>>>> /* vmv.v.x has rs2 = 0 and vm = 1 */
>>>> vext_check_ss(s, a->rd, 0, 1)) {
>>>> TCGv s1;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> s1 = get_gpr(s, a->rs1, EXT_SIGN);
>>>>
>>>> @@ -2102,7 +2050,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
>>>> }
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -2129,8 +2076,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
>>>> gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
>>>> gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
>>>> };
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> s1 = tcg_constant_i64(simm);
>>>> dest = tcg_temp_new_ptr();
>>>> @@ -2140,7 +2085,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
>>>> fns[s->sew](dest, s1, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> }
>>>> return true;
>>>> }
>>>> @@ -2275,9 +2219,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> gen_helper_##NAME##_w, \
>>>> gen_helper_##NAME##_d, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm(s, RISCV_FRM_DYN); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2292,7 +2234,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew - 1]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2310,9 +2251,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>>>> TCGv_i32 desc;
>>>> TCGv_i64 t1;
>>>>
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> -
>>>> dest = tcg_temp_new_ptr();
>>>> mask = tcg_temp_new_ptr();
>>>> src2 = tcg_temp_new_ptr();
>>>> @@ -2330,7 +2268,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
>>>> fn(dest, mask, t1, src2, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> @@ -2393,9 +2330,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> static gen_helper_gvec_4_ptr * const fns[2] = { \
>>>> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm(s, RISCV_FRM_DYN); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2408,7 +2343,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew - 1]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2467,9 +2401,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> static gen_helper_gvec_4_ptr * const fns[2] = { \
>>>> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm(s, RISCV_FRM_DYN); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2482,7 +2414,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew - 1]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2584,9 +2515,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
>>>> {
>>>> if (checkfn(s, a)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> gen_set_rm_chkfrm(s, rm);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -2597,7 +2526,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
>>>> s->cfg_ptr->vlenb,
>>>> s->cfg_ptr->vlenb, data, fn);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -2696,8 +2624,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>>>> gen_helper_vmv_v_x_w,
>>>> gen_helper_vmv_v_x_d,
>>>> };
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> t1 = tcg_temp_new_i64();
>>>> /* NaN-box f[rs1] */
>>>> @@ -2711,7 +2637,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>>>> fns[s->sew - 1](dest, t1, tcg_env, desc);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> }
>>>> return true;
>>>> }
>>>> @@ -2773,9 +2698,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> gen_helper_##HELPER##_h, \
>>>> gen_helper_##HELPER##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm_chkfrm(s, FRM); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2787,7 +2710,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew - 1]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2824,9 +2746,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> gen_helper_##NAME##_h, \
>>>> gen_helper_##NAME##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm(s, RISCV_FRM_DYN); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2838,7 +2758,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2891,9 +2810,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> gen_helper_##HELPER##_h, \
>>>> gen_helper_##HELPER##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm_chkfrm(s, FRM); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2905,7 +2822,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew - 1]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -2940,9 +2856,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> gen_helper_##HELPER##_h, \
>>>> gen_helper_##HELPER##_w, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> gen_set_rm_chkfrm(s, FRM); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -2954,7 +2868,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->cfg_ptr->vlenb, data, \
>>>> fns[s->sew]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -3031,8 +2944,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
>>>> vext_check_isa_ill(s)) { \
>>>> uint32_t data = 0; \
>>>> gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> data = \
>>>> @@ -3043,7 +2954,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
>>>> s->cfg_ptr->vlenb, \
>>>> s->cfg_ptr->vlenb, data, fn); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -3131,8 +3041,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->vstart_eq_zero) { \
>>>> uint32_t data = 0; \
>>>> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -3145,7 +3053,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
>>>> s->cfg_ptr->vlenb, \
>>>> data, fn); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -3171,8 +3078,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
>>>> require_align(a->rd, s->lmul) &&
>>>> s->vstart_eq_zero) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -3187,7 +3092,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
>>>> s->cfg_ptr->vlenb,
>>>> s->cfg_ptr->vlenb, data, fns[s->sew]);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -3201,8 +3105,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
>>>> require_align(a->rd, s->lmul) &&
>>>> require_vm(a->vm, a->rd)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> @@ -3217,7 +3119,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
>>>> s->cfg_ptr->vlenb,
>>>> data, fns[s->sew]);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -3386,9 +3287,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
>>>> /* This instruction ignores LMUL and vector register groups */
>>>> TCGv_i64 t1;
>>>> TCGv s1;
>>>> - TCGLabel *over = gen_new_label();
>>>> -
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> t1 = tcg_temp_new_i64();
>>>>
>>>> @@ -3400,7 +3298,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
>>>> tcg_gen_ext_tl_i64(t1, s1);
>>>> vec_element_storei(s, a->rd, 0, t1);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -3442,10 +3339,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>>>>
>>>> /* The instructions ignore LMUL and vector register group. */
>>>> TCGv_i64 t1;
>>>> - TCGLabel *over = gen_new_label();
>>>> -
>>>> - /* if vstart >= vl, skip vector register write back */
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> /* NaN-box f[rs1] */
>>>> t1 = tcg_temp_new_i64();
>>>> @@ -3453,7 +3346,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>>>>
>>>> vec_element_storei(s, a->rd, 0, t1);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -3624,8 +3516,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
>>>> gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
>>>> gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
>>>> };
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>>>>
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
>>>> data = FIELD_DP32(data, VDATA, VTA, s->vta);
>>>> @@ -3635,7 +3525,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
>>>> s->cfg_ptr->vlenb, data,
>>>> fns[s->sew]);
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -3658,12 +3547,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
>>>> vreg_ofs(s, a->rs2), maxsz, maxsz); \
>>>> mark_vs_dirty(s); \
>>>> } else { \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> - tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
>>>> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
>>>> tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> } \
>>>> return true; \
>>>> } \
>>>> @@ -3692,8 +3578,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
>>>> {
>>>> uint32_t data = 0;
>>>> gen_helper_gvec_3_ptr *fn;
>>>> - TCGLabel *over = gen_new_label();
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>>
>>>> static gen_helper_gvec_3_ptr * const fns[6][4] = {
>>>> {
>>>> @@ -3738,7 +3622,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
>>>> s->cfg_ptr->vlenb, data, fn);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>>
>>>> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
>>>> index a5cdd1b67f..6d640e4596 100644
>>>> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
>>>> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
>>>> @@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
>>>> gen_helper_##NAME##_w, \
>>>> gen_helper_##NAME##_d, \
>>>> }; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
>>>> @@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
>>>> s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
>>>> data, fns[s->sew]); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
>>>> TCGv_ptr rd_v, rs2_v; \
>>>> TCGv_i32 desc, egs; \
>>>> uint32_t data = 0; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> \
>>>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>>>> /* save opcode for unwinding in case we throw an exception */ \
>>>> decode_save_opc(s); \
>>>> egs = tcg_constant_i32(EGS); \
>>>> gen_helper_egs_check(egs, tcg_env); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> } \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> @@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
>>>> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
>>>> gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>>>> TCGv_ptr rd_v, rs2_v; \
>>>> TCGv_i32 uimm_v, desc, egs; \
>>>> uint32_t data = 0; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> \
>>>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>>>> /* save opcode for unwinding in case we throw an exception */ \
>>>> decode_save_opc(s); \
>>>> egs = tcg_constant_i32(EGS); \
>>>> gen_helper_egs_check(egs, tcg_env); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> } \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> @@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>>>> tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
>>>> gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>>>> { \
>>>> if (CHECK(s, a)) { \
>>>> uint32_t data = 0; \
>>>> - TCGLabel *over = gen_new_label(); \
>>>> TCGv_i32 egs; \
>>>> \
>>>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
>>>> @@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>>>> decode_save_opc(s); \
>>>> egs = tcg_constant_i32(EGS); \
>>>> gen_helper_egs_check(egs, tcg_env); \
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
>>>> } \
>>>> \
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm); \
>>>> @@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>>>> data, gen_helper_##NAME); \
>>>> \
>>>> mark_vs_dirty(s); \
>>>> - gen_set_label(over); \
>>>> return true; \
>>>> } \
>>>> return false; \
>>>> @@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>>>> {
>>>> if (vsha_check(s, a)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> TCGv_i32 egs;
>>>>
>>>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
>>>> @@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>>>> decode_save_opc(s);
>>>> egs = tcg_constant_i32(ZVKNH_EGS);
>>>> gen_helper_egs_check(egs, tcg_env);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> }
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> @@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>>>> gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>>> @@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>>>> {
>>>> if (vsha_check(s, a)) {
>>>> uint32_t data = 0;
>>>> - TCGLabel *over = gen_new_label();
>>>> TCGv_i32 egs;
>>>>
>>>> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
>>>> @@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>>>> decode_save_opc(s);
>>>> egs = tcg_constant_i32(ZVKNH_EGS);
>>>> gen_helper_egs_check(egs, tcg_env);
>>>> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>>>> }
>>>>
>>>> data = FIELD_DP32(data, VDATA, VM, a->vm);
>>>> @@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>>>> gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
>>>>
>>>> mark_vs_dirty(s);
>>>> - gen_set_label(over);
>>>> return true;
>>>> }
>>>> return false;
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-03-08 11:23 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-06 17:19 [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 2/9] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
2024-03-08 3:34 ` LIU Zhiwei
2024-03-08 10:39 ` Daniel Henrique Barboza
2024-03-08 11:13 ` Alistair Francis
2024-03-08 11:23 ` Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 4/9] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 5/9] target/riscv: remove 'cpu_vl' global Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 6/9] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
2024-03-06 20:42 ` Philippe Mathieu-Daudé
2024-03-06 17:19 ` [PATCH v7 8/9] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
2024-03-06 17:19 ` [PATCH v7 9/9] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza
2024-03-07 0:37 ` [PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Alistair Francis
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