* [PATCH 1/5] andes: csr.h: Clean up CSR definition
@ 2023-12-25 13:05 Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 2/5] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-25 13:05 UTC (permalink / raw
To: u-boot; +Cc: randolph, peterlin, ycliang
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/include/asm/arch-andes/csr.h | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 393d51c6dd..93aa8b2343 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -15,17 +15,14 @@
#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc
-#define MCACHE_CTL_IC_EN_OFFSET 0
-#define MCACHE_CTL_DC_EN_OFFSET 1
-#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
-#define MCACHE_CTL_DC_COHEN_OFFSET 19
-#define MCACHE_CTL_DC_COHSTA_OFFSET 20
-
-#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
-#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
-#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
-#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
+/* mcache_ctl register */
+
+#define MCACHE_CTL_IC_EN BIT(0)
+#define MCACHE_CTL_DC_EN BIT(1)
+#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_DC_COHEN BIT(19)
+#define MCACHE_CTL_DC_COHSTA BIT(20)
+
#define CCTL_L1D_WBINVAL_ALL 6
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/5] andes: ae350: Implement cache switch via Kconfig
2023-12-25 13:05 [PATCH 1/5] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
@ 2023-12-25 13:05 ` Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 3/5] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-25 13:05 UTC (permalink / raw
To: u-boot; +Cc: randolph, peterlin, ycliang
Kconfig provides SYS_[I|D]CACHE_OFF config options
to switch off caches. Implement the corresponding options.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 9 +++++++--
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc..50cd31905d 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -32,8 +32,13 @@ void harts_early_init(void)
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
- MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+ mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \
+
+ if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+ mcache_ctl |= MCACHE_CTL_IC_EN;
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ mcache_ctl |= MCACHE_CTL_DC_EN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..bef9e3149e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
void spl_board_init()
{
/* enable v5l2 cache */
- enable_caches();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ enable_caches();
}
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/5] andes: cpu: Enable memboost feature
2023-12-25 13:05 [PATCH 1/5] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 2/5] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
@ 2023-12-25 13:05 ` Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 4/5] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 5/5] andes: ae350: Save cpu name to env Leo Yu-Chi Liang
3 siblings, 0 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-25 13:05 UTC (permalink / raw
To: u-boot; +Cc: randolph, peterlin, ycliang
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 7 +++++++
arch/riscv/include/asm/arch-andes/csr.h | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 50cd31905d..c9288dcb51 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \
+ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl |= MCACHE_CTL_IC_EN;
@@ -51,4 +54,8 @@ void harts_early_init(void)
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
}
}
+ mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+ csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
+ }
}
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 93aa8b2343..755504c3c4 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -20,9 +20,15 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/5] andes: cpu: Enable cache and TLB ECC support
2023-12-25 13:05 [PATCH 1/5] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 2/5] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 3/5] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
@ 2023-12-25 13:05 ` Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 5/5] andes: ae350: Save cpu name to env Leo Yu-Chi Liang
3 siblings, 0 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-25 13:05 UTC (permalink / raw
To: u-boot; +Cc: randolph, peterlin, ycliang
Andes CPU supports cache and TLB ECC.
Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 1 +
arch/riscv/include/asm/arch-andes/csr.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index c9288dcb51..c011c00a94 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -36,6 +36,7 @@ void harts_early_init(void)
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \
MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
+ MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl |= MCACHE_CTL_IC_EN;
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 755504c3c4..1a34618066 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -19,11 +19,14 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
+#define MCACHE_CTL_IC_ECCEN BIT(3)
+#define MCACHE_CTL_DC_ECCEN BIT(5)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
+#define MCACHE_CTL_TLB_ECCEN BIT(18)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 5/5] andes: ae350: Save cpu name to env
2023-12-25 13:05 [PATCH 1/5] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
` (2 preceding siblings ...)
2023-12-25 13:05 ` [PATCH 4/5] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
@ 2023-12-25 13:05 ` Leo Yu-Chi Liang
3 siblings, 0 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-25 13:05 UTC (permalink / raw
To: u-boot; +Cc: randolph, peterlin, ycliang
Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
board/AndesTech/ae350/ae350.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index bef9e3149e..9faf46d96e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -28,6 +28,26 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
+int misc_init_r(void)
+{
+ long csr_marchid = 0;
+ const long mask_64 = 0x8000;
+ const long mask_cpu = 0xff;
+ char cpu_name[10] = {};
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+ sbi_get_marchid(&csr_marchid);
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+ csr_marchid = csr_read(CSR_MARCHID);
+#endif
+ if (mask_64 & csr_marchid)
+ snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid));
+ else
+ snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
+
+ return env_set("cpu", cpu_name);
+}
+
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
void spl_perform_fixups(struct spl_image_info *spl_image)
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-12-25 13:06 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2023-12-25 13:05 [PATCH 1/5] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 2/5] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 3/5] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 4/5] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
2023-12-25 13:05 ` [PATCH 5/5] andes: ae350: Save cpu name to env Leo Yu-Chi Liang
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