* [PULL 0/8] target-arm queue
@ 2023-11-21 10:24 Peter Maydell
2023-11-21 10:24 ` [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Peter Maydell
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
Hi; here are some arm patches for rc1; all small bug fixes and cleanups.
thanks
-- PMM
The following changes since commit af9264da80073435fd78944bc5a46e695897d7e5:
Merge tag '20231119-xtensa-1' of https://github.com/OSLL/qemu-xtensa into staging (2023-11-20 05:25:19 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231121
for you to fetch changes up to 0cbb56c236a4a28f5149eed227d74bb737321cfc:
hw/arm/fsl-imx: Do not ignore Error argument (2023-11-20 15:34:19 +0000)
----------------------------------------------------------------
target-arm queue:
* enable FEAT_RNG on Neoverse-N2
* hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
* Fix SME FMOPA (16-bit), BFMOPA
* hw/core/machine: Constify MachineClass::valid_cpu_types[]
* stm32f* machines: Report error when user asks for wrong CPU type
* hw/arm/fsl-imx: Do not ignore Error argument
----------------------------------------------------------------
Ben Dooks (1):
hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
Gavin Shan (1):
hw/core/machine: Constify MachineClass::valid_cpu_types[]
Marcin Juszkiewicz (1):
target/arm: enable FEAT_RNG on Neoverse-N2
Philippe Mathieu-Daudé (4):
hw/arm/stm32f405: Report error when incorrect CPU is used
hw/arm/stm32f205: Report error when incorrect CPU is used
hw/arm/stm32f100: Report error when incorrect CPU is used
hw/arm/fsl-imx: Do not ignore Error argument
Richard Henderson (1):
target/arm: Fix SME FMOPA (16-bit), BFMOPA
include/hw/arm/stm32f100_soc.h | 4 ----
include/hw/arm/stm32f205_soc.h | 4 ----
include/hw/arm/stm32f405_soc.h | 4 ----
include/hw/boards.h | 2 +-
hw/arm/fsl-imx25.c | 3 ++-
hw/arm/fsl-imx6.c | 3 ++-
hw/arm/netduino2.c | 7 ++++++-
hw/arm/netduinoplus2.c | 7 ++++++-
hw/arm/olimex-stm32-h405.c | 8 ++++++--
hw/arm/stm32f100_soc.c | 9 ++-------
hw/arm/stm32f205_soc.c | 9 ++-------
hw/arm/stm32f405_soc.c | 8 +-------
hw/arm/stm32vldiscovery.c | 7 ++++++-
hw/hppa/machine.c | 22 ++++++++++------------
hw/intc/arm_gicv3_cpuif.c | 4 ++--
hw/m68k/q800.c | 11 +++++------
target/arm/tcg/cpu64.c | 2 +-
target/arm/tcg/sme_helper.c | 10 ++++------
18 files changed, 56 insertions(+), 68 deletions(-)
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ Peter Maydell
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
Neoverse-N2.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231114103443.1652308-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 08db1dbcc74..fcda99e1583 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
- cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
+ cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
2023-11-21 10:24 ` [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA Peter Maydell
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Ben Dooks <ben.dooks@codethink.co.uk>
The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from
ic{c,v}_fullprio_mask should technically also remove any
bit above 7 as these are marked reserved (read 0) and should
therefore should not be written as anything other than 0.
This was noted during a run of a proprietary test system and
discused on the mailing list [1] and initially thought not to
be an issue due to RES0 being technically allowed to be
written to and read back as long as the implementation does
not use the RES0 bits. It is very possible that the values
are used in comparison without masking, as pointed out by
Peter in [2], if (cs->hppi.prio >= cs->icc_pmr_el1) may well
do the wrong thing.
Masking these values in ic{c,v}_fullprio_mask() should fix
this and prevent any future problems with playing with the
values.
[1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html
[2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index d07b13eb270..ab1a00508e6 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -146,7 +146,7 @@ static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
* with the group priority, whose mask depends on the value of VBPR
* for the interrupt group.)
*/
- return ~0U << (8 - cs->vpribits);
+ return (~0U << (8 - cs->vpribits)) & 0xff;
}
static int ich_highest_active_virt_prio(GICv3CPUState *cs)
@@ -803,7 +803,7 @@ static uint32_t icc_fullprio_mask(GICv3CPUState *cs)
* with the group priority, whose mask depends on the value of BPR
* for the interrupt group.)
*/
- return ~0U << (8 - cs->pribits);
+ return (~0U << (8 - cs->pribits)) & 0xff;
}
static inline int icc_min_bpr(GICv3CPUState *cs)
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
2023-11-21 10:24 ` [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Peter Maydell
2023-11-21 10:24 ` [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[] Peter Maydell
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Perform the loop increment unconditionally, not nested
within the predication.
Cc: qemu-stable@nongnu.org
Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1985
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231117193135.1180657-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/sme_helper.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 296826ffe6a..1ee2690ceb5 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1037,10 +1037,9 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
m = f16mop_adj_pair(m, pcol, 0);
*a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
-
- col += 4;
- pcol >>= 4;
}
+ col += 4;
+ pcol >>= 4;
} while (col & 15);
}
row += 4;
@@ -1073,10 +1072,9 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
m = f16mop_adj_pair(m, pcol, 0);
*a = bfdotadd(*a, n, m);
-
- col += 4;
- pcol >>= 4;
}
+ col += 4;
+ pcol >>= 4;
} while (col & 15);
}
row += 4;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[]
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2023-11-21 10:24 ` [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used Peter Maydell
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Gavin Shan <gshan@redhat.com>
Constify MachineClass::valid_cpu_types[i], as suggested by Richard
Henderson.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231117071704.35040-2-philmd@linaro.org
[PMD: Constify HPPA machines,
restrict valid_cpu_types to machine_class_init() handlers]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/boards.h | 2 +-
hw/hppa/machine.c | 22 ++++++++++------------
hw/m68k/q800.c | 11 +++++------
3 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a7359992980..da85f86efb9 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -273,7 +273,7 @@ struct MachineClass {
bool has_hotpluggable_cpus;
bool ignore_memory_transaction_failures;
int numa_mem_align_shift;
- const char **valid_cpu_types;
+ const char * const *valid_cpu_types;
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 9d08f39490e..c8da7c18d53 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error **errp)
}
}
-static const char *HP_B160L_machine_valid_cpu_types[] = {
- TYPE_HPPA_CPU,
- NULL
-};
-
static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ TYPE_HPPA_CPU,
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
mc->desc = "HP B160L workstation";
mc->default_cpu_type = TYPE_HPPA_CPU;
- mc->valid_cpu_types = HP_B160L_machine_valid_cpu_types;
+ mc->valid_cpu_types = valid_cpu_types;
mc->init = machine_HP_B160L_init;
mc->reset = hppa_machine_reset;
mc->block_default_type = IF_SCSI;
@@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = {
},
};
-static const char *HP_C3700_machine_valid_cpu_types[] = {
- TYPE_HPPA64_CPU,
- NULL
-};
-
static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ TYPE_HPPA64_CPU,
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
mc->desc = "HP C3700 workstation";
mc->default_cpu_type = TYPE_HPPA64_CPU;
- mc->valid_cpu_types = HP_C3700_machine_valid_cpu_types;
+ mc->valid_cpu_types = valid_cpu_types;
mc->init = machine_HP_C3700_init;
mc->reset = hppa_machine_reset;
mc->block_default_type = IF_SCSI;
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 1d7cd5ff1c3..83d1571d02f 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] = {
};
static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
-static const char *q800_machine_valid_cpu_types[] = {
- M68K_CPU_TYPE_NAME("m68040"),
- NULL
-};
-
static void q800_machine_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ M68K_CPU_TYPE_NAME("m68040"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Macintosh Quadra 800";
mc->init = q800_machine_init;
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
- mc->valid_cpu_types = q800_machine_valid_cpu_types;
+ mc->valid_cpu_types = valid_cpu_types;
mc->max_cpus = 1;
mc->block_default_type = IF_SCSI;
mc->default_ram_id = "m68k_mac.ram";
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2023-11-21 10:24 ` [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[] Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 6/8] hw/arm/stm32f205: " Peter Maydell
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
CPU type requested by the command line. This might confuse users,
since the following will create a machine with a Cortex-M4 CPU:
$ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.
We now get:
$ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu
The valid types are: cortex-m4-arm-cpu
Since the SoC family can only use Cortex-M4 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f405_soc.h | 4 ----
hw/arm/netduinoplus2.c | 7 ++++++-
hw/arm/olimex-stm32-h405.c | 8 ++++++--
hw/arm/stm32f405_soc.c | 8 +-------
4 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
index c968ce3ab23..d15c03c4b5d 100644
--- a/include/hw/arm/stm32f405_soc.h
+++ b/include/hw/arm/stm32f405_soc.h
@@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
#define CCM_SIZE (64 * 1024)
struct STM32F405State {
- /*< private >*/
SysBusDevice parent_obj;
- /*< public >*/
-
- char *cpu_type;
ARMv7MState armv7m;
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 515c0816054..2e589849478 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
- qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine)
static void netduinoplus2_machine_init(MachineClass *mc)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"),
+ NULL
+ };
+
mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
mc->init = netduinoplus2_init;
+ mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 3aa61c91b75..d793de7c97f 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
- qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine)
static void olimex_stm32_h405_machine_init(MachineClass *mc)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"),
+ NULL
+ };
+
mc->desc = "Olimex STM32-H405 (Cortex-M4)";
mc->init = olimex_stm32_h405_init;
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+ mc->valid_cpu_types = valid_cpu_types;
/* SRAM pre-allocated as part of the SoC instantiation */
mc->default_ram_size = 0;
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index cef23d7ee41..a65bbe298d2 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
- qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+ qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("RNG", 0x50060800, 0x400);
}
-static Property stm32f405_soc_properties[] = {
- DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f405_soc_realize;
- device_class_set_props(dc, stm32f405_soc_properties);
/* No vmstate or reset required: device has no internal state */
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 6/8] hw/arm/stm32f205: Report error when incorrect CPU is used
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2023-11-21 10:24 ` [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 7/8] hw/arm/stm32f100: " Peter Maydell
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The 'netduino2' machine ignores the CPU type requested by the
command line. This might confuse users, since the following will
create a machine with a Cortex-M3 CPU:
$ qemu-system-arm -M netduino2 -cpu cortex-a9
Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.
We now get:
$ qemu-system-arm -M netduino2 -cpu cortex-a9
qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu
The valid types are: cortex-m3-arm-cpu
Since the SoC family can only use Cortex-M3 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f205_soc.h | 4 ----
hw/arm/netduino2.c | 7 ++++++-
hw/arm/stm32f205_soc.c | 9 ++-------
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 5a4f7762642..4f4c8bbebc1 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC)
#define SRAM_SIZE (128 * 1024)
struct STM32F205State {
- /*< private >*/
SysBusDevice parent_obj;
- /*< public >*/
-
- char *cpu_type;
ARMv7MState armv7m;
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 83753d53a3f..501f63a77f9 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F205_SOC);
- qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine)
static void netduino2_machine_init(MachineClass *mc)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m3"),
+ NULL
+ };
+
mc->desc = "Netduino 2 Machine (Cortex-M3)";
mc->init = netduino2_init;
+ mc->valid_cpu_types = valid_cpu_types;
mc->ignore_memory_transaction_failures = true;
}
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index c6b75a381d9..1a548646f6e 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
- qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+ qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
}
}
-static Property stm32f205_soc_properties[] = {
- DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f205_soc_realize;
- device_class_set_props(dc, stm32f205_soc_properties);
+ /* No vmstate or reset required: device has no internal state */
}
static const TypeInfo stm32f205_soc_info = {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 7/8] hw/arm/stm32f100: Report error when incorrect CPU is used
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2023-11-21 10:24 ` [PULL 6/8] hw/arm/stm32f205: " Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 10:24 ` [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument Peter Maydell
2023-11-21 15:14 ` [PULL 0/8] target-arm queue Stefan Hajnoczi
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The 'stm32vldiscovery' machine ignores the CPU type requested by
the command line. This might confuse users, since the following
will create a machine with a Cortex-M3 CPU:
$ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1
Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.
We now get:
$ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1
qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu
The valid types are: cortex-m3-arm-cpu
Since the SoC family can only use Cortex-M3 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f100_soc.h | 4 ----
hw/arm/stm32f100_soc.c | 9 ++-------
hw/arm/stm32vldiscovery.c | 7 ++++++-
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
index 40cd415b284..a74d7b369c1 100644
--- a/include/hw/arm/stm32f100_soc.h
+++ b/include/hw/arm/stm32f100_soc.h
@@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
#define SRAM_SIZE (8 * 1024)
struct STM32F100State {
- /*< private >*/
SysBusDevice parent_obj;
- /*< public >*/
- char *cpu_type;
-
ARMv7MState armv7m;
STM32F2XXUsartState usart[STM_NUM_USARTS];
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index f7b344ba9fb..b90d440d7aa 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
/* Init ARMv7m */
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 61);
- qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+ qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
qdev_connect_clock_in(armv7m, "refclk", s->refclk);
@@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("CRC", 0x40023000, 0x400);
}
-static Property stm32f100_soc_properties[] = {
- DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f100_soc_realize;
- device_class_set_props(dc, stm32f100_soc_properties);
+ /* No vmstate or reset required: device has no internal state */
}
static const TypeInfo stm32f100_soc_info = {
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 67675e952fc..190db6118b9 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F100_SOC);
- qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine)
static void stm32vldiscovery_machine_init(MachineClass *mc)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m3"),
+ NULL
+ };
+
mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
mc->init = stm32vldiscovery_init;
+ mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2023-11-21 10:24 ` [PULL 7/8] hw/arm/stm32f100: " Peter Maydell
@ 2023-11-21 10:24 ` Peter Maydell
2023-11-21 15:14 ` [PULL 0/8] target-arm queue Stefan Hajnoczi
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2023-11-21 10:24 UTC (permalink / raw
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Both i.MX25 and i.MX6 SoC models ignore the Error argument when
setting the PHY number. Pick &error_abort which is the error
used by the i.MX7 SoC (see commit 1f7197deb0 "ability to change
the FEC PHY on i.MX7 processor").
Fixes: 74c1330582 ("ability to change the FEC PHY on i.MX25 processor")
Fixes: a9c167a3c4 ("ability to change the FEC PHY on i.MX6 processor")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231120115116.76858-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx25.c | 3 ++-
hw/arm/fsl-imx6.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 24c43745903..9aabbf7f587 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -169,7 +169,8 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
epit_table[i].irq));
}
- object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err);
+ object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num,
+ &error_abort);
qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) {
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 4fa7f0b95ed..7dc42cbfe64 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -379,7 +379,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
spi_table[i].irq));
}
- object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
+ object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
+ &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PULL 0/8] target-arm queue
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2023-11-21 10:24 ` [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument Peter Maydell
@ 2023-11-21 15:14 ` Stefan Hajnoczi
8 siblings, 0 replies; 10+ messages in thread
From: Stefan Hajnoczi @ 2023-11-21 15:14 UTC (permalink / raw
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-11-21 15:15 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-21 10:24 [PULL 0/8] target-arm queue Peter Maydell
2023-11-21 10:24 ` [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Peter Maydell
2023-11-21 10:24 ` [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ Peter Maydell
2023-11-21 10:24 ` [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA Peter Maydell
2023-11-21 10:24 ` [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[] Peter Maydell
2023-11-21 10:24 ` [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used Peter Maydell
2023-11-21 10:24 ` [PULL 6/8] hw/arm/stm32f205: " Peter Maydell
2023-11-21 10:24 ` [PULL 7/8] hw/arm/stm32f100: " Peter Maydell
2023-11-21 10:24 ` [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument Peter Maydell
2023-11-21 15:14 ` [PULL 0/8] target-arm queue Stefan Hajnoczi
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