* [PATCH V2 1/3] drm/amd/pm: fulfill SMU13.0.0 cstate control interface
@ 2022-10-12 6:32 Evan Quan
2022-10-12 6:32 ` [PATCH V2 2/3] drm/amd/pm: fulfill SMU13.0.7 " Evan Quan
2022-10-12 6:32 ` [PATCH V2 3/3] drm/amd/pm: disable cstate feature during smu cleanup Evan Quan
0 siblings, 2 replies; 3+ messages in thread
From: Evan Quan @ 2022-10-12 6:32 UTC (permalink / raw
To: amd-gfx; +Cc: Alexander.Deucher, Lijo.Lazar, Evan Quan, Hawking Zhang
Fulfill the functionality for cstate control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Change-Id: I2b7253898503b8051bbf90f429b46221410146b0
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 1d454485e0d9..29529328152d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -119,6 +119,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
+ MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
};
static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1753,6 +1754,15 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
return ret;
}
+static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
+ enum pp_df_cstate state)
+{
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_DFCstateControl,
+ state,
+ NULL);
+}
+
static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1822,6 +1832,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
.mode1_reset = smu_v13_0_mode1_reset,
.set_mp1_state = smu_v13_0_0_set_mp1_state,
+ .set_df_cstate = smu_v13_0_0_set_df_cstate,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH V2 2/3] drm/amd/pm: fulfill SMU13.0.7 cstate control interface
2022-10-12 6:32 [PATCH V2 1/3] drm/amd/pm: fulfill SMU13.0.0 cstate control interface Evan Quan
@ 2022-10-12 6:32 ` Evan Quan
2022-10-12 6:32 ` [PATCH V2 3/3] drm/amd/pm: disable cstate feature during smu cleanup Evan Quan
1 sibling, 0 replies; 3+ messages in thread
From: Evan Quan @ 2022-10-12 6:32 UTC (permalink / raw
To: amd-gfx; +Cc: Alexander.Deucher, Lijo.Lazar, Evan Quan, Hawking Zhang
Fulfill the functionality for cstate control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Change-Id: I3e7ec7d0434d3b34855a9267ab1989a3b85d5206
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index c422bf8a09b1..c4102cfb734c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -121,6 +121,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
+ MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
};
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
@@ -1587,6 +1588,16 @@ static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
return true;
}
+
+static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
+ enum pp_df_cstate state)
+{
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_DFCstateControl,
+ state,
+ NULL);
+}
+
static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1649,6 +1660,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
.mode1_reset = smu_v13_0_mode1_reset,
.set_mp1_state = smu_v13_0_7_set_mp1_state,
+ .set_df_cstate = smu_v13_0_7_set_df_cstate,
};
void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH V2 3/3] drm/amd/pm: disable cstate feature during smu cleanup
2022-10-12 6:32 [PATCH V2 1/3] drm/amd/pm: fulfill SMU13.0.0 cstate control interface Evan Quan
2022-10-12 6:32 ` [PATCH V2 2/3] drm/amd/pm: fulfill SMU13.0.7 " Evan Quan
@ 2022-10-12 6:32 ` Evan Quan
1 sibling, 0 replies; 3+ messages in thread
From: Evan Quan @ 2022-10-12 6:32 UTC (permalink / raw
To: amd-gfx; +Cc: Alexander.Deucher, Lijo.Lazar, Evan Quan, Hawking Zhang
This can address some reset failures observed on SMU13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Change-Id: Ieb4e204c49abd405b1dce559c2ff75bb3887b6f9
--
v1->v2:
- revise the code comments(Alex)
- limit this to SMU13.0.0 and 13.0.7
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 13c5c7f1ecb9..b0310b2e24f8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1443,13 +1443,20 @@ static int smu_disable_dpms(struct smu_context *smu)
((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
/*
- * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
- * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
+ * For SMU 13.0.0 and 13.0.7, per PMFW team's suggestion,
+ * driver needs to disable gfxoff and df cstate features(this
+ * can address some mode1 reset failures). For other features,
+ * PMFW will handle them properly.
*/
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
- return 0;
+ if (smu->ppt_funcs->set_df_cstate) {
+ ret = smu->ppt_funcs->set_df_cstate(smu, DF_CSTATE_DISALLOW);
+ if (ret)
+ dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
+ }
+ return ret;
default:
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-10-12 6:35 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2022-10-12 6:32 [PATCH V2 1/3] drm/amd/pm: fulfill SMU13.0.0 cstate control interface Evan Quan
2022-10-12 6:32 ` [PATCH V2 2/3] drm/amd/pm: fulfill SMU13.0.7 " Evan Quan
2022-10-12 6:32 ` [PATCH V2 3/3] drm/amd/pm: disable cstate feature during smu cleanup Evan Quan
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