On 12.06.2021 12:10:19, Fabio Estevam wrote:
> I am trying to run CAN stress tests on an i.MX8MM-based board that
> has two mcp2518fd chips. I am using linux-next 20210607 and this is
> the ecspi dts:
> 
> https://pastebin.com/raw/YVvuqAAc
>
> Then I launch the test script:
> ./cantest start
>
> This is the script content:
> https://pastebin.com/raw/hc8gKgUf
>
> The problem is that RX FIFO overflow happens:
>
> [  128.559485] mcp251xfd spi0.0 can0: RX-0: FIFO overflow.
> [  128.573478] mcp251xfd spi0.0 can0: RX-0: FIFO overflow.
> [  128.584787] mcp251xfd spi0.0 can0: RX-0: FIFO overflow.
>
> and also cansequence errors:
> # 2020-02-09 01:41:15:368 sequence CNT: 2779938, RX:      8    expected:  34    missing:  230    skt overfl d:    0 a:    0    delta: 230    incident: 6    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 136
> 2020-02-09 01:41:15:368 sequence CNT:      9, RX:     34    expected:   9    missing:   25    skt overfl d:   [  899.794388] mcp251xfd spi0.0 can0: RX-0: FIFO overflow.
>  0 a:    0    delta:  25    incident: 7    seq_wrap RX: 10860   [  899.804780] mcp251xfd spi0.0 can0: RX-0: FIFO overflow.
>   sequ_wrap_expected: 10860   overall lost: 161
> 2020-02-09 01:41:15:370 sequence CNT:     40, RX:      9    expected:  40    missing:  225    skt overfl d:    0 a:    0    delta: 225    incident: 8    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 130
> 2020-02-09 01:41:15:392 sequence CNT:    137, RX:    105    expected: 137    missing:  224    skt overfl d:    0 a:    0    delta: 224    incident: 9    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 98
> 2020-02-09 01:41:15:396 sequence CNT:    137, RX:    145    expected: 137    missing:    8    skt overfl d:    0 a:    0    delta:   8    incident: 10    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 106
> 2020-02-09 01:41:15:403 sequence CNT:    160, ERRORFRAME 20000004   00 01 00 00 00 00 00 00
> 2020-02-09 01:41:15:414 sequence CNT:    192, ERRORFRAME 20000004   00 01 00 00 00 00 00 00
> 2020-02-09 01:41:15:414 sequence CNT:    192, RX:    210    expected: 192    missing:   18    skt overfl d:    0 a:    0    delta:  18    incident: 11    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 124
> 2020-02-09 01:41:15:416 sequence CNT:    220, RX:    222    expected: 220    missing:    2    skt overfl d:    0 a:    0    delta:   2    incident: 12    seq_wrap RX: 10860     sequ_wrap_expected: 10860   overall lost: 126
>
> I have applied this series to get SPI DMA to work on i.MX8MM:
> https://patches.linaro.org/cover/417924/
>
> I have also tried SPI PIO mode instead of DMA, but it does not help.
>
> Any ideas of what can be done to improve this?

The imx SPI driver has quite some overhead, when it comes to small SPI
transfers. The mcp251fd driver performs much better with the SPI IP
cores on the raspi, which have quite good optimized drivers.

Hook up a scope to the SPI's clock and chip select lines of the imx,
you'll see the time between end of transfer until the chip select is
inactive is longer than the SPI transfer itself.

I expect most bang for the buck can be archived by adding an IRQ less
busy polling transfer mode, which kicks in below a certain SPI transfer
length.

On the mcp251xfd driver side, there is some room for optimization. The
basic idea is to reduce the number of SPI transfers by combining several
reads into one transfer. This can be done in some places.

For peak loads in CAN-2.0 mode it would be interesting to make use of
the remaining RAM for a 2nd FIFO.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde           |
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