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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v2 08/17] drm/i915: Store the HDMI default entry in the bug trans struct
Date: Tue,  8 Jun 2021 10:35:54 +0300	[thread overview]
Message-ID: <20210608073603.2408-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210608073603.2408-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Store the default HDMI buf trans entry in struct intel_ddi_buf_trans
so that it's next to the actual table. This let's us start ridding
ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries().

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_ddi_buf_trans.c    | 49 ++++++++++---------
 .../drm/i915/display/intel_ddi_buf_trans.h    |  1 +
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 95b8f9b43ea2..fd2216dc8c33 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -66,6 +66,7 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = {
 static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = {
 	.entries = _hsw_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi),
+	.hdmi_default_entry = 6,
 };
 
 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = {
@@ -136,6 +137,7 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = {
 static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = {
 	.entries = _bdw_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi),
+	.hdmi_default_entry = 7,
 };
 
 /* Skylake H and S */
@@ -330,6 +332,7 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = {
 static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = {
 	.entries = _skl_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi),
+	.hdmi_default_entry = 8,
 };
 
 /* Skylake/Kabylake Y */
@@ -350,6 +353,7 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = {
 static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = {
 	.entries = _skl_y_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi),
+	.hdmi_default_entry = 8,
 };
 
 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = {
@@ -410,6 +414,7 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = {
 static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
 	.entries = _bxt_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi),
+	.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
 };
 
 /* Voltage Swing Programming for VccIO 0.85V for DP */
@@ -447,6 +452,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[]
 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = {
 	.entries = _cnl_ddi_translations_hdmi_0_85V,
 	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V),
+	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1,
 };
 
 /* Voltage Swing Programming for VccIO 0.85V for eDP */
@@ -507,6 +513,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[]
 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = {
 	.entries = _cnl_ddi_translations_hdmi_0_95V,
 	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V),
+	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1,
 };
 
 /* Voltage Swing Programming for VccIO 0.95V for eDP */
@@ -568,6 +575,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[]
 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = {
 	.entries = _cnl_ddi_translations_hdmi_1_05V,
 	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V),
+	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1,
 };
 
 /* Voltage Swing Programming for VccIO 1.05V for eDP */
@@ -661,6 +669,7 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm
 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
 	.entries = _icl_combo_phy_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi),
+	.hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1,
 };
 
 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
@@ -813,6 +822,7 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[]
 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = {
 	.entries = _icl_mg_phy_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi),
+	.hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1,
 };
 
 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = {
@@ -870,6 +880,7 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[
 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
 	.entries = _tgl_dkl_phy_ddi_translations_hdmi,
 	.num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi),
+	.hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1,
 };
 
 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
@@ -1693,42 +1704,34 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	const struct intel_ddi_buf_trans *ddi_translations = NULL;
 	int n_entries;
 
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
+			ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
-		*default_entry = n_entries - 1;
+			ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 	} else if (DISPLAY_VER(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
+			ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
-		*default_entry = n_entries - 1;
+			ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		cnl_get_buf_trans_hdmi(encoder, &n_entries);
-		*default_entry = n_entries - 1;
+		ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
-		bxt_get_buf_trans_hdmi(encoder, &n_entries);
-		*default_entry = n_entries - 1;
-	} else if (DISPLAY_VER(dev_priv) == 9) {
-		hsw_get_buf_trans_hdmi(encoder, &n_entries);
-		*default_entry = 8;
-	} else if (IS_BROADWELL(dev_priv)) {
-		hsw_get_buf_trans_hdmi(encoder, &n_entries);
-		*default_entry = 7;
-	} else if (IS_HASWELL(dev_priv)) {
-		hsw_get_buf_trans_hdmi(encoder, &n_entries);
-		*default_entry = 6;
-	} else {
-		drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
-		return 0;
+		ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
+	} else if (DISPLAY_VER(dev_priv) == 9 ||
+		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+		ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries);
 	}
 
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
+	if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) {
+		*default_entry = 0;
 		return 0;
+	}
+
+	*default_entry = ddi_translations->hdmi_default_entry;
 
 	return n_entries;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 2ffa534010b3..879f1deec3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -56,6 +56,7 @@ union intel_ddi_buf_trans_entry {
 struct intel_ddi_buf_trans {
 	const union intel_ddi_buf_trans_entry *entries;
 	u8 num_entries;
+	u8 hdmi_default_entry;
 };
 
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table);
-- 
2.31.1

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  parent reply	other threads:[~2021-06-08  7:36 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-08  7:35 [Intel-gfx] [PATCH v2 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 01/17] drm/i915: s/intel/hsw/ for hsw/bdw/skl buf trans Ville Syrjala
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala
2021-06-18 12:04   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala
2021-06-18 12:04   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala
2021-06-18 12:05   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala
2021-06-18 12:08   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala
2021-06-18 12:11   ` Jani Nikula
2021-06-08  7:35 ` Ville Syrjala [this message]
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala
2021-06-18 12:19   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala
2021-06-18 12:22   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala
2021-06-18 12:28   ` Jani Nikula
2021-06-08  7:35 ` [Intel-gfx] [PATCH v2 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table Ville Syrjala
2021-06-18 12:30   ` Jani Nikula
2021-06-23 12:55     ` Ville Syrjälä
2021-06-08  7:36 ` [Intel-gfx] [PATCH v2 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala
2021-06-23 14:02   ` Jani Nikula
2021-06-08  7:36 ` [Intel-gfx] [PATCH v2 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala
2021-06-23 14:13   ` Jani Nikula
2021-06-24 17:05     ` Ville Syrjälä
2021-06-08  7:36 ` [Intel-gfx] [PATCH v2 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala
2021-06-23 14:14   ` Jani Nikula
2021-06-08  7:36 ` [Intel-gfx] [PATCH v2 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-06-23 14:36   ` Jani Nikula
2021-06-08  8:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev4) Patchwork
2021-06-08  8:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-08  9:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-08  9:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2021-06-08 13:33 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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