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From: Bin Meng <bmeng.cn@gmail.com>
To: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	U-Boot Mailing List <u-boot@lists.denx.de>
Subject: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
Date: Fri,  4 Jun 2021 13:51:12 +0800	[thread overview]
Message-ID: <20210604055113.3630286-4-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210604055113.3630286-1-bmeng.cn@gmail.com>

All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/dts/ae350_32.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0917b83108..70576846f2 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,7 @@
 
 		plic0: interrupt-controller@e4000000 {
 			compatible = "riscv,plic0";
-			#interrupt-cells = <1>;
+			#interrupt-cells = <2>;
 			interrupt-controller;
 			reg = <0xe4000000 0x2000000>;
 			riscv,ndev=<71>;
-- 
2.25.1


  parent reply	other threads:[~2021-06-04  5:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04  5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
2021-06-04  5:51 ` [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8768@ATCPCS12.andestech.com>
2021-06-09  6:56     ` Rick Chen
2021-06-15 15:58   ` Leo Liang
2021-06-04  5:51 ` [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B61@ATCPCS12.andestech.com>
2021-06-15  5:32     ` Rick Chen
2021-06-15 15:59   ` Leo Liang
2021-06-04  5:51 ` Bin Meng [this message]
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B6E@ATCPCS12.andestech.com>
2021-06-15  5:33     ` [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit Rick Chen
2021-06-15 16:00   ` Leo Liang
2021-06-04  5:51 ` [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8783@ATCPCS12.andestech.com>
2021-06-09  7:06     ` [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" " Rick Chen
2021-06-09  7:20       ` Bin Meng
2021-06-12 13:30         ` Rick Chen
2021-06-12 14:33           ` Bin Meng
2021-06-15  3:19             ` Rick Chen
2021-06-08  8:41 ` [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
2021-06-11  3:30 ` Leo Liang
     [not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA7FD5@ATCPCS12.andestech.com>
2021-06-15  3:33   ` Rick Chen

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