* [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's
@ 2021-01-17 12:50 Biju Das
2021-01-17 12:50 ` [PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Biju Das @ 2021-01-17 12:50 UTC (permalink / raw
To: u-boot
This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.
This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=224764
v9:
* Fixed make file to use default family type function for SPL builds
for both R-Car Gen{2,3} family's.
v8:
* Added Jaehoon Chung's Rb tag
* Optimized the cpu detection image size, when Renesas SoC identification
driver is disabled for R-Car Gen2 SPL builds
with v8:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
120 0 0 120 78 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
with v7:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
154 0 0 154 9a spl/arch/arm/mach-rmobile/cpu_info-rcar.o
v7:
* Incorporated Jaehoon Chung's review comments.
* Fixed the build error on Renesas ARM32 platforms.
* Seperated driver patch series from board support patches.
v6:
* Optimized the unique CPU identification method by using Renesas SoC identification driver.
* quirks using soc_device_match.
Biju Das (4):
arm: rmobile: Add RZ/G2[HMNE] SoC support
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
arch/arm/mach-rmobile/Makefile | 5 +
arch/arm/mach-rmobile/cpu_info-rcar.c | 20 ++-
arch/arm/mach-rmobile/cpu_info.c | 12 +-
arch/arm/mach-rmobile/include/mach/rmobile.h | 63 ++++++--
arch/arm/mach-rmobile/soc_family-info.c | 21 +++
drivers/mmc/renesas-sdhi.c | 160 +++++++++++++++++++
6 files changed, 260 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/mach-rmobile/soc_family-info.c
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
2021-01-17 12:50 [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's Biju Das
@ 2021-01-17 12:50 ` Biju Das
2021-01-17 12:50 ` [PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Biju Das @ 2021-01-17 12:50 UTC (permalink / raw
To: u-boot
RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.
RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v8-->v9
* Fixed make file to use default family type function for SPL builds
for both R-Car Gen{2,3} family's.
v7->v8
* Optimized the cpu detection image size, when Renesas SoC identification
driver is disabled for R-Car Gen2 SPL builds
with v8:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
330 0 0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
120 0 0 120 78 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
with v7:
--------
$ size spl/arch/arm/mach-rmobile/cpu_info.o
text data bss dec hex filename
462 0 0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-rmobile/cpu_info.o
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-rmobile/cpu_info-rcar.o
$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text data bss dec hex filename
154 0 0 154 9a spl/arch/arm/mach-rmobile/cpu_info-rcar.o
v6->v7
* Seperated driver patch series from board support patches.
v5->v6
* Optimized the unique CPU identification method by using Renesas SoC identification driver.
v4->v5
* Add support for unique identification of RZ/G2 CPU types
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das.jz at bp.renesas.com/)
v3->v4
* Dropped CPU info reporting logic for RZ/G2. Will address this later.
* Added PRRID's for RZG2[HMNE]
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das.jz at bp.renesas.com/)
v2->v3
* Reworked as per Marek's suggestion
* Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible string
* Removed SoC family type Enum
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das.jz at bp.renesas.com/)
v1->v2:
* Add comment's related to loop logic
(ref: https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das.jz at bp.renesas.com/)
v1:
* New patch
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das.jz at bp.renesas.com/
---
arch/arm/mach-rmobile/Makefile | 5 ++
arch/arm/mach-rmobile/cpu_info-rcar.c | 20 ++++++-
arch/arm/mach-rmobile/cpu_info.c | 12 +++-
arch/arm/mach-rmobile/include/mach/rmobile.h | 63 +++++++++++++++-----
arch/arm/mach-rmobile/soc_family-info.c | 21 +++++++
5 files changed, 100 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/mach-rmobile/soc_family-info.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3206bce722..25636699f4 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_RCAR_GEN2) += soc_family-info.o
+obj-$(CONFIG_RCAR_GEN3) += soc_family-info.o
+endif
+
OBJCOPYFLAGS_u-boot-spl.srec := -O srec
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..4483363f6b 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ * arch/arm/mach-rmobile/cpu_info-rcar.c
*
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2021 Renesas Electronics Corporation
*/
#include <common.h>
#include <asm/io.h>
@@ -12,6 +12,15 @@
#define R8A7796_REV_1_1 0x5210
#define R8A7796_REV_1_3 0x5211
+#if defined(CONFIG_SPL_BUILD)
+static bool __is_rzg_family(void)
+{
+ return false;
+}
+bool is_rzg_family(void)
+ __attribute__((weak, alias("__is_rzg_family")));
+#endif
+
static u32 rmobile_get_prr(void)
{
#ifdef CONFIG_RCAR_GEN3
@@ -23,7 +32,12 @@ static u32 rmobile_get_prr(void)
u32 rmobile_get_cpu_type(void)
{
- return (rmobile_get_prr() & 0x00007F00) >> 8;
+ u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+ if (is_rzg_family())
+ soc_id |= RZG_CPU_MASK;
+
+ return soc_id;
}
u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..2555fa4903 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
-#include <cpu_func.h>
#include <asm/cache.h>
-#include <init.h>
#include <asm/io.h>
+#include <common.h>
+#include <cpu_func.h>
#include <env.h>
+#include <init.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
@@ -64,6 +64,11 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
+#ifdef CONFIG_RCAR_GEN3
+ { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+ { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+ { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+ { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
@@ -71,6 +76,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
+#endif
{ 0x0, "CPU" },
};
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..58e51e8df2 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -1,6 +1,8 @@
#ifndef __ASM_ARCH_RMOBILE_H
#define __ASM_ARCH_RMOBILE_H
+#include <stdbool.h>
+
#if defined(CONFIG_ARCH_RMOBILE)
#if defined(CONFIG_SH73A0)
#include <asm/arch/sh73a0.h>
@@ -24,23 +26,54 @@
#endif
#endif /* CONFIG_ARCH_RMOBILE */
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A0 0x37
-#define RMOBILE_CPU_TYPE_R8A7740 0x40
-#define RMOBILE_CPU_TYPE_R8A7790 0x45
-#define RMOBILE_CPU_TYPE_R8A7791 0x47
-#define RMOBILE_CPU_TYPE_R8A7792 0x4A
-#define RMOBILE_CPU_TYPE_R8A7793 0x4B
-#define RMOBILE_CPU_TYPE_R8A7794 0x4C
-#define RMOBILE_CPU_TYPE_R8A7795 0x4F
-#define RMOBILE_CPU_TYPE_R8A7796 0x52
-#define RMOBILE_CPU_TYPE_R8A77965 0x55
-#define RMOBILE_CPU_TYPE_R8A77970 0x54
-#define RMOBILE_CPU_TYPE_R8A77980 0x56
-#define RMOBILE_CPU_TYPE_R8A77990 0x57
-#define RMOBILE_CPU_TYPE_R8A77995 0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0 0x37
+#define SOC_ID_R8A7740 0x40
+#define SOC_ID_R8A774A1 0x52
+#define SOC_ID_R8A774B1 0x55
+#define SOC_ID_R8A774C0 0x57
+#define SOC_ID_R8A774E1 0x4F
+#define SOC_ID_R8A7790 0x45
+#define SOC_ID_R8A7791 0x47
+#define SOC_ID_R8A7792 0x4A
+#define SOC_ID_R8A7793 0x4B
+#define SOC_ID_R8A7794 0x4C
+#define SOC_ID_R8A7795 0x4F
+#define SOC_ID_R8A7796 0x52
+#define SOC_ID_R8A77965 0x55
+#define SOC_ID_R8A77970 0x54
+#define SOC_ID_R8A77980 0x56
+#define SOC_ID_R8A77990 0x57
+#define SOC_ID_R8A77995 0x58
+
+/* CPU IDs */
+#define RMOBILE_CPU_TYPE_SH73A0 SOC_ID_SH73A0
+#define RMOBILE_CPU_TYPE_R8A7740 SOC_ID_R8A7740
+#define RMOBILE_CPU_TYPE_R8A774A1 (SOC_ID_R8A774A1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774B1 (SOC_ID_R8A774B1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774C0 (SOC_ID_R8A774C0 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774E1 (SOC_ID_R8A774E1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A7790 SOC_ID_R8A7790
+#define RMOBILE_CPU_TYPE_R8A7791 SOC_ID_R8A7791
+#define RMOBILE_CPU_TYPE_R8A7792 SOC_ID_R8A7792
+#define RMOBILE_CPU_TYPE_R8A7793 SOC_ID_R8A7793
+#define RMOBILE_CPU_TYPE_R8A7794 SOC_ID_R8A7794
+#define RMOBILE_CPU_TYPE_R8A7795 SOC_ID_R8A7795
+#define RMOBILE_CPU_TYPE_R8A7796 SOC_ID_R8A7796
+#define RMOBILE_CPU_TYPE_R8A77965 SOC_ID_R8A77965
+#define RMOBILE_CPU_TYPE_R8A77970 SOC_ID_R8A77970
+#define RMOBILE_CPU_TYPE_R8A77980 SOC_ID_R8A77980
+#define RMOBILE_CPU_TYPE_R8A77990 SOC_ID_R8A77990
+#define RMOBILE_CPU_TYPE_R8A77995 SOC_ID_R8A77995
+
+/*
+ * R-Car and RZ/G SoC's share same PRR ID's for the same SoC type. The
+ * RZG_CPU_MASK is used to provide a unique CPU identification for RZ/G SoC's.
+ */
+#define RZG_CPU_MASK 0x1000
#ifndef __ASSEMBLY__
+bool is_rzg_family(void);
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
diff --git a/arch/arm/mach-rmobile/soc_family-info.c b/arch/arm/mach-rmobile/soc_family-info.c
new file mode 100644
index 0000000000..f09bd1a79f
--- /dev/null
+++ b/arch/arm/mach-rmobile/soc_family-info.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ *
+ */
+#include <common.h>
+#include <soc.h>
+
+bool is_rzg_family(void)
+{
+ bool rzg_family_type = false;
+ struct udevice *soc;
+ char name[16];
+
+ if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
+ if (!strcmp(name, "RZ/G2"))
+ rzg_family_type = true;
+ }
+
+ return rzg_family_type;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2021-01-17 12:50 [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's Biju Das
2021-01-17 12:50 ` [PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
@ 2021-01-17 12:50 ` Biju Das
2021-01-17 12:50 ` [PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
2021-01-17 12:50 ` [PATCH v9 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
3 siblings, 0 replies; 5+ messages in thread
From: Biju Das @ 2021-01-17 12:50 UTC (permalink / raw
To: u-boot
Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>
---
v9:
* No Change.
v8:
* Added Jaehoon Chung's Rb tag
v7:
* Incorporated Jaehoon Chung's review comments.
* Fixed the build error on Renesas ARM32 platforms.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 117 +++++++++++++++++++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 24130e620b..d17134d27b 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/sizes.h>
#include <power/regulator.h>
+#include <soc.h>
#include <asm/unaligned.h>
#include "tmio-common.h"
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
return clk_get_rate(&priv->clk);
}
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+ bool hs400_disabled;
+ bool hs400_4taps;
+ u32 hs400_bad_taps;
+ const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+ .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+ .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[] = {
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = &sdhi_quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = &sdhi_quirks_r8a7796_es13
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = &sdhi_quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = &sdhi_quirks_r8a7796_es13
+ },
+ { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+ struct tmio_sd_priv *priv,
+ const struct renesas_sdhi_quirks *quirks)
+{
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+ priv->nrtaps = 8;
+
+ if (!quirks)
+ return;
+
+ if (quirks->hs400_disabled) {
+ plat->cfg.host_caps &= ~MMC_MODE_HS400;
+ if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+ }
+
+ if (quirks->hs400_4taps)
+ priv->nrtaps = 4;
+
+ if (quirks->hs400_bad_taps)
+ priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+ if (quirks->hs400_calib_table) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_calib_table =
+ quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ if (quirks == &sdhi_quirks_r8a7796_es12)
+ priv->adjust_hs400_offset = 3;
+ else if (quirks == &sdhi_quirks_r8a7796_es13)
+ priv->adjust_hs400_offset = 0;
+ }
+}
+#endif
+
static void renesas_sdhi_filter_caps(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_plat(dev);
+ const struct soc_attr *attr;
+
+ attr = soc_device_match(sdhi_quirks_match);
+ if (attr) {
+ renesas_sdhi_add_quirks(plat, priv, attr->data);
+ return;
+ }
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
2021-01-17 12:50 [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's Biju Das
2021-01-17 12:50 ` [PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
2021-01-17 12:50 ` [PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
@ 2021-01-17 12:50 ` Biju Das
2021-01-17 12:50 ` [PATCH v9 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
3 siblings, 0 replies; 5+ messages in thread
From: Biju Das @ 2021-01-17 12:50 UTC (permalink / raw
To: u-boot
Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>
---
v9:
* No Change
v7->v8:
* Added Jaehoon chung's Rb tag
v6->v7:
* No Change. rebased on u-boot-sh/next
v6:
* New patch
---
drivers/mmc/renesas-sdhi.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d17134d27b..055fdbbc99 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a77965_calib_table,
+};
+
/*
* Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
* So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = &sdhi_quirks_r8a7796_es13
},
+ { .soc_id = "r8a774b1",
+ .data = &sdhi_quirks_r8a77965
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = &sdhi_quirks_r8a7796_es13
},
+ { .soc_id = "r8a77965",
+ .data = &sdhi_quirks_r8a77965
+ },
{ /* Sentinel. */ },
};
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
- if (quirks == &sdhi_quirks_r8a7796_es12)
+ if (quirks == &sdhi_quirks_r8a7796_es12 ||
+ quirks == &sdhi_quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == &sdhi_quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
2021-01-17 12:50 [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's Biju Das
` (2 preceding siblings ...)
2021-01-17 12:50 ` [PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
@ 2021-01-17 12:50 ` Biju Das
3 siblings, 0 replies; 5+ messages in thread
From: Biju Das @ 2021-01-17 12:50 UTC (permalink / raw
To: u-boot
Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>
---
v9:
* No Change.
v8:
* Added Jaehoon chung's Rb tag.
v7:
* No Change.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 055fdbbc99..6b3cb02a3e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7795_calib_table,
+};
+
static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[] = {
{ .soc_id = "r8a774b1",
.data = &sdhi_quirks_r8a77965
},
+ { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = &sdhi_quirks_r8a7795_es30
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = &sdhi_quirks_4tap
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = &sdhi_quirks_r8a7795_es30
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
if (quirks == &sdhi_quirks_r8a7796_es12 ||
quirks == &sdhi_quirks_r8a77965)
priv->adjust_hs400_offset = 3;
- else if (quirks == &sdhi_quirks_r8a7796_es13)
+ else if (quirks == &sdhi_quirks_r8a7796_es13 ||
+ quirks == &sdhi_quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-01-17 12:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-01-17 12:50 [PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's Biju Das
2021-01-17 12:50 ` [PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
2021-01-17 12:50 ` [PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
2021-01-17 12:50 ` [PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
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