* v3.16-rc1 & default cachepolicy
@ 2014-06-19 20:36 ` Aaro Koskinen
0 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-19 20:36 UTC (permalink / raw
To: linux-arm-kernel
Hi,
When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
E.g. initramfs unpack takes several minutes. This was caused by default
cachepolicy getting changed from writethrough -> uncached for some reason:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro at cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
[ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: Amstrad E3 (Delta)
[ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache uncached
[...]
[ 4.602732] Unpacking initramfs...
[ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
It seems this is caused by commit:
commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue May 27 20:34:28 2014 +0100
ARM: ensure C page table setup code follows assembly code
I can workaround this with "cachepolicy=writethrough" parameter.
A.
^ permalink raw reply [flat|nested] 12+ messages in thread
* v3.16-rc1 & default cachepolicy
@ 2014-06-19 20:36 ` Aaro Koskinen
0 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-19 20:36 UTC (permalink / raw
To: Russell King; +Cc: linux-arm-kernel, linux-omap
Hi,
When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
E.g. initramfs unpack takes several minutes. This was caused by default
cachepolicy getting changed from writethrough -> uncached for some reason:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro@cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
[ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: Amstrad E3 (Delta)
[ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache uncached
[...]
[ 4.602732] Unpacking initramfs...
[ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
It seems this is caused by commit:
commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue May 27 20:34:28 2014 +0100
ARM: ensure C page table setup code follows assembly code
I can workaround this with "cachepolicy=writethrough" parameter.
A.
^ permalink raw reply [flat|nested] 12+ messages in thread
* v3.16-rc1 & default cachepolicy
2014-06-19 20:36 ` Aaro Koskinen
@ 2014-06-19 20:58 ` Russell King - ARM Linux
-1 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux @ 2014-06-19 20:58 UTC (permalink / raw
To: linux-arm-kernel
On Thu, Jun 19, 2014 at 11:36:55PM +0300, Aaro Koskinen wrote:
> Hi,
>
> When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
> E.g. initramfs unpack takes several minutes. This was caused by default
> cachepolicy getting changed from writethrough -> uncached for some reason:
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Initializing cgroup subsys cpu
> [ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro at cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
> [ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> [ 0.000000] Machine: Amstrad E3 (Delta)
> [ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] Memory policy: Data cache uncached
> [...]
> [ 4.602732] Unpacking initramfs...
> [ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
>
> It seems this is caused by commit:
>
> commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
> Author: Russell King <rmk+kernel@arm.linux.org.uk>
> Date: Tue May 27 20:34:28 2014 +0100
>
> ARM: ensure C page table setup code follows assembly code
>
> I can workaround this with "cachepolicy=writethrough" parameter.
It brings up the question - proc-arm925.S contains:
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
In other words, it's telling the assembly code to setup uncached mappings
for everything, even memory. Most people want to set memory up (even at
the assembly code time) in cacheable mode... so I'd suggest adding:
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
from the first. You'll find it in the .macro at the end of proc-arm925.S.
Please let me know if that works for you.
Thanks.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: v3.16-rc1 & default cachepolicy
@ 2014-06-19 20:58 ` Russell King - ARM Linux
0 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux @ 2014-06-19 20:58 UTC (permalink / raw
To: Aaro Koskinen; +Cc: linux-omap, linux-arm-kernel
On Thu, Jun 19, 2014 at 11:36:55PM +0300, Aaro Koskinen wrote:
> Hi,
>
> When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
> E.g. initramfs unpack takes several minutes. This was caused by default
> cachepolicy getting changed from writethrough -> uncached for some reason:
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Initializing cgroup subsys cpu
> [ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro@cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
> [ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
> [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> [ 0.000000] Machine: Amstrad E3 (Delta)
> [ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] Memory policy: Data cache uncached
> [...]
> [ 4.602732] Unpacking initramfs...
> [ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
>
> It seems this is caused by commit:
>
> commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
> Author: Russell King <rmk+kernel@arm.linux.org.uk>
> Date: Tue May 27 20:34:28 2014 +0100
>
> ARM: ensure C page table setup code follows assembly code
>
> I can workaround this with "cachepolicy=writethrough" parameter.
It brings up the question - proc-arm925.S contains:
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
In other words, it's telling the assembly code to setup uncached mappings
for everything, even memory. Most people want to set memory up (even at
the assembly code time) in cacheable mode... so I'd suggest adding:
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
from the first. You'll find it in the .macro at the end of proc-arm925.S.
Please let me know if that works for you.
Thanks.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 12+ messages in thread
* v3.16-rc1 & default cachepolicy
2014-06-19 20:58 ` Russell King - ARM Linux
@ 2014-06-19 22:40 ` Aaro Koskinen
-1 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-19 22:40 UTC (permalink / raw
To: linux-arm-kernel
Hi,
On Thu, Jun 19, 2014 at 09:58:53PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 19, 2014 at 11:36:55PM +0300, Aaro Koskinen wrote:
> > When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
> > E.g. initramfs unpack takes several minutes. This was caused by default
> > cachepolicy getting changed from writethrough -> uncached for some reason:
> >
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Initializing cgroup subsys cpu
> > [ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro at cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
> > [ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
> > [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> > [ 0.000000] Machine: Amstrad E3 (Delta)
> > [ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
> > [ 0.000000] bootconsole [earlycon0] enabled
> > [ 0.000000] Memory policy: Data cache uncached
> > [...]
> > [ 4.602732] Unpacking initramfs...
> > [ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
> >
> > It seems this is caused by commit:
> >
> > commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
> > Author: Russell King <rmk+kernel@arm.linux.org.uk>
> > Date: Tue May 27 20:34:28 2014 +0100
> >
> > ARM: ensure C page table setup code follows assembly code
> >
> > I can workaround this with "cachepolicy=writethrough" parameter.
>
> It brings up the question - proc-arm925.S contains:
>
> .long PMD_TYPE_SECT | \
> PMD_BIT4 | \
> PMD_SECT_AP_WRITE | \
> PMD_SECT_AP_READ
> .long PMD_TYPE_SECT | \
> PMD_BIT4 | \
> PMD_SECT_AP_WRITE | \
> PMD_SECT_AP_READ
>
> In other words, it's telling the assembly code to setup uncached mappings
> for everything, even memory. Most people want to set memory up (even at
> the assembly code time) in cacheable mode... so I'd suggest adding:
>
> PMD_SECT_BUFFERABLE | \
> PMD_SECT_CACHEABLE | \
>
> from the first. You'll find it in the .macro at the end of proc-arm925.S.
> Please let me know if that works for you.
So I tried the below change. But now it hangs early, even before
the earlyprintk is working. :-/
A.
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 97448c3..cb7c0e7 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -502,6 +502,8 @@ __\name\()_proc_info:
.long \cpu_val
.long \cpu_mask
.long PMD_TYPE_SECT | \
+ PMD_SECT_BUFFERABLE | \
+ PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: v3.16-rc1 & default cachepolicy
@ 2014-06-19 22:40 ` Aaro Koskinen
0 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-19 22:40 UTC (permalink / raw
To: Russell King - ARM Linux; +Cc: linux-omap, linux-arm-kernel
Hi,
On Thu, Jun 19, 2014 at 09:58:53PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 19, 2014 at 11:36:55PM +0300, Aaro Koskinen wrote:
> > When booting v3.16-rc1 on OMAP1, I noticed strange slowness.
> > E.g. initramfs unpack takes several minutes. This was caused by default
> > cachepolicy getting changed from writethrough -> uncached for some reason:
> >
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Initializing cgroup subsys cpu
> > [ 0.000000] Linux version 3.16.0-rc1-e3-los_880e+ (aaro@cooljazz) (gcc version 4.9.0 (GCC) ) #1 PREEMPT Thu Jun 19 22:51:42 EEST 2014
> > [ 0.000000] CPU: ARM925T [54029252] revision 2 (ARMv4T), cr=0000317f
> > [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> > [ 0.000000] Machine: Amstrad E3 (Delta)
> > [ 0.000000] Ignoring memory below PHYS_OFFSET: 0x02000000-0x10000000
> > [ 0.000000] bootconsole [earlycon0] enabled
> > [ 0.000000] Memory policy: Data cache uncached
> > [...]
> > [ 4.602732] Unpacking initramfs...
> > [ 425.125093] Freeing initrd memory: 3532K (c1c00000 - c1f73000)
> >
> > It seems this is caused by commit:
> >
> > commit ca8f0b0a545f55b3dc6877cda24d609a8979c951
> > Author: Russell King <rmk+kernel@arm.linux.org.uk>
> > Date: Tue May 27 20:34:28 2014 +0100
> >
> > ARM: ensure C page table setup code follows assembly code
> >
> > I can workaround this with "cachepolicy=writethrough" parameter.
>
> It brings up the question - proc-arm925.S contains:
>
> .long PMD_TYPE_SECT | \
> PMD_BIT4 | \
> PMD_SECT_AP_WRITE | \
> PMD_SECT_AP_READ
> .long PMD_TYPE_SECT | \
> PMD_BIT4 | \
> PMD_SECT_AP_WRITE | \
> PMD_SECT_AP_READ
>
> In other words, it's telling the assembly code to setup uncached mappings
> for everything, even memory. Most people want to set memory up (even at
> the assembly code time) in cacheable mode... so I'd suggest adding:
>
> PMD_SECT_BUFFERABLE | \
> PMD_SECT_CACHEABLE | \
>
> from the first. You'll find it in the .macro at the end of proc-arm925.S.
> Please let me know if that works for you.
So I tried the below change. But now it hangs early, even before
the earlyprintk is working. :-/
A.
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 97448c3..cb7c0e7 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -502,6 +502,8 @@ __\name\()_proc_info:
.long \cpu_val
.long \cpu_mask
.long PMD_TYPE_SECT | \
+ PMD_SECT_BUFFERABLE | \
+ PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
^ permalink raw reply related [flat|nested] 12+ messages in thread
* v3.16-rc1 & default cachepolicy
2014-06-19 22:40 ` Aaro Koskinen
@ 2014-06-19 23:36 ` Russell King - ARM Linux
-1 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux @ 2014-06-19 23:36 UTC (permalink / raw
To: linux-arm-kernel
On Fri, Jun 20, 2014 at 01:40:04AM +0300, Aaro Koskinen wrote:
> So I tried the below change. But now it hangs early, even before
> the earlyprintk is working. :-/
Thanks for trying. I notice you said "write-through", so can you
drop the PMD_SECT_BUFFERABLE flag and try again please?
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: v3.16-rc1 & default cachepolicy
@ 2014-06-19 23:36 ` Russell King - ARM Linux
0 siblings, 0 replies; 12+ messages in thread
From: Russell King - ARM Linux @ 2014-06-19 23:36 UTC (permalink / raw
To: Aaro Koskinen; +Cc: linux-omap, linux-arm-kernel
On Fri, Jun 20, 2014 at 01:40:04AM +0300, Aaro Koskinen wrote:
> So I tried the below change. But now it hangs early, even before
> the earlyprintk is working. :-/
Thanks for trying. I notice you said "write-through", so can you
drop the PMD_SECT_BUFFERABLE flag and try again please?
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 12+ messages in thread
* v3.16-rc1 & default cachepolicy
2014-06-19 23:36 ` Russell King - ARM Linux
@ 2014-06-20 8:57 ` Aaro Koskinen
-1 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-20 8:57 UTC (permalink / raw
To: linux-arm-kernel
Hi,
On Fri, Jun 20, 2014 at 12:36:26AM +0100, Russell King - ARM Linux wrote:
> On Fri, Jun 20, 2014 at 01:40:04AM +0300, Aaro Koskinen wrote:
> > So I tried the below change. But now it hangs early, even before
> > the earlyprintk is working. :-/
>
> Thanks for trying. I notice you said "write-through", so can you
> drop the PMD_SECT_BUFFERABLE flag and try again please?
Yes, that works.
A.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: v3.16-rc1 & default cachepolicy
@ 2014-06-20 8:57 ` Aaro Koskinen
0 siblings, 0 replies; 12+ messages in thread
From: Aaro Koskinen @ 2014-06-20 8:57 UTC (permalink / raw
To: Russell King - ARM Linux; +Cc: linux-omap, linux-arm-kernel
Hi,
On Fri, Jun 20, 2014 at 12:36:26AM +0100, Russell King - ARM Linux wrote:
> On Fri, Jun 20, 2014 at 01:40:04AM +0300, Aaro Koskinen wrote:
> > So I tried the below change. But now it hangs early, even before
> > the earlyprintk is working. :-/
>
> Thanks for trying. I notice you said "write-through", so can you
> drop the PMD_SECT_BUFFERABLE flag and try again please?
Yes, that works.
A.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] ARM: arm925: ensure assembly sets up writethrough mapping
2014-06-20 8:57 ` Aaro Koskinen
@ 2014-06-20 10:26 ` Russell King
-1 siblings, 0 replies; 12+ messages in thread
From: Russell King @ 2014-06-20 10:26 UTC (permalink / raw
To: linux-arm-kernel
Commit ca8f0b0a545f ("ARM: ensure C page table setup code follows
assembly code") did what it said on the tin, but some of the older
CPU code omitted the default cache policy from their files. This
results in the kernel running with the caches disabled. Fix this
for ARM925.
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/proc-arm925.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 97448c3acf38..ba0d58e1a2a2 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -502,6 +502,7 @@ __\name\()_proc_info:
.long \cpu_val
.long \cpu_mask
.long PMD_TYPE_SECT | \
+ PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
--
1.8.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH] ARM: arm925: ensure assembly sets up writethrough mapping
@ 2014-06-20 10:26 ` Russell King
0 siblings, 0 replies; 12+ messages in thread
From: Russell King @ 2014-06-20 10:26 UTC (permalink / raw
To: Aaro Koskinen; +Cc: linux-omap, linux-arm-kernel
Commit ca8f0b0a545f ("ARM: ensure C page table setup code follows
assembly code") did what it said on the tin, but some of the older
CPU code omitted the default cache policy from their files. This
results in the kernel running with the caches disabled. Fix this
for ARM925.
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/proc-arm925.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 97448c3acf38..ba0d58e1a2a2 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -502,6 +502,7 @@ __\name\()_proc_info:
.long \cpu_val
.long \cpu_mask
.long PMD_TYPE_SECT | \
+ PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
--
1.8.3.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2014-06-20 10:26 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-06-19 20:36 v3.16-rc1 & default cachepolicy Aaro Koskinen
2014-06-19 20:36 ` Aaro Koskinen
2014-06-19 20:58 ` Russell King - ARM Linux
2014-06-19 20:58 ` Russell King - ARM Linux
2014-06-19 22:40 ` Aaro Koskinen
2014-06-19 22:40 ` Aaro Koskinen
2014-06-19 23:36 ` Russell King - ARM Linux
2014-06-19 23:36 ` Russell King - ARM Linux
2014-06-20 8:57 ` Aaro Koskinen
2014-06-20 8:57 ` Aaro Koskinen
2014-06-20 10:26 ` [PATCH] ARM: arm925: ensure assembly sets up writethrough mapping Russell King
2014-06-20 10:26 ` Russell King
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