* [PATCH 0/7] Enable RC6/Turbo on CHV
@ 2014-05-23 15:30 deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
Squashed some of the patches and rebased the patches on latest nightly.
Deepak S (5):
drm/i915/chv: Enable Render Standby (RC6) for Cherryview
drm/i915/chv: Added CHV specific register read and write and
Streamline CHV forcewake stuff
drm/i915/chv: Enable RPS (Turbo) for Cherryview
drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
drm/i915/chv: Freq(opcode) request for CHV.
Ville Syrjälä (2):
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 12 ++
drivers/gpu/drm/i915/intel_pm.c | 219 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 14 +++
drivers/gpu/drm/i915/intel_uncore.c | 146 +++++++++++++++++++----
6 files changed, 372 insertions(+), 32 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
` (5 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
v6: Rebase patch on latest nightly (Deepak)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +++++++++++++++++++++++++++++++++++++---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5122254..c1f36a5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1167,6 +1167,8 @@ enum punit_power_well {
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT 12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
#define EIR 0x020b0
#define EMR 0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 906d06f..1816c52 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3341,6 +3341,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3763,6 +3770,35 @@ static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
dev_priv->vlv_pctx->stolen->start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
+
+ WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long pctx_paddr, paddr;
+ struct i915_gtt *gtt = &dev_priv->gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(&dev->struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
+ paddr = (dev_priv->mm.stolen_base +
+ (gtt->stolen_size - pctx_size));
+
+ pctx_paddr = (paddr & (~4095));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3852,11 +3888,70 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_engine_cs *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
+ gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a & 1b: Get forcewake during program sequence. Although the driver
+ * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
+
+ /* 3: Enable RC6 */
+ if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
+ (pcbr >> VLV_PCBR_ADDR_SHIFT))
+ rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+
+ I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
+
static void valleyview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4665,13 +4760,17 @@ void intel_init_gt_powersave(struct drm_device *dev)
{
i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
- if (IS_VALLEYVIEW(dev))
+ if (IS_CHERRYVIEW(dev))
+ cherryview_init_gt_powersave(dev);
+ else if (IS_VALLEYVIEW(dev))
valleyview_init_gt_powersave(dev);
}
void intel_cleanup_gt_powersave(struct drm_device *dev)
{
- if (IS_VALLEYVIEW(dev))
+ if (IS_CHERRYVIEW(dev))
+ return;
+ else if (IS_VALLEYVIEW(dev))
valleyview_cleanup_gt_powersave(dev);
}
@@ -4685,13 +4784,15 @@ void intel_disable_gt_powersave(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
- } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 6) {
if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
intel_runtime_pm_put(dev_priv);
cancel_work_sync(&dev_priv->rps.work);
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev))
+ if (IS_CHERRYVIEW(dev))
+ cherryview_disable_rps(dev);
+ else if (IS_VALLEYVIEW(dev))
valleyview_disable_rps(dev);
else
gen6_disable_rps(dev);
@@ -4709,7 +4810,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev)) {
+ cherryview_enable_rps(dev);
+ } else if (IS_VALLEYVIEW(dev)) {
valleyview_enable_rps(dev);
} else if (IS_BROADWELL(dev)) {
gen8_enable_rps(dev);
@@ -4734,7 +4837,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
ironlake_enable_rc6(dev);
intel_init_emon(dev);
mutex_unlock(&dev->struct_mutex);
- } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 6) {
/*
* PCU communication is slow and this doesn't need to be
* done at any specific time, so do this out of our fast path
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-26 8:07 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
` (4 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
Re-factor CHV/VLV Forcewake offsets (Ben)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
v4: Squash the patches (Mika)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 135 +++++++++++++++++++++++++++++++-----
1 file changed, 118 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2f5d5d3..7409de0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((reg) < 0x40000 && (reg) != FORCEWAKE)
-#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
- (((reg) >= 0x2000 && (reg) < 0x4000) ||\
- ((reg) >= 0x5000 && (reg) < 0x8000) ||\
- ((reg) >= 0xB000 && (reg) < 0x12000) ||\
- ((reg) >= 0x2E000 && (reg) < 0x30000))
+#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
-#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) >= 0x12000 && (reg) < 0x14000) ||\
- ((reg) >= 0x22000 && (reg) < 0x24000) ||\
- ((reg) >= 0x30000 && (reg) < 0x40000))
+#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+ REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0xB000, 0x12000) || \
+ REG_RANGE((reg), 0x2E000, 0x30000))
+
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x12000, 0x14000) || \
+ REG_RANGE((reg), 0x22000, 0x24000) || \
+ REG_RANGE((reg), 0x30000, 0x40000))
+
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+ REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0x8300, 0x8500) || \
+ REG_RANGE((reg), 0xB000, 0xC000) || \
+ REG_RANGE((reg), 0xE000, 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x8800, 0x8900) || \
+ REG_RANGE((reg), 0xD000, 0xD800) || \
+ REG_RANGE((reg), 0x12000, 0x14000) || \
+ REG_RANGE((reg), 0x1A000, 0x1C000) || \
+ REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+ REG_RANGE((reg), 0x30000, 0x40000))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x4000, 0x5000) || \
+ REG_RANGE((reg), 0x8000, 0x8300) || \
+ REG_RANGE((reg), 0x8500, 0x8600) || \
+ REG_RANGE((reg), 0x9000, 0xB000) || \
+ REG_RANGE((reg), 0xC000, 0xC800) || \
+ REG_RANGE((reg), 0xF000, 0x10000) || \
+ REG_RANGE((reg), 0x14000, 0x14400) || \
+ REG_RANGE((reg), 0x22000, 0x24000))
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
+ } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+ REG_READ_FOOTER; \
+}
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -608,6 +663,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef __gen6_read
#undef __gen5_read
@@ -712,6 +768,38 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
REG_WRITE_FOOTER; \
}
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+ unsigned fwengine = 0; \
+ bool shadowed = is_gen8_shadowed(dev_priv, reg); \
+ REG_WRITE_HEADER; \
+ if (!shadowed) { \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
+ } \
+ } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+ __raw_i915_write##x(dev_priv, reg, val); \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+ REG_WRITE_FOOTER; \
+}
+
+__chv_write(8)
+__chv_write(16)
+__chv_write(32)
+__chv_write(64)
__gen8_write(8)
__gen8_write(16)
__gen8_write(32)
@@ -733,6 +821,7 @@ __gen4_write(16)
__gen4_write(32)
__gen4_write(64)
+#undef __chv_write
#undef __gen8_write
#undef __hsw_write
#undef __gen6_write
@@ -796,14 +885,26 @@ void intel_uncore_init(struct drm_device *dev)
switch (INTEL_INFO(dev)->gen) {
default:
- dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
- dev_priv->uncore.funcs.mmio_writew = gen8_write16;
- dev_priv->uncore.funcs.mmio_writel = gen8_write32;
- dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
- dev_priv->uncore.funcs.mmio_readb = gen6_read8;
- dev_priv->uncore.funcs.mmio_readw = gen6_read16;
- dev_priv->uncore.funcs.mmio_readl = gen6_read32;
- dev_priv->uncore.funcs.mmio_readq = gen6_read64;
+ if (IS_CHERRYVIEW(dev)) {
+ dev_priv->uncore.funcs.mmio_writeb = chv_write8;
+ dev_priv->uncore.funcs.mmio_writew = chv_write16;
+ dev_priv->uncore.funcs.mmio_writel = chv_write32;
+ dev_priv->uncore.funcs.mmio_writeq = chv_write64;
+ dev_priv->uncore.funcs.mmio_readb = chv_read8;
+ dev_priv->uncore.funcs.mmio_readw = chv_read16;
+ dev_priv->uncore.funcs.mmio_readl = chv_read32;
+ dev_priv->uncore.funcs.mmio_readq = chv_read64;
+
+ } else {
+ dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
+ dev_priv->uncore.funcs.mmio_writew = gen8_write16;
+ dev_priv->uncore.funcs.mmio_writel = gen8_write32;
+ dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
+ dev_priv->uncore.funcs.mmio_readb = gen6_read8;
+ dev_priv->uncore.funcs.mmio_readw = gen6_read16;
+ dev_priv->uncore.funcs.mmio_readl = gen6_read32;
+ dev_priv->uncore.funcs.mmio_readq = gen6_read64;
+ }
break;
case 7:
case 6:
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-26 13:30 ` Mika Kuoppala
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
` (3 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx; +Cc: Daniel Vetter
From: Deepak S <deepak.s@linux.intel.com>
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 ++++
drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0412b12..5f0e338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..37f4b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,7 @@
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
+#define CHV_IOSF_PORT_NC 0x04
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
@@ -529,6 +530,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
@@ -933,6 +942,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..08dcdc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
+ rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+ rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+
+ dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+ DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+ dev_priv->rps.max_freq);
+
+ dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+ dev_priv->rps.min_freq);
+
+ /* Preserve min/max settings in case of re-init */
+ if (dev_priv->rps.max_freq_softlimit == 0)
+ dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+ if (dev_priv->rps.min_freq_softlimit == 0)
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
}
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* 4 Program defaults and thresholds for RPS*/
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ /* 5: Enable RPS */
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_AVG);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+ DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+ dev_priv->rps.cur_freq);
+
+ DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 01d841e..a74f60b 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
SB_CRWRDA_NP, reg, &val);
}
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+ u32 val = 0;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ mutex_lock(&dev_priv->dpio_lock);
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
+ SB_CRRDDA_NP, addr, &val);
+ mutex_unlock(&dev_priv->dpio_lock);
+
+ return val;
+}
+
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
u32 val = 0;
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
` (2 preceding siblings ...)
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
` (2 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7409de0..5f9200a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -231,8 +231,8 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
}
/* WaRsForcewakeWaitTC0:vlv */
- __gen6_gt_wait_for_thread_c0(dev_priv);
-
+ if (!IS_CHERRYVIEW(dev_priv->dev))
+ __gen6_gt_wait_for_thread_c0(dev_priv);
}
static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
` (3 preceding siblings ...)
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s
6 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5f9200a..d44941b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -250,9 +250,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
- /* The below doubles as a POSTING_READ */
- gen6_gt_check_fifodbg(dev_priv);
-
+ /* something from same cacheline, but !FORCEWAKE_VLV */
+ __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
+ if (!IS_CHERRYVIEW(dev_priv->dev))
+ gen6_gt_check_fifodbg(dev_priv);
}
static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
` (4 preceding siblings ...)
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
@ 2014-05-23 15:30 ` deepak.s
2014-05-26 15:19 ` Mika Kuoppala
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s
6 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08dcdc5..0b73a6d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val >> 6) & 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv->mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv->mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV.
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
` (5 preceding siblings ...)
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
@ 2014-05-23 15:30 ` deepak.s
6 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-05-23 15:30 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 28bae6e..671d751 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1258,8 +1258,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
if (adj > 0)
adj *= 2;
- else
- adj = 1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
+ }
new_delay = dev_priv->rps.cur_freq + adj;
/*
@@ -1277,8 +1279,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj < 0)
adj *= 2;
- else
- adj = -1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
+ }
new_delay = dev_priv->rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv->rps.cur_freq;
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
@ 2014-05-26 8:07 ` Daniel Vetter
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-05-26 8:07 UTC (permalink / raw
To: deepak.s; +Cc: intel-gfx
On Fri, May 23, 2014 at 09:00:16PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> Support to individually control Media/Render well based on the register access.
> Add CHV specific write function to habdle difference between registers
> that are sadowed vs those that need forcewake even for writes.
>
> Streamline the CHV forcewake functions just like was done for VLV.
>
> This will also fix a bug in accessing the common well registers,
> where we'd end up trying to wake up the wells too many times
> since we'd call force_wake_get/put twice per register access, with
> FORCEFAKE_ALL both times.
>
> v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
> Re-factor CHV/VLV Forcewake offsets (Ben)
>
> v3: Fix for decrementing fw count in chv read/write. (Deepak)
>
> v4: Squash the patches (Mika)
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> [vsyrjala: Move the register range macros into intel_uncore.c]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Only merged up to this one stil the next patch is missing r-b still. Mika?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 135 +++++++++++++++++++++++++++++++-----
> 1 file changed, 118 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 2f5d5d3..7409de0 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
> #define NEEDS_FORCE_WAKE(dev_priv, reg) \
> ((reg) < 0x40000 && (reg) != FORCEWAKE)
>
> -#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
> - (((reg) >= 0x2000 && (reg) < 0x4000) ||\
> - ((reg) >= 0x5000 && (reg) < 0x8000) ||\
> - ((reg) >= 0xB000 && (reg) < 0x12000) ||\
> - ((reg) >= 0x2E000 && (reg) < 0x30000))
> +#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
>
> -#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
> - (((reg) >= 0x12000 && (reg) < 0x14000) ||\
> - ((reg) >= 0x22000 && (reg) < 0x24000) ||\
> - ((reg) >= 0x30000 && (reg) < 0x40000))
> +#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
> + (REG_RANGE((reg), 0x2000, 0x4000) || \
> + REG_RANGE((reg), 0x5000, 0x8000) || \
> + REG_RANGE((reg), 0xB000, 0x12000) || \
> + REG_RANGE((reg), 0x2E000, 0x30000))
> +
> +#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
> + (REG_RANGE((reg), 0x12000, 0x14000) || \
> + REG_RANGE((reg), 0x22000, 0x24000) || \
> + REG_RANGE((reg), 0x30000, 0x40000))
> +
> +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> + (REG_RANGE((reg), 0x2000, 0x4000) || \
> + REG_RANGE((reg), 0x5000, 0x8000) || \
> + REG_RANGE((reg), 0x8300, 0x8500) || \
> + REG_RANGE((reg), 0xB000, 0xC000) || \
> + REG_RANGE((reg), 0xE000, 0xE800))
> +
> +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
> + (REG_RANGE((reg), 0x8800, 0x8900) || \
> + REG_RANGE((reg), 0xD000, 0xD800) || \
> + REG_RANGE((reg), 0x12000, 0x14000) || \
> + REG_RANGE((reg), 0x1A000, 0x1C000) || \
> + REG_RANGE((reg), 0x1E800, 0x1EA00) || \
> + REG_RANGE((reg), 0x30000, 0x40000))
> +
> +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
> + (REG_RANGE((reg), 0x4000, 0x5000) || \
> + REG_RANGE((reg), 0x8000, 0x8300) || \
> + REG_RANGE((reg), 0x8500, 0x8600) || \
> + REG_RANGE((reg), 0x9000, 0xB000) || \
> + REG_RANGE((reg), 0xC000, 0xC800) || \
> + REG_RANGE((reg), 0xF000, 0x10000) || \
> + REG_RANGE((reg), 0x14000, 0x14400) || \
> + REG_RANGE((reg), 0x22000, 0x24000))
>
> static void
> ilk_dummy_write(struct drm_i915_private *dev_priv)
> @@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> REG_READ_FOOTER; \
> }
>
> +#define __chv_read(x) \
> +static u##x \
> +chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> + unsigned fwengine = 0; \
> + REG_READ_HEADER(x); \
> + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine = FORCEWAKE_RENDER; \
> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine = FORCEWAKE_MEDIA; \
> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine |= FORCEWAKE_RENDER; \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine |= FORCEWAKE_MEDIA; \
> + } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> + val = __raw_i915_read##x(dev_priv, reg); \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> + REG_READ_FOOTER; \
> +}
>
> +__chv_read(8)
> +__chv_read(16)
> +__chv_read(32)
> +__chv_read(64)
> __vlv_read(8)
> __vlv_read(16)
> __vlv_read(32)
> @@ -608,6 +663,7 @@ __gen4_read(16)
> __gen4_read(32)
> __gen4_read(64)
>
> +#undef __chv_read
> #undef __vlv_read
> #undef __gen6_read
> #undef __gen5_read
> @@ -712,6 +768,38 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> REG_WRITE_FOOTER; \
> }
>
> +#define __chv_write(x) \
> +static void \
> +chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> + unsigned fwengine = 0; \
> + bool shadowed = is_gen8_shadowed(dev_priv, reg); \
> + REG_WRITE_HEADER; \
> + if (!shadowed) { \
> + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine = FORCEWAKE_RENDER; \
> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine = FORCEWAKE_MEDIA; \
> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine |= FORCEWAKE_RENDER; \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine |= FORCEWAKE_MEDIA; \
> + } \
> + } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> + __raw_i915_write##x(dev_priv, reg, val); \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> + REG_WRITE_FOOTER; \
> +}
> +
> +__chv_write(8)
> +__chv_write(16)
> +__chv_write(32)
> +__chv_write(64)
> __gen8_write(8)
> __gen8_write(16)
> __gen8_write(32)
> @@ -733,6 +821,7 @@ __gen4_write(16)
> __gen4_write(32)
> __gen4_write(64)
>
> +#undef __chv_write
> #undef __gen8_write
> #undef __hsw_write
> #undef __gen6_write
> @@ -796,14 +885,26 @@ void intel_uncore_init(struct drm_device *dev)
>
> switch (INTEL_INFO(dev)->gen) {
> default:
> - dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
> - dev_priv->uncore.funcs.mmio_writew = gen8_write16;
> - dev_priv->uncore.funcs.mmio_writel = gen8_write32;
> - dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
> - dev_priv->uncore.funcs.mmio_readb = gen6_read8;
> - dev_priv->uncore.funcs.mmio_readw = gen6_read16;
> - dev_priv->uncore.funcs.mmio_readl = gen6_read32;
> - dev_priv->uncore.funcs.mmio_readq = gen6_read64;
> + if (IS_CHERRYVIEW(dev)) {
> + dev_priv->uncore.funcs.mmio_writeb = chv_write8;
> + dev_priv->uncore.funcs.mmio_writew = chv_write16;
> + dev_priv->uncore.funcs.mmio_writel = chv_write32;
> + dev_priv->uncore.funcs.mmio_writeq = chv_write64;
> + dev_priv->uncore.funcs.mmio_readb = chv_read8;
> + dev_priv->uncore.funcs.mmio_readw = chv_read16;
> + dev_priv->uncore.funcs.mmio_readl = chv_read32;
> + dev_priv->uncore.funcs.mmio_readq = chv_read64;
> +
> + } else {
> + dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
> + dev_priv->uncore.funcs.mmio_writew = gen8_write16;
> + dev_priv->uncore.funcs.mmio_writel = gen8_write32;
> + dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
> + dev_priv->uncore.funcs.mmio_readb = gen6_read8;
> + dev_priv->uncore.funcs.mmio_readw = gen6_read16;
> + dev_priv->uncore.funcs.mmio_readl = gen6_read32;
> + dev_priv->uncore.funcs.mmio_readq = gen6_read64;
> + }
> break;
> case 7:
> case 6:
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
@ 2014-05-26 13:30 ` Mika Kuoppala
2014-05-26 13:54 ` Deepak S
0 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-05-26 13:30 UTC (permalink / raw
To: deepak.s, intel-gfx; +Cc: Daniel Vetter
Hi Deepak,
deepak.s@linux.intel.com writes:
> From: Deepak S <deepak.s@linux.intel.com>
>
> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>
> v3: Mass rename of the dev_priv->rps variables in upstream.
>
> v4: Rebase against latest code. (Deepak)
>
> v5: Rebase against latest nightly code. (Deepak)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
> 4 files changed, 119 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0412b12..5f0e338 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1f36a5..37f4b12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -487,6 +487,7 @@
> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
>
> +#define CHV_IOSF_PORT_NC 0x04
Use IOSF_PORT_PUNIT instead of defining this?
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> @@ -529,6 +530,14 @@ enum punit_power_well {
> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>
> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
> +
> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
> +#define CHV_FB_RPE_FREQ_SHIFT 8
> +#define CHV_FB_RPE_FREQ_MASK 0xff
> +
These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf
etc...
> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> @@ -933,6 +942,7 @@ enum punit_power_well {
> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>
> +
> /* control register for cpu gtt access */
> #define TILECTL 0x101000
> #define TILECTL_SWZCTL (1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1816c52..08dcdc5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rp0;
> +
> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
> +
I didn't find any reason we couldn't use vlv_punit_read().
> + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
> + CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
> +
> + return rp0;
> +}
> +
> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rpe;
> +
> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
> + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
> +
> + return rpe;
> +}
> +
> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rpn;
> +
> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
> + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
> +
Please don't reuse mask/shift from other register even tho
they happen to be identical. This confuses the reader alot.
Define new ones with proper naming.
> + return rpn;
> +}
> +
> int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> {
> u32 val, rp0;
> @@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>
> static void cherryview_init_gt_powersave(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> cherryview_setup_pctx(dev);
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> +
> + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> + dev_priv->rps.max_freq);
> +
> + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> + dev_priv->rps.efficient_freq);
> +
> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> + dev_priv->rps.min_freq);
> +
> + /* Preserve min/max settings in case of re-init */
> + if (dev_priv->rps.max_freq_softlimit == 0)
> + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
> +
> + if (dev_priv->rps.min_freq_softlimit == 0)
> + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
> +
> + mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
> @@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> - u32 gtfifodbg, rc6_mode = 0, pcbr;
> + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
> int i;
>
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> @@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
>
> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>
> + /* 4 Program defaults and thresholds for RPS*/
> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> + I915_WRITE(GEN6_RP_UP_EI, 66000);
> + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> +
> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> + /* 5: Enable RPS */
> + I915_WRITE(GEN6_RP_CONTROL,
> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
> + GEN6_RP_MEDIA_IS_GFX |
> + GEN6_RP_ENABLE |
> + GEN6_RP_UP_BUSY_AVG |
> + GEN6_RP_DOWN_IDLE_AVG);
> +
> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +
> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> +
> + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> + dev_priv->rps.cur_freq);
> +
> + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> + dev_priv->rps.efficient_freq);
> +
> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> +
> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 01d841e..a74f60b 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> SB_CRWRDA_NP, reg, &val);
> }
>
> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> +{
> + u32 val = 0;
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> + mutex_lock(&dev_priv->dpio_lock);
> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
> + SB_CRRDDA_NP, addr, &val);
> + mutex_unlock(&dev_priv->dpio_lock);
> +
> + return val;
> +}
> +
Use vlv_punit_read() and you can get rid of this function.
-Mika
> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> {
> u32 val = 0;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 13:30 ` Mika Kuoppala
@ 2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
` (3 more replies)
0 siblings, 4 replies; 24+ messages in thread
From: Deepak S @ 2014-05-26 13:54 UTC (permalink / raw
To: Mika Kuoppala, intel-gfx; +Cc: Daniel Vetter
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
> Hi Deepak,
>
> deepak.s@linux.intel.com writes:
>
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>>
>> v3: Mass rename of the dev_priv->rps variables in upstream.
>>
>> v4: Rebase against latest code. (Deepak)
>>
>> v5: Rebase against latest nightly code. (Deepak)
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
>> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 0412b12..5f0e338 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
>> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c1f36a5..37f4b12 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -487,6 +487,7 @@
>> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
>> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
>>
>> +#define CHV_IOSF_PORT_NC 0x04
> Use IOSF_PORT_PUNIT instead of defining this?
Yes, Agreed, I will address this
>> /* See configdb bunit SB addr map */
>> #define BUNIT_REG_BISOC 0x11
>>
>> @@ -529,6 +530,14 @@ enum punit_power_well {
>> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
>> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>>
>> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
>> +
>> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
>> +#define CHV_FB_RPE_FREQ_SHIFT 8
>> +#define CHV_FB_RPE_FREQ_MASK 0xff
>> +
> These seem to be also part of punit space so I would prefer:
> PUNIT_REG_GPU_STATUS 0xdb
> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> PUNIT_REG_GPU_DUTYCYCLE 0xdf
>
> etc...
I can change. Q? don't we want to identify the register with CHV?
>> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
>> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
>> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
>> @@ -933,6 +942,7 @@ enum punit_power_well {
>> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
>> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>>
>> +
>> /* control register for cpu gtt access */
>> #define TILECTL 0x101000
>> #define TILECTL_SWZCTL (1 << 0)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 1816c52..08dcdc5 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
>> mutex_unlock(&dev_priv->rps.hw_lock);
>> }
>>
>> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>> +{
>> + u32 val, rp0;
>> +
>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>> +
> I didn't find any reason we couldn't use vlv_punit_read().
I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV
I would prefer to keep distinguish between fuse and punit read.
>> + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
>> + CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
>> +
>> + return rp0;
>> +}
>> +
>> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>> +{
>> + u32 val, rpe;
>> +
>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
>> + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>> +
>> + return rpe;
>> +}
>> +
>> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>> +{
>> + u32 val, rpn;
>> +
>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>> + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>> +
> Please don't reuse mask/shift from other register even tho
> they happen to be identical. This confuses the reader alot.
> Define new ones with proper naming.
>
>> + return rpn;
>> +}
>> +
>> int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>> {
>> u32 val, rp0;
>> @@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>>
>> static void cherryview_init_gt_powersave(struct drm_device *dev)
>> {
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> cherryview_setup_pctx(dev);
>> +
>> + mutex_lock(&dev_priv->rps.hw_lock);
>> +
>> + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>> + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>> + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>> + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>> + dev_priv->rps.max_freq);
>> +
>> + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
>> + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> + dev_priv->rps.efficient_freq);
>> +
>> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>> + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>> + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>> + dev_priv->rps.min_freq);
>> +
>> + /* Preserve min/max settings in case of re-init */
>> + if (dev_priv->rps.max_freq_softlimit == 0)
>> + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
>> +
>> + if (dev_priv->rps.min_freq_softlimit == 0)
>> + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
>> +
>> + mutex_unlock(&dev_priv->rps.hw_lock);
>> }
>>
>> static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
>> @@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>> {
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_engine_cs *ring;
>> - u32 gtfifodbg, rc6_mode = 0, pcbr;
>> + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
>> int i;
>>
>> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>> @@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>
>> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>>
>> + /* 4 Program defaults and thresholds for RPS*/
>> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>> + I915_WRITE(GEN6_RP_UP_EI, 66000);
>> + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
>> +
>> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>> +
>> + /* 5: Enable RPS */
>> + I915_WRITE(GEN6_RP_CONTROL,
>> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
>> + GEN6_RP_MEDIA_IS_GFX |
>> + GEN6_RP_ENABLE |
>> + GEN6_RP_UP_BUSY_AVG |
>> + GEN6_RP_DOWN_IDLE_AVG);
>> +
>> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>> +
>> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>> + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>> +
>> + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>> + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
>> + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>> + dev_priv->rps.cur_freq);
>> +
>> + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>> + dev_priv->rps.efficient_freq);
>> +
>> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>> +
>> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index 01d841e..a74f60b 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>> SB_CRWRDA_NP, reg, &val);
>> }
>>
>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>> +{
>> + u32 val = 0;
>> +
>> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>> +
>> + mutex_lock(&dev_priv->dpio_lock);
>> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
>> + SB_CRRDDA_NP, addr, &val);
>> + mutex_unlock(&dev_priv->dpio_lock);
>> +
>> + return val;
>> +}
>> +
> Use vlv_punit_read() and you can get rid of this function.
Same as above. I would prefer to keep distinguish between fuse and punit read. If needed i can change
Let me know you thoughts?
> -Mika
>
>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>> {
>> u32 val = 0;
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 13:54 ` Deepak S
@ 2014-05-26 14:32 ` Ville Syrjälä
2014-05-27 3:29 ` Deepak S
2014-05-26 14:37 ` Mika Kuoppala
` (2 subsequent siblings)
3 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2014-05-26 14:32 UTC (permalink / raw
To: Deepak S; +Cc: intel-gfx, Daniel Vetter
On Mon, May 26, 2014 at 07:24:21PM +0530, Deepak S wrote:
>
> On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
> > Hi Deepak,
> >
> > deepak.s@linux.intel.com writes:
> >
> >> From: Deepak S <deepak.s@linux.intel.com>
> >>
> >> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
> >>
> >> v3: Mass rename of the dev_priv->rps variables in upstream.
> >>
> >> v4: Rebase against latest code. (Deepak)
> >>
> >> v5: Rebase against latest nightly code. (Deepak)
> >>
> >> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
> >> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
> >> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
> >> 4 files changed, 119 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 0412b12..5f0e338 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
> >> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
> >> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
> >> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> >> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> >> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> >> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> >> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index c1f36a5..37f4b12 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -487,6 +487,7 @@
> >> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
> >> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
> >>
> >> +#define CHV_IOSF_PORT_NC 0x04
> > Use IOSF_PORT_PUNIT instead of defining this?
>
> Yes, Agreed, I will address this
>
> >> /* See configdb bunit SB addr map */
> >> #define BUNIT_REG_BISOC 0x11
> >>
> >> @@ -529,6 +530,14 @@ enum punit_power_well {
> >> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> >> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
> >>
> >> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
> >> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
> >> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
> >> +
> >> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
> >> +#define CHV_FB_RPE_FREQ_SHIFT 8
> >> +#define CHV_FB_RPE_FREQ_MASK 0xff
> >> +
> > These seem to be also part of punit space so I would prefer:
> > PUNIT_REG_GPU_STATUS 0xdb
> > PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> > PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> > PUNIT_REG_GPU_DUTYCYCLE 0xdf
> >
> > etc...
>
> I can change. Q? don't we want to identify the register with CHV?
>
> >> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> >> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> >> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> >> @@ -933,6 +942,7 @@ enum punit_power_well {
> >> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
> >> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
> >>
> >> +
> >> /* control register for cpu gtt access */
> >> #define TILECTL 0x101000
> >> #define TILECTL_SWZCTL (1 << 0)
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index 1816c52..08dcdc5 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
> >> mutex_unlock(&dev_priv->rps.hw_lock);
> >> }
> >>
> >> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> >> +{
> >> + u32 val, rp0;
> >> +
> >> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
> >> +
> > I didn't find any reason we couldn't use vlv_punit_read().
>
> I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV
> I would prefer to keep distinguish between fuse and punit read.
If the register is in the punit you should use the punit funcs. If
there's something special about those registers just add a comment
which explains it.
The whole nc unit seems to have disappeared in CHV, so it's rather
confusing when you see NC being mentioned and then you go digging
through the docs and can't find anything like it.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
@ 2014-05-26 14:37 ` Mika Kuoppala
2014-05-27 3:29 ` Deepak S
2014-05-27 6:36 ` [PATCH v6] " deepak.s
2014-05-27 10:29 ` [PATCH v7] " deepak.s
3 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-05-26 14:37 UTC (permalink / raw
To: Deepak S, intel-gfx; +Cc: Daniel Vetter
Deepak S <deepak.s@linux.intel.com> writes:
> On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
>> Hi Deepak,
>>
>> deepak.s@linux.intel.com writes:
>>
>>> From: Deepak S <deepak.s@linux.intel.com>
>>>
>>> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>>>
>>> v3: Mass rename of the dev_priv->rps variables in upstream.
>>>
>>> v4: Rebase against latest code. (Deepak)
>>>
>>> v5: Rebase against latest nightly code. (Deepak)
>>>
>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
>>> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
>>> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
>>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 0412b12..5f0e338 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>>> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
>>> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>>> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>>> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index c1f36a5..37f4b12 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -487,6 +487,7 @@
>>> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
>>> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
>>>
>>> +#define CHV_IOSF_PORT_NC 0x04
>> Use IOSF_PORT_PUNIT instead of defining this?
>
> Yes, Agreed, I will address this
>
>>> /* See configdb bunit SB addr map */
>>> #define BUNIT_REG_BISOC 0x11
>>>
>>> @@ -529,6 +530,14 @@ enum punit_power_well {
>>> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
>>> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>>>
>>> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
>>> +
>>> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
>>> +#define CHV_FB_RPE_FREQ_SHIFT 8
>>> +#define CHV_FB_RPE_FREQ_MASK 0xff
>>> +
>> These seem to be also part of punit space so I would prefer:
>> PUNIT_REG_GPU_STATUS 0xdb
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
>> PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
>> PUNIT_REG_GPU_DUTYCYCLE 0xdf
>>
>> etc...
>
> I can change. Q? don't we want to identify the register with CHV?
If you like, add /* chv */ after those punit regs you add.
I would not globber the namespace more. As in this case only chv
code will use these inside cherryview_* named functions.
>>> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
>>> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
>>> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
>>> @@ -933,6 +942,7 @@ enum punit_power_well {
>>> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
>>> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>>>
>>> +
>>> /* control register for cpu gtt access */
>>> #define TILECTL 0x101000
>>> #define TILECTL_SWZCTL (1 << 0)
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 1816c52..08dcdc5 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
>>> mutex_unlock(&dev_priv->rps.hw_lock);
>>> }
>>>
>>> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>>> +{
>>> + u32 val, rp0;
>>> +
>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>>> +
>> I didn't find any reason we couldn't use vlv_punit_read().
>
> I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV
> I would prefer to keep distinguish between fuse and punit read.
>>> + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
>>> + CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
>>> +
>>> + return rp0;
>>> +}
>>> +
>>> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>>> +{
>>> + u32 val, rpe;
>>> +
>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
>>> + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>>> +
>>> + return rpe;
>>> +}
>>> +
>>> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>>> +{
>>> + u32 val, rpn;
>>> +
>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>>> + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>>> +
>> Please don't reuse mask/shift from other register even tho
>> they happen to be identical. This confuses the reader alot.
>> Define new ones with proper naming.
>>
>>> + return rpn;
>>> +}
>>> +
>>> int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>>> {
>>> u32 val, rp0;
>>> @@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>>>
>>> static void cherryview_init_gt_powersave(struct drm_device *dev)
>>> {
>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>> cherryview_setup_pctx(dev);
>>> +
>>> + mutex_lock(&dev_priv->rps.hw_lock);
>>> +
>>> + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>>> + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>>> + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>>> + dev_priv->rps.max_freq);
>>> +
>>> + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
>>> + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>> + dev_priv->rps.efficient_freq);
>>> +
>>> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>>> + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>>> + dev_priv->rps.min_freq);
>>> +
>>> + /* Preserve min/max settings in case of re-init */
>>> + if (dev_priv->rps.max_freq_softlimit == 0)
>>> + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
>>> +
>>> + if (dev_priv->rps.min_freq_softlimit == 0)
>>> + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
>>> +
>>> + mutex_unlock(&dev_priv->rps.hw_lock);
>>> }
>>>
>>> static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
>>> @@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>> {
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct intel_engine_cs *ring;
>>> - u32 gtfifodbg, rc6_mode = 0, pcbr;
>>> + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
>>> int i;
>>>
>>> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>> @@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>
>>> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>>>
>>> + /* 4 Program defaults and thresholds for RPS*/
>>> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>>> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>>> + I915_WRITE(GEN6_RP_UP_EI, 66000);
>>> + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
>>> +
>>> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>>> +
>>> + /* 5: Enable RPS */
>>> + I915_WRITE(GEN6_RP_CONTROL,
>>> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
>>> + GEN6_RP_MEDIA_IS_GFX |
>>> + GEN6_RP_ENABLE |
>>> + GEN6_RP_UP_BUSY_AVG |
>>> + GEN6_RP_DOWN_IDLE_AVG);
>>> +
>>> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>> +
>>> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>>> + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>>> +
>>> + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>>> + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>>> + dev_priv->rps.cur_freq);
>>> +
>>> + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>> + dev_priv->rps.efficient_freq);
>>> +
>>> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>>> +
>>> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>>> index 01d841e..a74f60b 100644
>>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>>> @@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>>> SB_CRWRDA_NP, reg, &val);
>>> }
>>>
>>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>>> +{
>>> + u32 val = 0;
>>> +
>>> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>> +
>>> + mutex_lock(&dev_priv->dpio_lock);
>>> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
>>> + SB_CRRDDA_NP, addr, &val);
>>> + mutex_unlock(&dev_priv->dpio_lock);
>>> +
>>> + return val;
>>> +}
>>> +
>> Use vlv_punit_read() and you can get rid of this function.
>
> Same as above. I would prefer to keep distinguish between fuse and punit read. If needed i can change
> Let me know you thoughts?
The registers are in the punit space. The sideband target address is
punit target address. For what I know, this is a punit access.
Please explain why this fuse distingtion is needed/comes from.
If it has been fuse read in past then we have opportunity to forget the
ugly past in here and match the code with the documentation. If this is
the case, please change it to punit read and remove references to 'nc'
Thanks,
-Mika
>> -Mika
>>
>>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>>> {
>>> u32 val = 0;
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
@ 2014-05-26 15:19 ` Mika Kuoppala
2014-05-27 11:42 ` Daniel Vetter
0 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-05-26 15:19 UTC (permalink / raw
To: deepak.s, intel-gfx
deepak.s@linux.intel.com writes:
> From: Deepak S <deepak.s@linux.intel.com>
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> [vsyrjala: Fix merge fubmle where the code ended up in
> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 08dcdc5..0b73a6d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> GEN6_RP_UP_BUSY_AVG |
> GEN6_RP_DOWN_IDLE_AVG);
>
> + /* ToDo: Update the mem freq based on latest spec [CHV]*/
Please do and consider fixing the vlv decoding. It seems to be off
too.
-Mika
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + switch ((val >> 6) & 3) {
> + case 0:
> + case 1:
> + case 2:
> + dev_priv->mem_freq = 1600;
> + break;
> + case 3:
> + dev_priv->mem_freq = 2000;
> + break;
> + }
>
> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 14:37 ` Mika Kuoppala
@ 2014-05-27 3:29 ` Deepak S
0 siblings, 0 replies; 24+ messages in thread
From: Deepak S @ 2014-05-27 3:29 UTC (permalink / raw
To: Mika Kuoppala, intel-gfx; +Cc: Daniel Vetter
Thanks for the Review. I will address the comments
On Monday 26 May 2014 08:07 PM, Mika Kuoppala wrote:
> Deepak S <deepak.s@linux.intel.com> writes:
>
>> On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
>>> Hi Deepak,
>>>
>>> deepak.s@linux.intel.com writes:
>>>
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>>>>
>>>> v3: Mass rename of the dev_priv->rps variables in upstream.
>>>>
>>>> v4: Rebase against latest code. (Deepak)
>>>>
>>>> v5: Rebase against latest nightly code. (Deepak)
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
>>>> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
>>>> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
>>>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index 0412b12..5f0e338 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>>>> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>>>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>>>> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>>>> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index c1f36a5..37f4b12 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -487,6 +487,7 @@
>>>> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
>>>> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
>>>>
>>>> +#define CHV_IOSF_PORT_NC 0x04
>>> Use IOSF_PORT_PUNIT instead of defining this?
>> Yes, Agreed, I will address this
>>
>>>> /* See configdb bunit SB addr map */
>>>> #define BUNIT_REG_BISOC 0x11
>>>>
>>>> @@ -529,6 +530,14 @@ enum punit_power_well {
>>>> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
>>>> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>>>>
>>>> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
>>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
>>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
>>>> +
>>>> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
>>>> +#define CHV_FB_RPE_FREQ_SHIFT 8
>>>> +#define CHV_FB_RPE_FREQ_MASK 0xff
>>>> +
>>> These seem to be also part of punit space so I would prefer:
>>> PUNIT_REG_GPU_STATUS 0xdb
>>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
>>> PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
>>> PUNIT_REG_GPU_DUTYCYCLE 0xdf
>>>
>>> etc...
>> I can change. Q? don't we want to identify the register with CHV?
> If you like, add /* chv */ after those punit regs you add.
>
> I would not globber the namespace more. As in this case only chv
> code will use these inside cherryview_* named functions.
>
>>>> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
>>>> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
>>>> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
>>>> @@ -933,6 +942,7 @@ enum punit_power_well {
>>>> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
>>>> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>>>>
>>>> +
>>>> /* control register for cpu gtt access */
>>>> #define TILECTL 0x101000
>>>> #define TILECTL_SWZCTL (1 << 0)
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index 1816c52..08dcdc5 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
>>>> mutex_unlock(&dev_priv->rps.hw_lock);
>>>> }
>>>>
>>>> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + u32 val, rp0;
>>>> +
>>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>>>> +
>>> I didn't find any reason we couldn't use vlv_punit_read().
>> I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV
>> I would prefer to keep distinguish between fuse and punit read.
>>>> + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
>>>> + CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
>>>> +
>>>> + return rp0;
>>>> +}
>>>> +
>>>> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + u32 val, rpe;
>>>> +
>>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
>>>> + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>>>> +
>>>> + return rpe;
>>>> +}
>>>> +
>>>> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + u32 val, rpn;
>>>> +
>>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>>>> + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
>>>> +
>>> Please don't reuse mask/shift from other register even tho
>>> they happen to be identical. This confuses the reader alot.
>>> Define new ones with proper naming.
>>>
>>>> + return rpn;
>>>> +}
>>>> +
>>>> int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>>>> {
>>>> u32 val, rp0;
>>>> @@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>>>>
>>>> static void cherryview_init_gt_powersave(struct drm_device *dev)
>>>> {
>>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>>> +
>>>> cherryview_setup_pctx(dev);
>>>> +
>>>> + mutex_lock(&dev_priv->rps.hw_lock);
>>>> +
>>>> + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>>>> + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>>>> + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>>>> + dev_priv->rps.max_freq);
>>>> +
>>>> + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
>>>> + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
>>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>>> + dev_priv->rps.efficient_freq);
>>>> +
>>>> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>>>> + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>>>> + dev_priv->rps.min_freq);
>>>> +
>>>> + /* Preserve min/max settings in case of re-init */
>>>> + if (dev_priv->rps.max_freq_softlimit == 0)
>>>> + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
>>>> +
>>>> + if (dev_priv->rps.min_freq_softlimit == 0)
>>>> + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
>>>> +
>>>> + mutex_unlock(&dev_priv->rps.hw_lock);
>>>> }
>>>>
>>>> static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
>>>> @@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>> {
>>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>>> struct intel_engine_cs *ring;
>>>> - u32 gtfifodbg, rc6_mode = 0, pcbr;
>>>> + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
>>>> int i;
>>>>
>>>> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>>> @@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>>
>>>> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>>>>
>>>> + /* 4 Program defaults and thresholds for RPS*/
>>>> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>>>> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>>>> + I915_WRITE(GEN6_RP_UP_EI, 66000);
>>>> + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
>>>> +
>>>> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>>>> +
>>>> + /* 5: Enable RPS */
>>>> + I915_WRITE(GEN6_RP_CONTROL,
>>>> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
>>>> + GEN6_RP_MEDIA_IS_GFX |
>>>> + GEN6_RP_ENABLE |
>>>> + GEN6_RP_UP_BUSY_AVG |
>>>> + GEN6_RP_DOWN_IDLE_AVG);
>>>> +
>>>> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>>> +
>>>> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>>>> + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>>>> +
>>>> + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
>>>> + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
>>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
>>>> + dev_priv->rps.cur_freq);
>>>> +
>>>> + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
>>>> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>>>> + dev_priv->rps.efficient_freq);
>>>> +
>>>> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
>>>> +
>>>> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>>>> }
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>>>> index 01d841e..a74f60b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>>>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>>>> @@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>>>> SB_CRWRDA_NP, reg, &val);
>>>> }
>>>>
>>>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>>>> +{
>>>> + u32 val = 0;
>>>> +
>>>> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>>> +
>>>> + mutex_lock(&dev_priv->dpio_lock);
>>>> + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
>>>> + SB_CRRDDA_NP, addr, &val);
>>>> + mutex_unlock(&dev_priv->dpio_lock);
>>>> +
>>>> + return val;
>>>> +}
>>>> +
>>> Use vlv_punit_read() and you can get rid of this function.
>> Same as above. I would prefer to keep distinguish between fuse and punit read. If needed i can change
>> Let me know you thoughts?
> The registers are in the punit space. The sideband target address is
> punit target address. For what I know, this is a punit access.
> Please explain why this fuse distingtion is needed/comes from.
>
> If it has been fuse read in past then we have opportunity to forget the
> ugly past in here and match the code with the documentation. If this is
> the case, please change it to punit read and remove references to 'nc'
>
> Thanks,
> -Mika
>
>>> -Mika
>>>
>>>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>>>> {
>>>> u32 val = 0;
>>>> --
>>>> 1.9.1
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 14:32 ` Ville Syrjälä
@ 2014-05-27 3:29 ` Deepak S
0 siblings, 0 replies; 24+ messages in thread
From: Deepak S @ 2014-05-27 3:29 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx, Daniel Vetter
On Monday 26 May 2014 08:02 PM, Ville Syrjälä wrote:
> On Mon, May 26, 2014 at 07:24:21PM +0530, Deepak S wrote:
>> On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
>>> Hi Deepak,
>>>
>>> deepak.s@linux.intel.com writes:
>>>
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>>>>
>>>> v3: Mass rename of the dev_priv->rps variables in upstream.
>>>>
>>>> v4: Rebase against latest code. (Deepak)
>>>>
>>>> v5: Rebase against latest nightly code. (Deepak)
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>>> drivers/gpu/drm/i915/i915_reg.h | 10 ++++
>>>> drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++-
>>>> drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
>>>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index 0412b12..5f0e338 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>>>> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>>>> u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
>>>> u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
>>>> void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>>>> u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index c1f36a5..37f4b12 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -487,6 +487,7 @@
>>>> #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
>>>> #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
>>>>
>>>> +#define CHV_IOSF_PORT_NC 0x04
>>> Use IOSF_PORT_PUNIT instead of defining this?
>> Yes, Agreed, I will address this
>>
>>>> /* See configdb bunit SB addr map */
>>>> #define BUNIT_REG_BISOC 0x11
>>>>
>>>> @@ -529,6 +530,14 @@ enum punit_power_well {
>>>> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
>>>> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>>>>
>>>> +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
>>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
>>>> +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
>>>> +
>>>> +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf
>>>> +#define CHV_FB_RPE_FREQ_SHIFT 8
>>>> +#define CHV_FB_RPE_FREQ_MASK 0xff
>>>> +
>>> These seem to be also part of punit space so I would prefer:
>>> PUNIT_REG_GPU_STATUS 0xdb
>>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
>>> PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
>>> PUNIT_REG_GPU_DUTYCYCLE 0xdf
>>>
>>> etc...
>> I can change. Q? don't we want to identify the register with CHV?
>>
>>>> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
>>>> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
>>>> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
>>>> @@ -933,6 +942,7 @@ enum punit_power_well {
>>>> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
>>>> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>>>>
>>>> +
>>>> /* control register for cpu gtt access */
>>>> #define TILECTL 0x101000
>>>> #define TILECTL_SWZCTL (1 << 0)
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index 1816c52..08dcdc5 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
>>>> mutex_unlock(&dev_priv->rps.hw_lock);
>>>> }
>>>>
>>>> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + u32 val, rp0;
>>>> +
>>>> + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
>>>> +
>>> I didn't find any reason we couldn't use vlv_punit_read().
>> I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV
>> I would prefer to keep distinguish between fuse and punit read.
> If the register is in the punit you should use the punit funcs. If
> there's something special about those registers just add a comment
> which explains it.
>
> The whole nc unit seems to have disappeared in CHV, so it's rather
> confusing when you see NC being mentioned and then you go digging
> through the docs and can't find anything like it.
>
Reading the latest Docs, I will address the comments.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
2014-05-26 14:37 ` Mika Kuoppala
@ 2014-05-27 6:36 ` deepak.s
2014-05-27 10:29 ` [PATCH v7] " deepak.s
3 siblings, 0 replies; 24+ messages in thread
From: deepak.s @ 2014-05-27 6:36 UTC (permalink / raw
To: intel-gfx; +Cc: Daniel Vetter
From: Deepak S <deepak.s@linux.intel.com>
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec (Mika)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++
drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..7e8968b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,16 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define CHV_IOSF_PUNIT_FB_GFX_FREQ_REG 0xdb
+#define CHV_FB_GFX_MAX_FREQ_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_MASK 0xff
+#define CHV_FB_GFX_MIN_FREQ_SHIFT 8
+#define CHV_FB_GFX_MIN_FREQ_MASK 0xff
+
+#define CHV_IOSF_PUNIT_FB_GFX_RPE_REG 0xdf
+#define CHV_FB_GFX_RPE_FREQ_SHIFT 8
+#define CHV_FB_GFX_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
@@ -933,6 +943,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..d4a84b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_FREQ_REG);
+
+ rp0 = (val >> CHV_FB_GFX_MAX_FREQ_SHIFT) &
+ CHV_FB_GFX_MAX_FREQ_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_RPE_REG);
+ rpe = (val >> CHV_FB_GFX_RPE_FREQ_SHIFT) & CHV_FB_GFX_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_FREQ_REG);
+ rpn = (val >> CHV_FB_GFX_MIN_FREQ_SHIFT) & CHV_FB_GFX_MIN_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+
+ dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+ DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+ dev_priv->rps.max_freq);
+
+ dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+ dev_priv->rps.min_freq);
+
+ /* Preserve min/max settings in case of re-init */
+ if (dev_priv->rps.max_freq_softlimit == 0)
+ dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+ if (dev_priv->rps.min_freq_softlimit == 0)
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
}
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* 4 Program defaults and thresholds for RPS*/
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ /* 5: Enable RPS */
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_AVG);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+ DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+ dev_priv->rps.cur_freq);
+
+ DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-26 13:54 ` Deepak S
` (2 preceding siblings ...)
2014-05-27 6:36 ` [PATCH v6] " deepak.s
@ 2014-05-27 10:29 ` deepak.s
2014-05-27 10:45 ` Mika Kuoppala
3 siblings, 1 reply; 24+ messages in thread
From: deepak.s @ 2014-05-27 10:29 UTC (permalink / raw
To: intel-gfx; +Cc: Daniel Vetter
From: Deepak S <deepak.s@linux.intel.com>
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec (Mika)
v7: change min/max freq variable naming to match spec (Mika)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++
drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..8a935cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,16 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define PUNIT_GPU_STATUS_REG 0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
@@ -933,6 +943,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..0f36405 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(&dev_priv->rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
+ rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+
+ dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+ DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+ dev_priv->rps.max_freq);
+
+ dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+ dev_priv->rps.min_freq);
+
+ /* Preserve min/max settings in case of re-init */
+ if (dev_priv->rps.max_freq_softlimit == 0)
+ dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+ if (dev_priv->rps.min_freq_softlimit == 0)
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
}
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
@@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* 4 Program defaults and thresholds for RPS*/
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ /* 5: Enable RPS */
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_AVG);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+ DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+ DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+ dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+ DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+ dev_priv->rps.cur_freq);
+
+ DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+ vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+ dev_priv->rps.efficient_freq);
+
+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-27 10:29 ` [PATCH v7] " deepak.s
@ 2014-05-27 10:45 ` Mika Kuoppala
2014-05-27 11:44 ` Daniel Vetter
0 siblings, 1 reply; 24+ messages in thread
From: Mika Kuoppala @ 2014-05-27 10:45 UTC (permalink / raw
To: deepak.s, intel-gfx; +Cc: Daniel Vetter
deepak.s@linux.intel.com writes:
> From: Deepak S <deepak.s@linux.intel.com>
>
> v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
>
> v3: Mass rename of the dev_priv->rps variables in upstream.
>
> v4: Rebase against latest code. (Deepak)
>
> v5: Rebase against latest nightly code. (Deepak)
>
> v6: Rename the variables to match the spec (Mika)
>
> v7: change min/max freq variable naming to match spec (Mika)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> drivers/gpu/drm/i915/i915_reg.h | 11 +++++
> drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1f36a5..8a935cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -529,6 +529,16 @@ enum punit_power_well {
> #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
>
> +#define PUNIT_GPU_STATUS_REG 0xdb
> +#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> +#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> +#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
> +#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
> +
> +#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
> +
> #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> @@ -933,6 +943,7 @@ enum punit_power_well {
> #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
> #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
>
> +
> /* control register for cpu gtt access */
> #define TILECTL 0x101000
> #define TILECTL_SWZCTL (1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1816c52..0f36405 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rp0;
> +
> + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> + rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> +
> + return rp0;
> +}
> +
> +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rpe;
> +
> + val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
> + rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
> +
> + return rpe;
> +}
> +
> +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rpn;
> +
> + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> + rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
> + return rpn;
> +}
> +
> int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> {
> u32 val, rp0;
> @@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>
> static void cherryview_init_gt_powersave(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> cherryview_setup_pctx(dev);
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> +
> + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> + dev_priv->rps.max_freq);
> +
> + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> + dev_priv->rps.efficient_freq);
> +
> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> + dev_priv->rps.min_freq);
> +
> + /* Preserve min/max settings in case of re-init */
> + if (dev_priv->rps.max_freq_softlimit == 0)
> + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
> +
> + if (dev_priv->rps.min_freq_softlimit == 0)
> + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
> +
> + mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
> @@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> - u32 gtfifodbg, rc6_mode = 0, pcbr;
> + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
> int i;
>
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> @@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
>
> I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>
> + /* 4 Program defaults and thresholds for RPS*/
> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> + I915_WRITE(GEN6_RP_UP_EI, 66000);
> + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> +
> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> + /* 5: Enable RPS */
> + I915_WRITE(GEN6_RP_CONTROL,
> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
> + GEN6_RP_MEDIA_IS_GFX |
> + GEN6_RP_ENABLE |
> + GEN6_RP_UP_BUSY_AVG |
> + GEN6_RP_DOWN_IDLE_AVG);
> +
> + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +
> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> +
> + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> + dev_priv->rps.cur_freq);
> +
> + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> + dev_priv->rps.efficient_freq);
> +
> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> +
> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> }
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-26 15:19 ` Mika Kuoppala
@ 2014-05-27 11:42 ` Daniel Vetter
2014-05-27 11:59 ` Ville Syrjälä
2014-05-27 12:13 ` Deepak S
0 siblings, 2 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-05-27 11:42 UTC (permalink / raw
To: Mika Kuoppala; +Cc: intel-gfx
On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
> deepak.s@linux.intel.com writes:
>
> > From: Deepak S <deepak.s@linux.intel.com>
> >
> > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > [vsyrjala: Fix merge fubmle where the code ended up in
> > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 08dcdc5..0b73a6d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > GEN6_RP_UP_BUSY_AVG |
> > GEN6_RP_DOWN_IDLE_AVG);
> >
> > + /* ToDo: Update the mem freq based on latest spec [CHV]*/
>
> Please do and consider fixing the vlv decoding. It seems to be off
> too.
Poke about this one here. Iirc the situation on vlv is simply terminal
confusion, and iirc the current code matches reality of shipping vbiosen,
but not any spec. I hope we're bettter for chv.
-Daniel
>
> -Mika
>
> > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > + switch ((val >> 6) & 3) {
> > + case 0:
> > + case 1:
> > + case 2:
> > + dev_priv->mem_freq = 1600;
> > + break;
> > + case 3:
> > + dev_priv->mem_freq = 2000;
> > + break;
> > + }
> >
> > DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> > DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
2014-05-27 10:45 ` Mika Kuoppala
@ 2014-05-27 11:44 ` Daniel Vetter
0 siblings, 0 replies; 24+ messages in thread
From: Daniel Vetter @ 2014-05-27 11:44 UTC (permalink / raw
To: Mika Kuoppala; +Cc: Daniel Vetter, intel-gfx
On Tue, May 27, 2014 at 01:45:59PM +0300, Mika Kuoppala wrote:
> deepak.s@linux.intel.com writes:
>
> > From: Deepak S <deepak.s@linux.intel.com>
> >
> > v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
> >
> > v3: Mass rename of the dev_priv->rps variables in upstream.
> >
> > v4: Rebase against latest code. (Deepak)
> >
> > v5: Rebase against latest nightly code. (Deepak)
> >
> > v6: Rename the variables to match the spec (Mika)
> >
> > v7: change min/max freq variable naming to match spec (Mika)
> >
> > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Ok, I've merged all remaining patches except for patch 6. This one here
angered checkpatch a bit, please check your patches before submission if
you don't have a text editor which just gets all the little alignment
recommendations right.
Thanks, Daniel
>
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++++
> > drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
> > 2 files changed, 102 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c1f36a5..8a935cf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -529,6 +529,16 @@ enum punit_power_well {
> > #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> > #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
> >
> > +#define PUNIT_GPU_STATUS_REG 0xdb
> > +#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
> > +#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
> > +#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
> > +#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
> > +
> > +#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
> > +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
> > +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
> > +
> > #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
> > #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
> > #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
> > @@ -933,6 +943,7 @@ enum punit_power_well {
> > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
> > #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
> >
> > +
> > /* control register for cpu gtt access */
> > #define TILECTL 0x101000
> > #define TILECTL_SWZCTL (1 << 0)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 1816c52..0f36405 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > }
> >
> > +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rp0;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > + rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> > +
> > + return rp0;
> > +}
> > +
> > +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rpe;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
> > + rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
> > +
> > + return rpe;
> > +}
> > +
> > +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val, rpn;
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> > + rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
> > + return rpn;
> > +}
> > +
> > int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> > {
> > u32 val, rp0;
> > @@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
> >
> > static void cherryview_init_gt_powersave(struct drm_device *dev)
> > {
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > cherryview_setup_pctx(dev);
> > +
> > + mutex_lock(&dev_priv->rps.hw_lock);
> > +
> > + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> > + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> > + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> > + dev_priv->rps.max_freq);
> > +
> > + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> > + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > + dev_priv->rps.efficient_freq);
> > +
> > + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> > + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > + dev_priv->rps.min_freq);
> > +
> > + /* Preserve min/max settings in case of re-init */
> > + if (dev_priv->rps.max_freq_softlimit == 0)
> > + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
> > +
> > + if (dev_priv->rps.min_freq_softlimit == 0)
> > + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
> > +
> > + mutex_unlock(&dev_priv->rps.hw_lock);
> > }
> >
> > static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
> > @@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_engine_cs *ring;
> > - u32 gtfifodbg, rc6_mode = 0, pcbr;
> > + u32 gtfifodbg, val, rc6_mode = 0, pcbr;
> > int i;
> >
> > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > @@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >
> > I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> >
> > + /* 4 Program defaults and thresholds for RPS*/
> > + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> > + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> > + I915_WRITE(GEN6_RP_UP_EI, 66000);
> > + I915_WRITE(GEN6_RP_DOWN_EI, 350000);
> > +
> > + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> > +
> > + /* 5: Enable RPS */
> > + I915_WRITE(GEN6_RP_CONTROL,
> > + GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > + GEN6_RP_MEDIA_IS_GFX |
> > + GEN6_RP_ENABLE |
> > + GEN6_RP_UP_BUSY_AVG |
> > + GEN6_RP_DOWN_IDLE_AVG);
> > +
> > + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > +
> > + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> > + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> > +
> > + dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> > + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> > + dev_priv->rps.cur_freq);
> > +
> > + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > + dev_priv->rps.efficient_freq);
> > +
> > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> > +
> > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> > }
> >
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-27 11:42 ` Daniel Vetter
@ 2014-05-27 11:59 ` Ville Syrjälä
2014-05-27 12:11 ` Deepak S
2014-05-27 12:13 ` Deepak S
1 sibling, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2014-05-27 11:59 UTC (permalink / raw
To: Daniel Vetter; +Cc: intel-gfx
On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
> > deepak.s@linux.intel.com writes:
> >
> > > From: Deepak S <deepak.s@linux.intel.com>
> > >
> > > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > > [vsyrjala: Fix merge fubmle where the code ended up in
> > > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> > > 1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 08dcdc5..0b73a6d 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > > GEN6_RP_UP_BUSY_AVG |
> > > GEN6_RP_DOWN_IDLE_AVG);
> > >
> > > + /* ToDo: Update the mem freq based on latest spec [CHV]*/
> >
> > Please do and consider fixing the vlv decoding. It seems to be off
> > too.
>
> Poke about this one here. Iirc the situation on vlv is simply terminal
> confusion, and iirc the current code matches reality of shipping vbiosen,
> but not any spec.
Yeah changed back here:
commit f6d519481b662d9fc52836e6e6107520f03e0122
Author: Deepak S <deepak.s@linux.intel.com>
Date: Thu Apr 3 21:01:28 2014 +0530
Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
As per the inputs provided by hardware team we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.
I think what we need is a comment there which states why
we're going against the spec, just to avoid future confusion
and someone accidentally changing it back again.
> I hope we're bettter for chv.
One can dream.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-27 11:59 ` Ville Syrjälä
@ 2014-05-27 12:11 ` Deepak S
0 siblings, 0 replies; 24+ messages in thread
From: Deepak S @ 2014-05-27 12:11 UTC (permalink / raw
To: Ville Syrjälä, Daniel Vetter; +Cc: intel-gfx
On Tuesday 27 May 2014 05:29 PM, Ville Syrjälä wrote:
> On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
>> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
>>> deepak.s@linux.intel.com writes:
>>>
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> [vsyrjala: Fix merge fubmle where the code ended up in
>>>> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> Acked-by: Ben Widawsky <ben@bwidawsk.net>
>>>> ---
>>>> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>> 1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index 08dcdc5..0b73a6d 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>> GEN6_RP_UP_BUSY_AVG |
>>>> GEN6_RP_DOWN_IDLE_AVG);
>>>>
>>>> + /* ToDo: Update the mem freq based on latest spec [CHV]*/
>>> Please do and consider fixing the vlv decoding. It seems to be off
>>> too.
>> Poke about this one here. Iirc the situation on vlv is simply terminal
>> confusion, and iirc the current code matches reality of shipping vbiosen,
>> but not any spec.
> Yeah changed back here:
>
> commit f6d519481b662d9fc52836e6e6107520f03e0122
> Author: Deepak S <deepak.s@linux.intel.com>
> Date: Thu Apr 3 21:01:28 2014 +0530
>
> Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
>
> As per the inputs provided by hardware team we still use DDR
> Rates as 0,1=800, 2=1066, 3=1333.
> With this change, Turbo freqs used on current machines matches.
>
>
> I think what we need is a comment there which states why
> we're going against the spec, just to avoid future confusion
> and someone accidentally changing it back again.
>
>> I hope we're bettter for chv.
> One can dream.
Problem is the spec is not update to latest. Based on the communication from the HW team i update the proper value.
For CHV, I have updated based on the values i got from HW team.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
2014-05-27 11:42 ` Daniel Vetter
2014-05-27 11:59 ` Ville Syrjälä
@ 2014-05-27 12:13 ` Deepak S
1 sibling, 0 replies; 24+ messages in thread
From: Deepak S @ 2014-05-27 12:13 UTC (permalink / raw
To: Daniel Vetter, Mika Kuoppala; +Cc: intel-gfx
On Tuesday 27 May 2014 05:12 PM, Daniel Vetter wrote:
> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
>> deepak.s@linux.intel.com writes:
>>
>>> From: Deepak S <deepak.s@linux.intel.com>
>>>
>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>> [vsyrjala: Fix merge fubmle where the code ended up in
>>> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Acked-by: Ben Widawsky <ben@bwidawsk.net>
>>> ---
>>> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 08dcdc5..0b73a6d 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>> GEN6_RP_UP_BUSY_AVG |
>>> GEN6_RP_DOWN_IDLE_AVG);
>>>
>>> + /* ToDo: Update the mem freq based on latest spec [CHV]*/
>> Please do and consider fixing the vlv decoding. It seems to be off
>> too.
> Poke about this one here. Iirc the situation on vlv is simply terminal
> confusion, and iirc the current code matches reality of shipping vbiosen,
> but not any spec. I hope we're bettter for chv.
> -Daniel
I am trying to get proper values updated in the spec so that we dont have confusion. Once it is available I will update the code accordingly.
>> -Mika
>>
>>> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>> + switch ((val >> 6) & 3) {
>>> + case 0:
>>> + case 1:
>>> + case 2:
>>> + dev_priv->mem_freq = 1600;
>>> + break;
>>> + case 3:
>>> + dev_priv->mem_freq = 2000;
>>> + break;
>>> + }
>>>
>>> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>>> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2014-05-27 12:13 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
2014-05-26 8:07 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-26 13:30 ` Mika Kuoppala
2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
2014-05-27 3:29 ` Deepak S
2014-05-26 14:37 ` Mika Kuoppala
2014-05-27 3:29 ` Deepak S
2014-05-27 6:36 ` [PATCH v6] " deepak.s
2014-05-27 10:29 ` [PATCH v7] " deepak.s
2014-05-27 10:45 ` Mika Kuoppala
2014-05-27 11:44 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-26 15:19 ` Mika Kuoppala
2014-05-27 11:42 ` Daniel Vetter
2014-05-27 11:59 ` Ville Syrjälä
2014-05-27 12:11 ` Deepak S
2014-05-27 12:13 ` Deepak S
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s
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